Alinx ZYNQ7000 FPGA User manual

ZYNQ7000 FPGA
Development Board
AX7Z010
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-12-15
Rachel Zhou
First Release

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Table of Contents
Version Record......................................................................................... 2
Part 1: FPGA Development Board Introduction ........................................ 7
Part 2: AC7Z010 core board................................................................... 11
Part 2.1: AC7Z010 core board Introduction ......................................11
Part 2.2: ZYNQ Chip ........................................................................13
Part 2.3: DDR3 DRAM .....................................................................15
Part 2.4: QSPI Flash ........................................................................19
Part 2.5: Clock configuration ............................................................21
Part 2.6: Power Supply.....................................................................21
Part 2.7: AC7Z010 Core Board Size Dimension...............................24
Part 2.8: Board to Board Connectors pin assignment.......................24
Part 3: Carrier Board .............................................................................. 29
Part 3.1: Carrier Board Introduction..................................................29
Part 3.2: CAN communication interface............................................29
Part 3.3: 485 communication interface .............................................31
Part 3.4: Gigabit Ethernet Interface..................................................32
Part 3.5: USB2.0 Host Interface .......................................................34
Part 3.6: USB to Serial Port..............................................................36
Part 3.7: AD input interface ..............................................................37
Part 3.8: HDMI Output Interface.......................................................38
Part 3.9: MIPI camera interface (only for AX7Z020) .........................40
Part 3.10: SD Card Slot Interface.....................................................42
Part 3.11: EEPROM .........................................................................43
Part 3.12: Real-time clock ................................................................44
Part 3.13: Temperature sensor.........................................................45
Part 3.14: JTAG Debug Port.............................................................46
Part 3.15: User LEDs .......................................................................47

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Part 3.16: User Keys........................................................................48
Part 3.17: Expansion Header ...........................................................49
Part 3.18: Power Supply...................................................................52
Part 3.19: Carrier Board Size Dimension..........................................54

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This ZYNQ7000 FPGA development platform adopts the core board +
carrier board mode, which is convenient for users to use the core board for
secondary development. The core board uses XILINX's Zynq7000 SOC chip
XC7Z010 solution, uses ARM+FPGA SOC technology to integrate dual-core
ARM Cortex-A9 and FPGA programmable logic on a single chip. In addition,
the core board contains 2 pieces of 512MB high-speed DDR3 SDRAM chips,
and 1 piece of 256Mb QSPI FLASH chip.
In the design of carrier board, we have extended a wealth of interfaces for
users, such as 1 Gigabit Ethernet interfaces, 1 USB2.0 HOST interface, 1
HDMI output interface, 1 UART USB interface. 1 SD card slot, 2-Channel CAN
bus interfaces, 2-Channel RS485 bus interfaces, 2-Channel AD input interface,
2-Channel 40-pin expansion header, some keys and LEDs. It meets users'
requirements for high-speed Ethernet data exchange, data storage, video
transmission processing and industrial control. It is a "professional" ZYNQ
development platform. For high-speed data transmission and exchange,
pre-verification and post-application of data processing is possible. This
product is very suitable for students, engineers and other groups engaged in
ZYNQ development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AX7Z010 FPGA development board is inherited
from our consistent core board + carrier board model. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of the smallest system of XC7Z010 +
2 DDR3 + QSPI FLASH, which is responsible for the high-speed data
processing and storage functions of the ZYNQ system. The data width between
the ZYNQ 7010 and the two DDR3 chips is 32 bits. The capacity of two DDR3
chips is up to 512MB. ZYNQ7010 uses Xilinx's Zynq7000 series chip, the
model number is XC7Z010-1CLG400I. ZYNQ7010 chip can be divided into
processor system part Processor System (PS) and programmable logic part
Programmable Logic (PL)
The AX7Z010 carrier board expands its rich peripheral interface, including
1 Gigabit Ethernet interfaces, 1 USB2.0 HOST interface, 1 HDMI output
interface, 1 UART USB interface. 1 SD card slot, 2-Channel CAN bus
interfaces, 2-Channel RS485 bus interfaces, 2-Channel AD input interface,
2-Channel 40-pin expansion header, some keys and LEDs.
The following figure shows the structure of the entire development system:

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CP2102
USB UART
JTAG
KSZ9031R
以太网网
口
HDMI输出
40针IO扩展口
USB3320
C
USB接口
TXS02612RT
WR
SD Card
LED & KEY
ZYNQ7000
XC7Z010
/XC7Z020
33.333M
hz
50Mhz
DDR3
DDR3
QSPI
FLASH
核心板
40针IO扩展口
SN65HV
D232
CAN接口
SN65HV
D232
MAX348
5
RS485接口
MAX348
5
EEPROM
Sensor
RTC
AD1AD2
MIPI
接口
Figure 1-1-1: The Schematic Diagram of the AX7Z010
Through this diagram, you can see the interfaces and functions that the
AX7Z010 FPGA Development Board contains:
ZYNQ7000 core board
It consists of XC7Z010 + 512MB DDR3 + 256Mb QSPI FLASH, and a
33.333333MHz crystal oscillator provides the clock to the PS system.
CAN Communication Interface
2 CAN bus interface, using SN65HVD232 chip from TI Company.
485 Communication Interface
2-Channel 485 communication interfaces, using MAX3485 chip of
MAXIM Company.

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Gigabit Ethernet Interface
1-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses Micrel's KSZ9031 industrial grade GPHY chip.
USB 2.0 HOST Interface
It can be used to connect USB peripherals such as mouse, keyboard
and U disk to the development board;
USB Uart Interface
1 port Uart to USB interfaces for communication with the computer, for
user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
Micro SD card slot
1-port Micro SD card holder, use to store operating system images and
file systems.
AD analog input interface
2 AD analog input interfaces, which can be used for analog signal input
and voltage conversion, SMA interface form. Analog signal voltage input
range is 0 ~ 10V (Do not input voltage exceeding this range)
HDMI video input
1 channel HDMI image video input interface, can realize 1080P video
image transmission.
EEPROM
One EEPROM 24LC04 with IIC interface
Temperature and humidity sensor chip LM75
On-board temperature and humidity sensor chip LM75, used to detect
the temperature and humidity of the surrounding environment around
the FPGA development board
1 MIPI camera interface

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It can be used to connect ALINX OV5640 camera with MIPI interface
(only for AX7Z020).
JTAG debug port
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download the ZYNQ system
through the XILINX downloader.
40-pin expansion port
2 40-pin 0.1-inch pitch expansion port can be connected to various
ALINX modules (binocular camera, TFT LCD screen, high-speed AD
module, etc.). The expansion port contains 1-channel 5V power supply,
2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
LED Lights
7 LEDs, include 6 LEDs on the core board, 1 LED on the carrier board.
There is 1 power indicator on the core board, 1 power indicator on the
carrier board. There is 1 power indicator, 1 DONE configuration
indicator, and 4 user indicators on the carrier board.
4 user buttons on the carrier board

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Part 2: AC7Z010 core board
Part 2.1: AC7Z010 core board Introduction
AC7Z010 (core board model, the same below) FPGA core board, ZYNQ
chip is based on XC7Z010-1CLG400I of XILINX company ZYNQ7000 series.
The ZYNQ chip's PS system integrates two ARM CortexTM-A9 processors,
AMBA® interconnects, internal memory, external memory interfaces and
peripherals. The FPGA of the ZYNQ chip contains a wealth of programmable
logic cells, DSP and internal RAM.
This core board uses two Micron's MT41K128M16TW-107 DDR3 chips,
each of which has a capacity of 256MB; the two DDR chips combine to form a
32-bit data bus width, and the clock frequency of read and write data between
ZYNQ and DDR3 Up to 533Mhz; this configuration can meet the needs of the
system's high-bandwidth data processing
In order to connect with the carrier board, the two board-to-board
connectors of this core board are extended with USB ports on the PS side,
Gigabit Ethernet interfaces, SD card slot, and other remaining MIO ports (48).
As well as almost all IO ports (100) of BANK13 (only for AC7Z010), BAN34 and
BANK35 on the PL side, the IO levels of BANK34 and BANK35 can be
provided through the carrier board to meet users' requirements for different
level interfaces. For users who need a lot of IO, this core board will be a good
choice. And the IO connection part, the ZYNQ chip to the interface between the
equal length and differential processing, and the core board size is only 35 * 42
(mm), which is very suitable for secondary development.

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Figure 2-1-1: AC7Z010 Core Board (Front View)
Figure 2-1-2: AC7Z100 Core Board (Rear View)

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Part 2.2: ZYNQ Chip
The FPGA core board AC7Z010 uses Xilinx's Zynq7000 series chip,
module XC7Z010-1CLG400I. The chip's PS system integrates two ARM
Cortex™-A9 processors, AMBA® interconnects, internal memory, external
memory interfaces and peripherals. These peripherals mainly include USB bus
interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus
interface, UART interface, GPIO etc. The PS can operate independently and
start up at power on or reset. Figure 2-2-1 detailed the Overall Block Diagram
of the ZYNQ7000 Chip.
Figure 2-2-1: Overall Block Diagram of the ZYNQ7000 Chip
The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 800MHz
32KB level 1 instruction and data cache per CPU, 512KB level 2 cache
2 CPU shares

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On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3 interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,
SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
4 pairs of 32bit GPIO, 54 (32 + 22) as PS system IO, 64 connected to
PL
High bandwidth connection within PS and PS to PL
The main parameters of the PL logic part are as follows:
Logic Cells: 28K
Look-up-tables (LUTs): 17600
Flip-flops: 35,200
18x25MACCs: 80
 Block RAM : 240KB
Two AD converters for on-chip voltage, temperature sensing and up
to 17 external differential input channels, 1MBPS
XC7Z100-1CLG400I chip speed grade is -1, industrial grade, package is
BGA400, pin pitch is 0.8mm the specific chip model definition of ZYNQ7000
series is shown in Figure 2-2-2

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Figure 2-2-2: The Specific Chip Model Definition of ZYNQ7000 Series
Figure 2-2-3: The XC7Z010 chip used on the Core Board
Part 2.3: DDR3 DRAM
The FPGA core board AC7Z010 is equipped with two Micron DDR3
SDRAM chips (1GB in total), model MT41K128M16TW-107 (Compatible with
Hynix H5TQ2G63AFR-PBI). The total bus width of DDR3 SDRAM is 32bit.
DDR3 SDRAM operates at a maximum speed of 533MHz (data rate

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1066Mbps). The DDR3 memory system is directly connected to the memory
interface of the BANK 502 of the ZYNQ Processing System (PS). The specific
configuration of DDR3 SDRAM is shown in Table 2-3-1 below:
Bit Number
Chip Model
Capacity
Factory
U8,U9
MT41K128M16TW-107
256M x 16bit
Micron
Table 2-3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
The hardware connection of DDR3 DRAM is shown in Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram

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Figure 2-3-2 is the DDR3 DRAM on the core board
DDR3 DRAM pin assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C2
DDR3_DQS0_N
PS_DDR_DQS_N0_502
B2
DDR3_DQS1_P
PS_DDR_DQS_P1_502
G2
DDR3_DQS1_N
PS_DDR_DQS_N1_502
F2
DDR3_DQS2_P
PS_DDR_DQS_P2_502
R2
DDR3_DQS2_N
PS_DDR_DQS_N2_502
T2
DDR3_DQS3_P
PS_DDR_DQS_P3_502
W5
DDR3_DQS4_N
PS_DDR_DQS_N3_502
W4
DDR3_D0
PS_DDR_DQ0_502
C3
DDR3_D1
PS_DDR_DQ1_502
B3
DDR3_D2
PS_DDR_DQ2_502
A2
DDR3_D3
PS_DDR_DQ3_502
A4
DDR3_D4
PS_DDR_DQ4_502
D3
DDR3_D5
PS_DDR_DQ5_502
D1
DDR3_D6
PS_DDR_DQ6_502
C1
DDR3_D7
PS_DDR_DQ7_502
E1
DDR3_D8
PS_DDR_DQ8_502
E2
DDR3_D9
PS_DDR_DQ9_502
E3

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DDR3_D10
PS_DDR_DQ10_502
G3
DDR3_D11
PS_DDR_DQ11_502
H3
DDR3_D12
PS_DDR_DQ12_502
J3
DDR3_D13
PS_DDR_DQ13_502
H2
DDR3_D14
PS_DDR_DQ14_502
H1
DDR3_D15
PS_DDR_DQ15_502
J1
DDR3_D16
PS_DDR_DQ16_502
P1
DDR3_D17
PS_DDR_DQ17_502
P3
DDR3_D18
PS_DDR_DQ18_502
R3
DDR3_D19
PS_DDR_DQ19_502
R1
DDR3_D20
PS_DDR_DQ20_502
T4
DDR3_D21
PS_DDR_DQ21_502
U4
DDR3_D22
PS_DDR_DQ22_502
U2
DDR3_D23
PS_DDR_DQ23_502
U3
DDR3_D24
PS_DDR_DQ24_502
V1
DDR3_D25
PS_DDR_DQ25_502
Y3
DDR3_D26
PS_DDR_DQ26_502
W1
DDR3_D27
PS_DDR_DQ27_502
Y4
DDR3_D28
PS_DDR_DQ28_502
Y2
DDR3_D29
PS_DDR_DQ29_502
W3
DDR3_D30
PS_DDR_DQ30_502
V2
DDR3_D31
PS_DDR_DQ31_502
V3
DDR3_DM0
PS_DDR_DM0_502
A1
DDR3_DM1
PS_DDR_DM1_502
F1
DDR3_DM2
PS_DDR_DM2_502
T1
DDR3_DM3
PS_DDR_DM3_502
Y1
DDR3_A0
PS_DDR_A0_502
N2
DDR3_A1
PS_DDR_A1_502
K2
DDR3_A2
PS_DDR_A2_502
M3
DDR3_A3
PS_DDR_A3_502
K3
DDR3_A4
PS_DDR_A4_502
M4
DDR3_A5
PS_DDR_A5_502
L1
DDR3_A6
PS_DDR_A6_502
L4
DDR3_A7
PS_DDR_A7_502
K4
DDR3_A8
PS_DDR_A8_502
K1
DDR3_A9
PS_DDR_A9_502
J4

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DDR3_A10
PS_DDR_A10_502
F5
DDR3_A11
PS_DDR_A11_502
G4
DDR3_A12
PS_DDR_A12_502
E4
DDR3_A13
PS_DDR_A13_502
D4
DDR3_A14
PS_DDR_A14_502
F4
DDR3_BA0
PS_DDR_BA0_502
L5
DDR3_BA1
PS_DDR_BA1_502
R4
DDR3_BA2
PS_DDR_BA2_502
J5
DDR3_S0
PS_DDR_CS_B_502
N1
DDR3_RAS
PS_DDR_RAS_B_502
P4
DDR3_CAS
PS_DDR_CAS_B_502
P5
DDR3_WE
PS_DDR_WE_B_502
M5
DDR3_ODT
PS_DDR_ODT_502
N5
DDR3_RESET
PS_DDR_DRST_B_502
B4
DDR3_CLK0_P
PS_DDR_CKP_502
L2
DDR3_CLK0_N
PS_DDR_CKN_502
M2
DDR3_CKE
PS_DDR_CKE_502
N3
Part 2.4: QSPI Flash
The FPGA core board AC7Z010 is equipped with one 256MBit Quad-SPI
FLASH chip, the flash model is W25Q256FVEI, which uses the 3.3V CMOS
voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used
as a boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, and other user
data files. The specific models and related parameters of QSPI FLASH are
shown in Table 2-4-1.
Position
Model
Capacity
Factory
U15
W25Q256FVEI
32M Byte
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of

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these PS ports need to be configured as the QSPI FLASH interface. Figure
2-4-1 shows the QSPI Flash in the schematic.
Figure 2-4-1: QSPI Flash in the schematic
Figure 2-4-2 is the QSPI Flash on the core board
Configure chip pin assignments:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
QSPI_SCK
PS_MIO6_500
A5
QSPI_CS
PS_MIO1_500
A7
QSPI_D0
PS_MIO2_500
B8
QSPI_D1
PS_MIO3_500
D6
QSPI_D2
PS_MIO4_500
B7
QSPI_D3
PS_MIO5_500
A6