Alinx ZYNQ7000 FPGA User manual

ZYNQ7000 FPGA
Development Board
AX7015
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-03-31
Rachel Zhou
First Release

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Tabel of Contents
Version Record.........................................................................................................2
Part 1: FPGA Development Board Introduction........................................................6
Part 2: AC7015 Core Board......................................................................................9
Part 2.1: Introduction ................................................................................................9
Part 2.2: ZYNQ Chip...............................................................................................11
Part 2.3: DDR3 DRAM............................................................................................14
Part 2.4: QSPI Flash...............................................................................................17
Part 2.5: eMMC Flash.............................................................................................18
Part 2.6: Clock configuration ..................................................................................19
Part 2.7: USB to Serial Port....................................................................................21
Part 2.8: LED Light .................................................................................................22
Part 2.9: Reset Button ............................................................................................24
Part 2.10: JTAG Interface.......................................................................................25
Part 2.11: DIP switch configuration ........................................................................25
Part 2.12: Power.....................................................................................................26
Part 2.13: Structure diagram ..................................................................................28
Part 2.14: Connector pin definition .........................................................................29
Part 3: Extension Board..........................................................................................36
Part 3.1: Introduction ..............................................................................................36
Part 3.2: Gigabit Ethernet interface ........................................................................37
Part 3.3: USB 2.0 Host Interface ............................................................................41
Part 3.4: HDMI Output Interface .............................................................................43
Part 3.5: HDMI Input Interface................................................................................45
Part 3.6: SFP Interface...........................................................................................47
Part 3.7: PCIe x2 Interface .....................................................................................49
Part 3.8: USB to Serial Port....................................................................................51
Part 3.9: SD Card Slot...........................................................................................52
Part 3.10: JTAG Interface.......................................................................................53
Part 3.11: LED Light ...............................................................................................54
Part 3.12: User Button............................................................................................56
Part 3-13: Expansion Port ......................................................................................57
Part 3.14: Power Supply.........................................................................................58
Part 3.15: Expansion Board Structure diagram ......................................................60

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This ZYNQ7000 FPGA development platform adopts the core board + expansion board
mode, which is convenient for users to use the core board for secondary development. The core
board uses XILINX's Zynq7000 SOC chip XC7Z015 solution, which combines dual-core ARM
Cortex-A9 and FPGA programmable logic on a single chip using ARM+FPGA SOC technology.
In addition, the core board contains 2 pieces of 1GB high-speed DDR3 SDRAM chip, 1 piece
8GB eMMC memory chip and 1 piece 256Mb QSPI FLASH chip.
In the design of the expansion board, it expands the rich peripheral interfaces, such as 1-
port PCIex2 interface, 2-port optical interfaces, 2-port Gigabit Ethernet interfaces, 4-port USB2.0
HOST interfaces, 1-port HDMI input interface, 1-port HDMI output interface, 1-port UART serial
port interface, 1 SD card interface, a 40-pin expansion interface, etc. It meets users'
requirements for high-speed data exchange, data storage, video transmission processing and
industrial control. It is a "professional" ZYNQ development platform. It is applied to high-speed
data transmission and exchange, pre-validation and post-application of data processing. This
product is very suitable for students, engineers and other groups engaged in ZYNQ development.

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Part 1: FPGA Development Board Introduction
Here, a brief introduction to the AX7015 ZYNQ FPGA development platform.
The entire structure of the development board, the core board + expansion
board mode design. A high-speed inter-board connector is used between the core
board and the expansion board.
The core board is mainly composed of the minimum system of ZYNQ7015 + 2
DDR3 + eMMC + QSPI FLASH. It undertakes the high-speed data processing and
storage function of the ZYNQ system. The data width between the ZYNQ7015 and
the two DDR3s is 32 bits, and the two DDR3 capacities up to 1GB. The 8GB
eMMC FLASH memory chip and 256Mb QSPI FLASH are used to statically store
the ZYNQ operating system, file system and user data. Users can select different
startup modes through the DIP switch on the core board. The ZYNQ7015 uses
Xilinx's Zynq7000 series of chips, model number XC7Z015-2CLG485. The
ZYNQ7020 chip can be divided into processor system part Processor System (PS)
and programmable logic part Programmable Logic (PL).
The expansion board expands the rich peripheral interface for the core board,
including 1-port PCIex2 interface, 2-port optical interfaces, 2-port Gigabit Ethernet
interfaces, 4-port USB2.0 HOST interfaces, 1-port HDMI input interface, 1-port
HDMI output interface, 1-port UART serial port interface, 1-port SD card interface,
1-port 40-pin expansion header and some button LEDs.
Figure 1-1-1 is the block diagram of the FPGA development board AX7015:

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Figure 1-1-1: The block diagram of AX7015
The interfaces and features included in the development board:
1-port PCIe x2 Interface
Supports the PCI Express 2.0 standard, and provides a standard PCIe x2
high-speed data transfer interface, for single-channel communication rates up to
5GBaud.
2-port SFP Optical Interface
The 2-chanlle high-speed transceiver of ZYNQ's GTP transceiver, which is
connected to the transmission and reception of two optical modules, to realize
two high-speed optical fiber communication interfaces. Each fiber optic data
communication receives and transmits at speeds up to 6.25 Gb/s.
Gigabit Ethernet Interface
2 channels 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network interface chip
uses Micrel's KSZ9031 industrial grade GPHY chip, one Ethernet connection to the
PS end of the ZYNQ chip, and one Ethernet connections to the PL end of the

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ZYNQ chip.
HDMI Video Output
1-channel HDMI video out interface, selected Silion Image's SIL9134
HDMI encoding chip, supports up to 1080P@60Hz output,
support 3D output.
HDMI Video Input
1-channel HDMI video input interface, selected Silion Image's SIL9013
HDMI decoder chip, supports up to 1080P@60Hz input, supports data input in
different formats.
USB2.0 HOST Interface
The USB Hub chip is used to extend the 4-way USB HOST interface. The 4-
way USB HOST interface is used to connect external USB slave devices, such as
a mouse, keyboard, USB flash drive, etc. The USB interface uses a flat USB
interface (USB Type A).
USB Uart Interface
2-channel Uart to USB interfaces for communication with a computer,
which makes it easy for users to debug.
1-channel Uart to USB interface on the
core board, used when core board working independently. 1-channel Uart to
USB interface on the expansion board, used for when the whole board
debugging.
Micro SD Socket
1-port Micro SD socket used for storing operating system images and file
systems.
40-pin Expansion Header
The 40-pin 2.54mm pitch expansion port use for external ALINX modules
(binocular camera, TFT LCD screen, high-speed AD module, etc.). The expansion
port includes 1 channel of 5V power supply, 2 channels of 3.3V power supply, 3
channels of ground, and 34 channels of IO port.
JTAG Interface

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The 10-pin 2.54mm standard JTAG port used for downloading and debugging
of FPGA programs. Users can debug and download the ZYNQ system through the
XILINX Downloader.
LED Light
10 LEDs, include 4 on the core board and 6 on the extension board. There are
1 power indicator, 1 DONE configuration indicator, 2 user indicators on the core
board. There are 1 power indicator and 5 user indicators on the extension board.
Button
3 buttons, 1 reset button on the core board, and 2 user buttons on the
expansion board.
Part 2: AC7015 Core Board
Part 2.1: Introduction
The AC7015 (core board model, the same below) core board is an FPGA
development board based on the ZynQ chip
XC7Z015-2CLG485I of the XILINX
ZYNQ7000 series. The ZYNQ chip's PS system integrates two ARM CortexTM-A9
processors, AMBA® interconnects, internal memory, external memory interfaces
and peripherals. The ZYNQ FPGA chip contains a wide range of programmable
logic cells, DSP and internal RAM.
The core board uses two SK Hynix DDR3 chips (H5TQ4G63AFR-PBI), each
with a DDR capacity of 4Gbit; two DDR chips form a 32-bit data bus width, and the
read and write data clock frequency between ZYNQ FPGA and DDR3 is up to
533Mhz; such a configuration can meet the system's high bandwidth data
processing needs
In order to connect to the expansion board, the four board-to-board connectors
of the core board extend the USB interface of the PS side, the Gigabit Ethernet
interface, the SD card interface and other remaining MIO ports. Extend ZynQ's 4-
pair high-speed transceiver GTP interface. Almost all IO ports (84) of BANK13,

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BAN34 and BANK35 on the PL side, the level of IO of BANK35 can be modified by
replacing the LDO chip on the core board to meet the requirements of users with
different level interfaces. For users who need a lot of IOs, this core board will be a
good choice. Moreover, the IOs connection part, the routing between the ZYNQ
FPGA chip and the interface is equal length and differential processing. The core
board size is only 60*60 (mm), which is very suitable for secondary development.
Figure 2-1-1: AC7015
Core board Front

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Figure 2-1-2: AC7015 Core Board Rear View
Part 2.2: ZYNQ Chip
The development board uses Xilinx's Zynq7000 series chip, model XC7Z015-
2CLG485I. The chip's PS system integrates two ARM CortexTM-A9 processors,
AMBA® interconnects, internal memory, external memory interfaces and
peripherals. These peripherals mainly include USB bus interface, Ethernet
interface, SD/SDIO interface, I2C bus interface, CAN bus interface, UART interface,
GPIO etc. The PS can operate independently and start up at power up or reset.
Figure 2-2-3 detailed the
Overall Block Diagram of the ZYNQ7000 Chip.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ7000 Chip
The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 1GHz
32KB level 1 instruction and data cache per CPU, 512KB level
2 cache 2 CPU shares
On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3
interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII,
RGMII, SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
4 groups of 32bit GPIO, 54 (32+22) as PS system IO, 64
connected to PL

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High bandwidth connection within PS and PS to PL
The main parameters of the PL logic part are as follows:
LogicCells: 85K
Look-up-tables (LUTs):53,200
Flip-flops:106,400
18x25MACCs：220;

BlockRAM ： 4.9Mb
Two AD converters for on-chip voltage, temperature sensing
and up to 17 external differential input channels, 1MBPS
XC7Z015-2CLG485I chip speed grade is -2, industrial grade, package is
BGA484, pin pitch is 0.8mm, the specific chip model definition of ZYNQ7000 series
is shown in Figure 2-2-2
Figure 2-2-2: The Specific Chip Model Definition of ZYNQ7000 Series

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Figure 2-2-3: TheXC7Z020 chip used on the Core Board
Part 2.3: DDR3 DRAM
The AC7015 core board is equipped with two SK Hynix DDR3 SDRAM chips (1GB total),
model H5TQ4G63AFR-PBI. The bus width of DDR3 SDRAM is 32 bits in total. DDR3 SDRAM
has a maximum operating speed of 533MHz (data rate 1066Mbps). The DDR3 memory system
is directly connected to the memory interface of the BANK 502 of the ZYNQ Processing System
(PS). The specific configuration of DDR3 SDRAM is shown in Table 2-3-1
Table 2-3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal integrity.
We have fully considered the matching resistor/terminal resistance, trace
impedance control, and trace length control in circuit design and PCB design to
ensure high-speed and stable operation of DDR3.
The hardware connection of DDR3 DRAM is shown in Figure 2-3-1:
Bit Number Chip Model Capacity Factory
U5,U6 H5TQ4G63AFR-PBI 256M x 16bit SK Hynix

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Figure 2-3-1: The Schematic part of DDR3 DRAM
Figure 2-3-2: DDR3 DRAM on the Core Board
DDR3 DRAM Pin Assignment
Signal Name
ZYNQ Pin Name
Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C21
DDR3_DQS0_N
PS_DDR_DQS_N0_502
D21
DDR3_DQS1_P
PS_DDR_DQS_P1_502
H21
DDR3_DQS1_N
PS_DDR_DQS_N1_502
J21
DDR3_DQS2_P
PS_DDR_DQS_P2_502
N21
DDR3_DQS2_N
PS_DDR_DQS_N2_502
P21
DDR3_DQS3_P
PS_DDR_DQS_P3_502
V21
DDR3_DQS4_N
PS_DDR_DQS_N3_502
W21
DDR3_D0
PS_DDR_DQ0_502
D12
DDR3_D1
PS_DDR_DQ1_502
C20
DDR3_D2
PS_DDR_DQ2_502
B21
DDR3_D3
PS_DDR_DQ3_502
D20

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DDR3_D4
PS_DDR_DQ4_502
E20
DDR3_D5
PS_DDR_DQ5_502
E22
DDR3_D6
PS_DDR_DQ6_502
F21
DDR3_D7
PS_DDR_DQ7_502
F22
DDR3_D8
PS_DDR_DQ8_502
G21
DDR3_D9
PS_DDR_DQ9_502
G22
DDR3_D10
PS_DDR_DQ10_502
L22
DDR3_D11
PS_DDR_DQ11_502
L21
DDR3_D12
PS_DDR_DQ12_502
L20
DDR3_D13
PS_DDR_DQ13_502
K22
DDR3_D14
PS_DDR_DQ14_502
J22
DDR3_D15
PS_DDR_DQ15_502
K20
DDR3_D16
PS_DDR_DQ16_502
M22
DDR3_D17
PS_DDR_DQ17_502
T20
DDR3_D18
PS_DDR_DQ18_502
N20
DDR3_D19
PS_DDR_DQ19_502
T22
DDR3_D20
PS_DDR_DQ20_502
R20
DDR3_D21
PS_DDR_DQ21_502
T21
DDR3_D22
PS_DDR_DQ22_502
M21
DDR3_D23
PS_DDR_DQ23_502
R22
DDR3_D24
PS_DDR_DQ24_502
A20
DDR3_D25
PS_DDR_DQ25_502
U22
DDR3_D26
PS_DDR_DQ26_502
AA22
DDR3_D27
PS_DDR_DQ27_502
U21
DDR3_D28
PS_DDR_DQ28_502
W22
DDR3_D29
PS_DDR_DQ29_502
W20
DDR3_D30
PS_DDR_DQ30_502
V20
DDR3_D31
PS_DDR_DQ31_502
Y22
DDR3_DM0
PS_DDR_DM0_502
B22
DDR3_DM1
PS_DDR_DM1_502
H20
DDR3_DM2
PS_DDR_DM2_502
P22
DDR3_DM3
PS_DDR_DM3_502
AA21
DDR3_A0
PS_DDR_A0_502
M19
DDR3_A1
PS_DDR_A1_502
M18
DDR3_A2
PS_DDR_A2_502
K19
DDR3_A3
PS_DDR_A3_502
L19
DDR3_A4
PS_DDR_A4_502
K17
DDR3_A5
PS_DDR_A5_502
K18
DDR3_A6
PS_DDR_A6_502
J16
DDR3_A7
PS_DDR_A7_502
J17
DDR3_A8
PS_DDR_A8_502
J18
DDR3_A9
PS_DDR_A9_502
H18
DDR3_A10
PS_DDR_A10_502
J20
DDR3_A11
PS_DDR_A11_502
G18
DDR3_A12
PS_DDR_A12_502
H19
DDR3_A13
PS_DDR_A13_502
F19
DDR3_A14
PS_DDR_A14_502
G19
DDR3_BA0
PS_DDR_BA0_502
L16
DDR3_BA1
PS_DDR_BA1_502
L17
DDR3_BA2
PS_DDR_BA2_502
M17
DDR3_S0
PS_DDR_CS_B_502
P17
DDR3_RAS
PS_DDR_RAS_B_502
R18
DDR3_CAS
PS_DDR_CAS_B_502
P20

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DDR3_WE
PS_DDR_WE_B_502
R19
DDR3_ODT
PS_DDR_ODT_502
P18
DDR3_RESET
PS_DDR_DRST_B_502
F20
DDR3_CLK0_P
PS_DDR_CKP_502
N19
DDR3_CLK0_N
PS_DDR_CKN_502
N18
DDR3_CKE
PS_DDR_CKE_502
T19
Table 2-3-2: DDR3 DRAM Pin Assignment
Part 2.4: QSPI Flash
The core board is equipped with a 256MBit Quad-SPI FLASH chip, model
W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-
volatile nature of QSPI FLASH, it can be used as a boot device for the system to
store the boot image of the system. These images mainly include FPGA bit files,
ARM application code, and other user data files. The specific models and related
parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U7
W25Q256FVEI
32M Byte
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS section
of the ZYNQ chip. In the system design, the GPIO port functions of these PS ports
need to be configured as the QSPI FLASH interface. Figure 2-4-1 shows the QSPI
Flash in the schematic.
ZYNQ QSPI FLASH
(W25Q256F)
QSPI_CS
U7
U1
BANK
500
QSPI_SCK
QSPI_D0~QSPI_D3
Figure 2-4-1: QSPI Flash in the schematic

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Figure 2-4-2: QSPI Flash on the Core Board
Pin Assignment of QSPI Flash
Signal Name
ZYNQ Pin Name
Pin Number
QSPI_SCK
PS_MIO6_500
A19
QSPI_CS
PS_MIO1_500
A22
QSPI_D0
PS_MIO2_500
A21
QSPI_D1
PS_MIO3_500
F17
QSPI_D2
PS_MIO4_500
E19
QSPI_D3
PS_MIO5_500
A20
Table 2-4-2: Pin Assignment of QSPI FLASH
Part 2.5: eMMC Flash
The core board is equipped with a large capacity 8GB eMMC FLASH chip,
model THGBMFG6C1LBAIL, which supports the JEDEC e-MMC V5.0 standard
HS-MMC interface with level support of 1.8V or 3.3V. The data width of the eMMC
FLASH and ZYNQ connections is 4 bits. Due to the large capacity and non-volatile
nature of eMMC FLASH, it can be used as a large-capacity storage device for the
ZYNQ system, such as ARM-based applications, system files, and other user data
files. The specific models and related parameters of eMMC FLASH are shown in
Table 2-5-1：
Position
Model
Capacity
Factory
U33
THGBMFG6C1LBAIL
8G Byte
TOSHIBA
Table 2-5-1: eMMC FLASH Specification
eMMC FLASH is connected to the GPIO port of the BANK501 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of these

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PS ports need to be configured as the SD interface. Figure 2-5-1 shows the eMMC
Flash in the schematic.
ZYNQ
eMMC
(THGBMFG8C2
LBAIL)
MMC_CCLK
U33
U1
BANK
501
MMC_CMD
MMC_DAT0~MMC_DAT3
Figure 2-5-1: eMMC Flash in the Schematic
Figure 2-5-2: eMMC Flash on the Core Board
Pin Assignment of eMMC Flash
Signal Name
ZYNQ Pin Name
Pin Number
MMC_CCLK
PS_MIO48_501
D12
MMC_CMD
PS_MIO47_501
B13
MMC_D0
PS_MIO46_501
D11
MMC_D1
PS_MIO49_501
C9
MMC_D2
PS_MIO50_501
D10
MMC_D3
PS_MIO51_501
C13
Table 2-5-2: Pin Assignment of eMMC FLASH
Part 2.6: Clock configuration
The AC7015 core board provides active clocks for the PS system and the PL

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logic sections, respectively, so that the PS system and the PL logic can work
independently.
PS system clock source
The ZYNQ chip provides a 33.333 MHz clock input to the PS section through
the X1 crystal on the development board. The input of the clock is connected to the
pins of PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic diagram is
shown in Figure 2-6-1:
Figure 2-6-1: Active crystal oscillator to the PS section
Figure 2-6-2: 33.333Mhz active Crystal Oscillator on the Core Board
PS Clock pin assignment:
Signal Name
ZYNQ Pin
PS_GCLK
F16
Table 2-6-1: PS Clock pin assignment
PL system clock source
The AC7015 core board provides a single-ended 125MHz PL system clock
source with 3.3V power supply. The crystal output is connected to the global clock
(MRCC) of the FPGA BANK13, which can be used to drive user logic within the