Alinx ACU7EVB User manual

ZYNQ UltraScale+ FPGA
Core Board
ACU7EVB
User Manual

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Version Record
Version
Date
Description
Rev 1.0
2022-08-30
First Release

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CONTENTS
Version Record .............................................................................................2
Part 1: ACU7EVB Core Board ..................................................................... 4
Part 1.1: ACU7EVB Core Board Introduction ..............................................4
Part 1.2: ZYNQ Chip .................................................................................... 5
Part 1.3: DDR4 DRAM ................................................................................. 7
Part 1.4: QSPI Flash .................................................................................. 16
Part 1.5: eMMC Flash ................................................................................ 17
Part 1.6: Clock configuration ......................................................................19
Part 1.7: Power Supply .............................................................................. 19
Part 1.8: ACU7EVB Core Board Size Dimension ..................................... 21
Part 1.9: Board to Board Connectors pin assignment .............................. 21

ZYNQ Ultrascale + FPGA Core Board ACU7EVB User Manual
Part 1: ACU7EVB Core Board
Part 1.1: ACU7EVB Core Board Introduction
ACU7EVB (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU7EV-2FFVB1156I of XILINX company Zynq UltraScale+
MPSoCs EG Family.
This core board uses 8 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. 4 DDR4 chip is mounted on the PL end, which is a 64-bit
data bus width and a capacity of 4GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1200MHz
(data rate 2400Mbps). In addition, two 256MBit QSPI FLASH and an 8GB
eMMC FLASH chip are also integrated on the core board to start storage
configuration and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and 16 GTH
transceivers and almost all IO ports on the PL side (HP I/O: 143, HD I/O: 46).
The wiring between the XCZU7EV chip and the interface has been processed
with equal length and differential, and the core board size is only 3.15*2.36
(inch), which is very suitable for secondary development.

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Figure 2-1-1: ACU7EVB Core Board (Front View)
Part 1.2: ZYNQ Chip
The FPGA core board ACU7EVB uses Xilinx's Zynq UltraScale+ MPSoCs
EV family chip, module XCZU7EV-2FFVB1156I. The PS system of the ZU7EV
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.3Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 533Mhz
The ZU7EV chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0, Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-2-1 detailed the Overall Block Diagram of the ZU7EV Chip.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU7EV Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.3GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
Image video processor Mali-400 MP2, speed up to 677MHz, 64KB
level 2 cache.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface

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Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/Low/PL/Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 504K
CLB Flip-flops: 460.8K
Look-up-tables (LUTs): 230.4K
 Block RAM : 11Mb
Clock Management Units (CMTs): 8
 DSP Slices: 1728
Part 1.3: DDR4 DRAM
The ACU7EVB core board is equipped with 8 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Four DDR4
chip is mounted on the PL end, which is a 64-bit data bus width and a capacity
of 4GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and four piece of DDR4 is connected to the

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BANK66,67,68 interface of the FPGA. The specific configuration of DDR4
SDRAM is shown in Table 2-3-1 below:
Position
Bit Number
Chip Model
Capacity
Factory
PS
U4,U5,U6,U7
MT40A512M16LY-062E
512M x 16bit
Micron
PL
U17,U19,U45,U46
MT40A512M16LY-062E
512M x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the PL Side is shown in
Figure 2-3-2:

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Figure 2-3-2: DDR4 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AN27
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AN26
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AP30
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AN29
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AJ26
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AH26
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AK29
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AK28
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
AD31
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
AD30
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
Y28
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
Y27
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
AB34
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
AB33
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
W32
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
W31

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PS_DDR4_DQ0
PS_DDR_DQ0_504
AP27
PS_DDR4_DQ1
PS_DDR_DQ1_504
AP25
PS_DDR4_DQ2
PS_DDR_DQ2_504
AP26
PS_DDR4_DQ3
PS_DDR_DQ3_504
AM26
PS_DDR4_DQ4
PS_DDR_DQ4_504
AP24
PS_DDR4_DQ5
PS_DDR_DQ5_504
AL25
PS_DDR4_DQ6
PS_DDR_DQ6_504
AM25
PS_DDR4_DQ7
PS_DDR_DQ7_504
AM24
PS_DDR4_DQ8
PS_DDR_DQ8_504
AM28
PS_DDR4_DQ9
PS_DDR_DQ9_504
AN28
PS_DDR4_DQ10
PS_DDR_DQ10_504
AP29
PS_DDR4_DQ11
PS_DDR_DQ11_504
AP28
PS_DDR4_DQ12
PS_DDR_DQ12_504
AM31
PS_DDR4_DQ13
PS_DDR_DQ13_504
AP31
PS_DDR4_DQ14
PS_DDR_DQ14_504
AN31
PS_DDR4_DQ15
PS_DDR_DQ15_504
AM30
PS_DDR4_DQ16
PS_DDR_DQ16_504
AF25
PS_DDR4_DQ17
PS_DDR_DQ17_504
AG25
PS_DDR4_DQ18
PS_DDR_DQ18_504
AG26
PS_DDR4_DQ19
PS_DDR_DQ19_504
AJ25
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG24
PS_DDR4_DQ21
PS_DDR_DQ21_504
AK25
PS_DDR4_DQ22
PS_DDR_DQ22_504
AJ24
PS_DDR4_DQ23
PS_DDR_DQ23_504
AK24
PS_DDR4_DQ24
PS_DDR_DQ24_504
AH28
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH27
PS_DDR4_DQ26
PS_DDR_DQ26_504
AJ27
PS_DDR4_DQ27
PS_DDR_DQ27_504
AK27
PS_DDR4_DQ28
PS_DDR_DQ28_504
AL26
PS_DDR4_DQ29
PS_DDR_DQ29_504
AL27
PS_DDR4_DQ30
PS_DDR_DQ30_504
AH29
PS_DDR4_DQ31
PS_DDR_DQ31_504
AL28
PS_DDR4_DQ32
PS_DDR_DQ32_504
AB29
PS_DDR4_DQ33
PS_DDR_DQ33_504
AB30
PS_DDR4_DQ34
PS_DDR_DQ34_504
AC29
PS_DDR4_DQ35
PS_DDR_DQ35_504
AD32

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PS_DDR4_DQ36
PS_DDR_DQ36_504
AC31
PS_DDR4_DQ37
PS_DDR_DQ37_504
AE30
PS_DDR4_DQ38
PS_DDR_DQ38_504
AC28
PS_DDR4_DQ39
PS_DDR_DQ39_504
AE29
PS_DDR4_DQ40
PS_DDR_DQ40_504
AC27
PS_DDR4_DQ41
PS_DDR_DQ41_504
AA27
PS_DDR4_DQ42
PS_DDR_DQ42_504
AA28
PS_DDR4_DQ43
PS_DDR_DQ43_504
AB28
PS_DDR4_DQ44
PS_DDR_DQ44_504
W27
PS_DDR4_DQ45
PS_DDR_DQ45_504
W29
PS_DDR4_DQ46
PS_DDR_DQ46_504
W28
PS_DDR4_DQ47
PS_DDR_DQ47_504
V27
PS_DDR4_DQ48
PS_DDR_DQ48_504
AA32
PS_DDR4_DQ49
PS_DDR_DQ49_504
AA33
PS_DDR4_DQ50
PS_DDR_DQ50_504
AA34
PS_DDR4_DQ51
PS_DDR_DQ51_504
AE34
PS_DDR4_DQ52
PS_DDR_DQ52_504
AD34
PS_DDR4_DQ53
PS_DDR_DQ53_504
AB31
PS_DDR4_DQ54
PS_DDR_DQ54_504
AC34
PS_DDR4_DQ55
PS_DDR_DQ55_504
AC33
PS_DDR4_DQ56
PS_DDR_DQ56_504
AA30
PS_DDR4_DQ57
PS_DDR_DQ57_504
Y30
PS_DDR4_DQ58
PS_DDR_DQ58_504
AA31
PS_DDR4_DQ59
PS_DDR_DQ59_504
W30
PS_DDR4_DQ60
PS_DDR_DQ60_504
Y33
PS_DDR4_DQ61
PS_DDR_DQ61_504
W33
PS_DDR4_DQ62
PS_DDR_DQ62_504
W34
PS_DDR4_DQ63
PS_DDR_DQ63_504
Y34
PS_DDR4_DM0
PS_DDR_DM0_504
AN24
PS_DDR4_DM1
PS_DDR_DM1_504
AM29
PS_DDR4_DM2
PS_DDR_DM2_504
AH24
PS_DDR4_DM3
PS_DDR_DM3_504
AJ29
PS_DDR4_DM4
PS_DDR_DM4_504
AD29
PS_DDR4_DM5
PS_DDR_DM5_504
Y29
PS_DDR4_DM6
PS_DDR_DM6_504
AC32
PS_DDR4_DM7
PS_DDR_DM7_504
Y32

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PL Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PL_DDR4_DQS0_N
IO_L10N_T1U_N7_QBC_AD4N_67
F13
PL_DDR4_DQS0_P
IO_L10P_T1U_N6_QBC_AD4P_67
G14
PL_DDR4_DQS1_N
IO_L4N_T0U_N7_DBC_AD7N_67
B13
PS_DDR4_A0
PS_DDR_A0_504
AN34
PS_DDR4_A1
PS_DDR_A1_504
AM34
PS_DDR4_A2
PS_DDR_A2_504
AM33
PS_DDR4_A3
PS_DDR_A3_504
AL34
PS_DDR4_A4
PS_DDR_A4_504
AL33
PS_DDR4_A5
PS_DDR_A5_504
AK33
PS_DDR4_A6
PS_DDR_A6_504
AK30
PS_DDR4_A7
PS_DDR_A7_504
AJ30
PS_DDR4_A8
PS_DDR_A8_504
AJ31
PS_DDR4_A9
PS_DDR_A9_504
AH31
PS_DDR4_A10
PS_DDR_A10_504
AG31
PS_DDR4_A11
PS_DDR_A11_504
AF31
PS_DDR4_A12
PS_DDR_A12_504
AG30
PS_DDR4_A13
PS_DDR_A13_504
AF30
PS_DDR4_ODT0
PS_DDR_ODT0_504
AP32
PS_DDR4_PARITY
PS_DDR_PARITY_504
AA26
PS_DDR4_RAS_B
PS_DDR_A16_504
AF28
PS_DDR4_RESET_B
PS_DDR_RAM_RST_N_504
AD26
PS_DDR4_WE_B
PS_DDR_A14_504
AG29
PS_DDR4_ACT_B
PS_DDR_ACT_N_504
AE25
PS_DDR4_ALERT_B
PS_DDR_ALERT_N_504
AB26
PS_DDR4_BA0
PS_DDR_BA0_504
AE27
PS_DDR4_BA1
PS_DDR_BA1_504
AE28
PS_DDR4_BG0
PS_DDR_BG0_504
AD27
PS_DDR4_CAS_B
PS_DDR_A15_504
AG28
PS_DDR4_CKE0
PS_DDR_CKE0_504
AN33
PS_DDR4_CS0_B
PS_DDR_CS_N0_504
AP33
PS_DDR4_CLK0_N
PS_DDR_CK_N0_504
AN32
PS_DDR4_CLK0_P
PS_DDR_CK0_504
AL31

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PL_DDR4_DQS1_P
IO_L4P_T0U_N6_DBC_AD7P_67
B14
PL_DDR4_DQS2_N
IO_L16N_T2U_N7_QBC_AD3N_67
H17
PL_DDR4_DQS2_P
IO_L16P_T2U_N6_QBC_AD3P_67
H18
PL_DDR4_DQS3_N
IO_L22N_T3U_N7_DBC_AD0N_67
K15
PL_DDR4_DQS3_P
IO_L22P_T3U_N6_DBC_AD0P_67
L15
PL_DDR4_DQS4_N
IO_L16N_T2U_N7_QBC_AD3N_68
D10
PL_DDR4_DQS4_P
IO_L16P_T2U_N6_QBC_AD3P_68
D11
PL_DDR4_DQS5_N
IO_L22N_T3U_N7_DBC_AD0N_68
A10
PL_DDR4_DQS5_P
IO_L22P_T3U_N6_DBC_AD0P_68
B10
PL_DDR4_DQS6_N
IO_L10N_T1U_N7_QBC_AD4N_68
D9
PL_DDR4_DQS6_P
IO_L10P_T1U_N6_QBC_AD4P_68
E9
PL_DDR4_DQS7_N
IO_L4N_T0U_N7_DBC_AD7N_68
J11
PL_DDR4_DQS7_P
IO_L4P_T0U_N6_DBC_AD7P_68
K12
PL_DDR4_DQ0
IO_L9N_T1L_N5_AD12N_67
E17
PL_DDR4_DQ1
IO_L11P_T1U_N8_GC_67
D15
PL_DDR4_DQ2
IO_L8P_T1L_N2_AD5P_67
D17
PL_DDR4_DQ3
IO_L12N_T1U_N11_GC_67
E14
PL_DDR4_DQ4
IO_L9P_T1L_N4_AD12P_67
E18
PL_DDR4_DQ5
IO_L11N_T1U_N9_GC_67
D14
PL_DDR4_DQ6
IO_L12P_T1U_N10_GC_67
E15
PL_DDR4_DQ7
IO_L8N_T1L_N3_AD5N_67
C17
PL_DDR4_DQ8
IO_L2P_T0L_N2_67
B16
PL_DDR4_DQ9
IO_L6P_T0U_N10_AD6P_67
C13
PL_DDR4_DQ10
IO_L3P_T0L_N4_AD15P_67
A15
PL_DDR4_DQ11
IO_L5P_T0U_N8_AD14P_67
A13
PL_DDR4_DQ12
IO_L2N_T0L_N3_67
B15
PL_DDR4_DQ13
IO_L5N_T0U_N9_AD14N_67
A12
PL_DDR4_DQ14
IO_L3N_T0L_N5_AD15N_67
A14
PL_DDR4_DQ15
IO_L6N_T0U_N11_AD6N_67
C12
PL_DDR4_DQ16
IO_L15P_T2L_N4_AD11P_67
H19
PL_DDR4_DQ17
IO_L18P_T2U_N10_AD2P_67
H16
PL_DDR4_DQ18
IO_L17P_T2U_N8_AD10P_67
G18
PL_DDR4_DQ19
IO_L18N_T2U_N11_AD2N_67
G16
PL_DDR4_DQ20
IO_L15N_T2L_N5_AD11N_67
G19
PL_DDR4_DQ21
IO_L14N_T2L_N3_GC_67
F15
PL_DDR4_DQ22
IO_L17N_T2U_N9_AD10N_67
F18

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PL_DDR4_DQ23
IO_L14P_T2L_N2_GC_67
G15
PL_DDR4_DQ24
IO_L24N_T3U_N11_67
L16
PL_DDR4_DQ25
IO_L21N_T3L_N5_AD8N_67
J17
PL_DDR4_DQ26
IO_L23P_T3U_N8_67
K19
PL_DDR4_DQ27
IO_L21P_T3L_N4_AD8P_67
K17
PL_DDR4_DQ28
IO_L24P_T3U_N10_67
L17
PL_DDR4_DQ29
IO_L20P_T3L_N2_AD1P_67
J16
PL_DDR4_DQ30
IO_L23N_T3U_N9_67
K18
PL_DDR4_DQ31
IO_L20N_T3L_N3_AD1N_67
J15
PL_DDR4_DQ32
IO_L18N_T2U_N11_AD2N_68
C11
PL_DDR4_DQ33
IO_L17P_T2U_N8_AD10P_68
F12
PL_DDR4_DQ34
IO_L17N_T2U_N9_AD10N_68
E12
PL_DDR4_DQ35
IO_L14P_T2L_N2_GC_68
F11
PL_DDR4_DQ36
IO_L18P_T2U_N10_AD2P_68
D12
PL_DDR4_DQ37
IO_L15N_T2L_N5_AD11N_68
H12
PL_DDR4_DQ38
IO_L15P_T2L_N4_AD11P_68
H13
PL_DDR4_DQ39
IO_L14N_T2L_N3_GC_68
E10
PL_DDR4_DQ40
IO_L20N_T3L_N3_AD1N_68
B8
PL_DDR4_DQ41
IO_L21N_T3L_N5_AD8N_68
A6
PL_DDR4_DQ42
IO_L20P_T3L_N2_AD1P_68
B9
PL_DDR4_DQ43
IO_L23N_T3U_N9_68
A7
PL_DDR4_DQ44
IO_L24P_T3U_N10_68
B11
PL_DDR4_DQ45
IO_L21P_T3L_N4_AD8P_68
B6
PL_DDR4_DQ46
IO_L24N_T3U_N11_68
A11
PL_DDR4_DQ47
IO_L23P_T3U_N8_68
A8
PL_DDR4_DQ48
IO_L12P_T1U_N10_GC_68
G10
PL_DDR4_DQ49
IO_L9P_T1L_N4_AD12P_68
F8
PL_DDR4_DQ50
IO_L8N_T1L_N3_AD5N_68
C8
PL_DDR4_DQ51
IO_L9N_T1L_N5_AD12N_68
E8
PL_DDR4_DQ52
IO_L12N_T1U_N11_GC_68
F10
PL_DDR4_DQ53
IO_L11P_T1U_N8_GC_68
H9
PL_DDR4_DQ54
IO_L8P_T1L_N2_AD5P_68
C9
PL_DDR4_DQ55
IO_L11N_T1U_N9_GC_68
G9
PL_DDR4_DQ56
IO_L5N_T0U_N9_AD14N_68
J14
PL_DDR4_DQ57
IO_L6N_T0U_N11_AD6N_68
K13
PL_DDR4_DQ58
IO_L5P_T0U_N8_AD14P_68
K14

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PL_DDR4_DQ59
IO_L2P_T0L_N2_68
K10
PL_DDR4_DQ60
IO_L6P_T0U_N10_AD6P_68
L14
PL_DDR4_DQ61
IO_L3P_T0L_N4_AD15P_68
L12
PL_DDR4_DQ62
IO_L2N_T0L_N3_68
J10
PL_DDR4_DQ63
IO_L3N_T0L_N5_AD15N_68
L11
PL_DDR4_DM0
IO_L7P_T1L_N0_QBC_AD13P_67
D16
PL_DDR4_DM1
IO_L1P_T0L_N0_DBC_67
A17
PL_DDR4_DM2
IO_L13P_T2L_N0_GC_QBC_67
F17
PL_DDR4_DM3
IO_L19P_T3L_N0_DBC_AD9P_67
L20
PL_DDR4_DM4
IO_L13P_T2L_N0_GC_QBC_68
H11
PL_DDR4_DM5
IO_L19P_T3L_N0_DBC_AD9P_68
C7
PL_DDR4_DM6
IO_L7P_T1L_N0_QBC_AD13P_68
F7
PL_DDR4_DM7
IO_L1P_T0L_N0_DBC_68
M13
PL_DDR4_A0
IO_L10P_T1U_N6_QBC_AD4P_66
AK8
PL_DDR4_A1
IO_L6P_T0U_N10_AD6P_66
AM9
PL_DDR4_A2
IO_L10N_T1U_N7_QBC_AD4N_66
AL8
PL_DDR4_A3
IO_L5N_T0U_N9_AD14N_66
AM10
PL_DDR4_A4
IO_L11N_T1U_N9_GC_66
AK10
PL_DDR4_A5
IO_L3N_T0L_N5_AD15N_66
AP11
PL_DDR4_A6
IO_L14N_T2L_N3_GC_66
AJ11
PL_DDR4_A7
IO_L4P_T0U_N6_DBC_AD7P_66
AN9
PL_DDR4_A8
IO_L17N_T2U_N9_AD10N_66
AG10
PL_DDR4_A9
IO_L6N_T0U_N11_AD6N_66
AM8
PL_DDR4_A10
IO_L11P_T1U_N8_GC_66
AJ10
PL_DDR4_A11
IO_L5P_T0U_N8_AD14P_66
AM11
PL_DDR4_A12
IO_L9N_T1L_N5_AD12N_66
AL12
PL_DDR4_A13
IO_L4N_T0U_N7_DBC_AD7N_66
AN8
PL_DDR4_ODT
IO_L16P_T2U_N6_QBC_AD3P_66
AG9
PL_DDR4_RAS_B
IO_L8P_T1L_N2_AD5P_66
AL11
PL_DDR4_RST
IO_L14P_T2L_N2_GC_66
AH11
PL_DDR4_WE_B
IO_L15N_T2L_N5_AD11N_66
AH13
PL_DDR4_ACT_B
IO_L16N_T2U_N7_QBC_AD3N_66
AH9
PL_DDR4_BA0
IO_L7N_T1L_N1_QBC_AD13N_66
AL13
PL_DDR4_BA1
IO_L3P_T0L_N4_AD15P_66
AN11
PL_DDR4_BG0
IO_L7P_T1L_N0_QBC_AD13P_66
AK13
PL_DDR4_CAS_B
IO_L8N_T1L_N3_AD5N_66
AL10

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PL_DDR4_CKE
IO_L15P_T2L_N4_AD11P_66
AG13
PL_DDR4_CS_B
IO_L9P_T1L_N4_AD12P_66
AK12
PL_DDR4_CLK_N
IO_L13N_T2L_N1_GC_QBC_66
AJ12
PL_DDR4_CLK_P
IO_L13P_T2L_N0_GC_QBC_66
AH12
Part 1.4: QSPI Flash
The FPGA core board ACU7EVB is equipped with two 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
Model
Capacity
Factory
U2, U3
MT25QU256ABA1EW9
256Mbit
Winbond
Table 2-4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure
2-4-1 shows the QSPI Flash in the schematic.

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Figure 2-4-1: QSPI Flash in the schematic
Configure chip pin assignments:
Signal Name
Pin Name
Pin Number
MIO0_QSPI0_SCLK
PS_MIO0_500
A24
MIO1_QSPI0_IO1
PS_MIO1_500
C24
MIO2_QSPI0_IO2
PS_MIO2_500
B24
MIO3_QSPI0_IO3
PS_MIO3_500
E25
MIO4_QSPI0_IO0
PS_MIO4_500
A25
MIO5_QSPI0_SS_B
PS_MIO5_500
D25
MIO10_QSPI1_IO2
PS_MIO10_500
F26
MIO11_QSPI1_IO3
PS_MIO11_500
B26
MIO12_QSPI1_SCLK
PS_MIO12_500
C27
MIO7_QSPI1_SS_B
PS_MIO7_500
B25
MIO8_QSPI1_IO0
PS_MIO8_500
D26
MIO9_QSPI1_IO1
PS_MIO9_500
C26
Part 1.5: eMMC Flash
The ACU7EVB core board is equipped with a large-capacity 8GB eMMC

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FLASH chip, the model is MTFC8GAKAJCN-4M, it supports the HS-MMC
interface of the JEDEC e-MMC V5.0 standard, and the level supports 1.8V or
3.3V. The data width of eMMC FLASH and ZYNQ connection is 8bit. Due to the
large-capacity and non-volatile characteristics of eMMC FLASH, it can be used
as a large-capacity storage device in the ZYNQ system, such as storing ARM
applications, system files and other user data files The specific models and
related parameters of eMMC FLASH are shown in Table 2-5-1.
Position
Model
Capacity
Factory
U19
MTFC8GAKAJCN-4M
8G Byte
Micron
Table 2-5-1: eMMC FLASH Specification
The eMMC FLASH is connected to the GPIO port of the BANK500 of the
PS part of the ZYNQ UltraScale+. In the system design, it is necessary to
configure the GPIO port function of the PS side as an EMMC interface. Figure
2-5-1 shows the part of eMMC Flash in the schematic diagram.
Figure 2-5-1: eMMC Flash in the schematic
Configuration Chip pin assignment:
Signal Name
Pin Name
Pin Number
MMC_CCLK
PS_MIO22_500
F28
MMC_CMD
PS_MIO21_500
C28
MMC_DAT0
PS_MIO13_500
D27

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MMC_DAT1
PS_MIO14_500
A27
MMC_DAT2
PS_MIO15_500
E27
MMC_DAT3
PS_MIO16_500
A28
MMC_DAT4
PS_MIO17_500
C29
MMC_DAT5
PS_MIO18_500
F27
MMC_DAT6
PS_MIO19_500
B28
MMC_DAT7
PS_MIO20_500
E29
MMC_RSTN
PS_MIO23_500
B29
Part 1.6: Clock configuration
The core board provides reference clock and RTC real-time clock for PS
system and PL logic respectively, so that PS system and PL logic can work
independently. The schematic diagram of the clock circuit design is shown in
Figure 2-6-1:
Figure 2-6-1: Core Board Clock Source
Part 1.7: Power Supply
The power supply voltage of the ACU7EVB core board is DC12V, which is
supplied by connecting the carrier board. The core board uses 2
MYMGM1R824 power chips in parallel to achieve a 50A current to provide the

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core power of the XCZU7EV with 0.85V. In addition, a PMIC chip TPS6508640
is used to generate all other power supplies required by the XCZU7EV chip.
For the TPS6508640 power supply design, please refer to the power supply
chip manual. The design block diagram is as follows :