Alinx ACU7EVB User manual

ZYNQ UltraScale+ FPGA
Core Board
ACU7EVB
User Manual

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Version Record
Version
Date
Description
Rev 1.0
2022-08-30
First Release

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CONTENTS
Version Record .............................................................................................2
Part 1: ACU7EVB Core Board ..................................................................... 4
Part 1.1: ACU7EVB Core Board Introduction ..............................................4
Part 1.2: ZYNQ Chip .................................................................................... 5
Part 1.3: DDR4 DRAM ................................................................................. 7
Part 1.4: QSPI Flash .................................................................................. 16
Part 1.5: eMMC Flash ................................................................................ 17
Part 1.6: Clock configuration ......................................................................19
Part 1.7: Power Supply .............................................................................. 19
Part 1.8: ACU7EVB Core Board Size Dimension ..................................... 21
Part 1.9: Board to Board Connectors pin assignment .............................. 21

ZYNQ Ultrascale + FPGA Core Board ACU7EVB User Manual
Part 1: ACU7EVB Core Board
Part 1.1: ACU7EVB Core Board Introduction
ACU7EVB (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU7EV-2FFVB1156I of XILINX company Zynq UltraScale+
MPSoCs EG Family.
This core board uses 8 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. 4 DDR4 chip is mounted on the PL end, which is a 64-bit
data bus width and a capacity of 4GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1200MHz
(data rate 2400Mbps). In addition, two 256MBit QSPI FLASH and an 8GB
eMMC FLASH chip are also integrated on the core board to start storage
configuration and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and 16 GTH
transceivers and almost all IO ports on the PL side (HP I/O: 143, HD I/O: 46).
The wiring between the XCZU7EV chip and the interface has been processed
with equal length and differential, and the core board size is only 3.15*2.36
(inch), which is very suitable for secondary development.

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Figure 2-1-1: ACU7EVB Core Board (Front View)
Part 1.2: ZYNQ Chip
The FPGA core board ACU7EVB uses Xilinx's Zynq UltraScale+ MPSoCs
EV family chip, module XCZU7EV-2FFVB1156I. The PS system of the ZU7EV
chip integrates 4 ARM Cortex™-A53 processors with a speed of up to 1.3Ghz
and supports Level 2 Cache; it also contains 2 Cortex-R5 processors with a
speed of up to 533Mhz
The ZU7EV chip supports 32-bit or 64-bit DDR4, LPDDR4, DDR3, DDR3L,
LPDDR3 memory chips, with rich high-speed interfaces on the PS side such as
PCIE Gen2, USB3.0, SATA 3.1, DisplayPort; it also supports USB2.0, Gigabit
Ethernet, SD/SDIO, I2C, CAN, UART, GPIO and other interfaces. The PL end
contains a wealth of programmable logic units, DSP and internal RAM. .
Figure 2-2-1 detailed the Overall Block Diagram of the ZU7EV Chip.

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Figure 2-2-1: Overall Block Diagram of the ZYNQ ZU7EV Chip
The main parameters of the PS system part are as follows:
ARM quad-core Cortex ™-A53 processor, speed up to 1.3GHz, each
CPU 32KB level 1 instruction and data cache, 1MB level 2 cache,
shared by 2 CPUs
ARM dual-core Cortex-R5 processor, speed up to 533MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled
memory.
Image video processor Mali-400 MP2, speed up to 677MHz, 64KB
level 2 cache.
External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface

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Static storage interface, support NAND, 2xQuad-SPI FLASH.
High-speed connection interface, support PCIe Gen2 x 4, 2 x USB3.0,
Sata 3.1, Display Port, 4 x Tri-mode, Gigabit Ethernet
Common connection interfaces: 2 x USB2.0, 2 x SD/SDIO, 2 x UART,
2 x CAN 2.0B, 2 x I2C, 2 x SPI, 4 x 32b GPIO
Power management: Support the four-part division of power supply
Full/Low/PL/Battery
Encryption algorithm: support RSA, AES and SHA.
System monitoring: 10-bit 1Mbps AD sampling for temperature and
voltage detection.
The main parameters of the PL logic part are as follows:
Logic Cells: 504K
CLB Flip-flops: 460.8K
Look-up-tables (LUTs): 230.4K
 Block RAM : 11Mb
Clock Management Units (CMTs): 8
 DSP Slices: 1728
Part 1.3: DDR4 DRAM
The ACU7EVB core board is equipped with 8 Micron (Micron) 1GB DDR4
chips, model MT40A512M16LY-062E, of which 4 DDR4 chips are mounted on
the PS side to form a 64-bit data bus bandwidth and 4GB capacity. Four DDR4
chip is mounted on the PL end, which is a 64-bit data bus width and a capacity
of 4GB. The maximum operating speed of the DDR4 SDRAM on the PS side
can reach 1200MHz (data rate 2400Mbps), and the 4 DDR4 storage systems
are directly connected to the memory interface of the PS BANK504. The
highest operating speed of the DDR4 SDRAM on the PL side can reach
1200MHz (data rate 2400Mbps), and four piece of DDR4 is connected to the

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BANK66,67,68 interface of the FPGA. The specific configuration of DDR4
SDRAM is shown in Table 2-3-1 below:
Position
Bit Number
Chip Model
Capacity
Factory
PS
U4,U5,U6,U7
MT40A512M16LY-062E
512M x 16bit
Micron
PL
U17,U19,U45,U46
MT40A512M16LY-062E
512M x 16bit
Micron
Table 2-3-1: DDR4 SDRAM Configuration
The hardware design of DDR4 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR4.
The hardware connection of DDR4 SDRAM on the PS Side is shown in
Figure 2-3-1:
Figure 2-3-1: DDR3 DRAM schematic diagram
The hardware connection of DDR4 SDRAM on the PL Side is shown in
Figure 2-3-2:

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Figure 2-3-2: DDR4 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AN27
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AN26
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AP30
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AN29
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AJ26
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AH26
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AK29
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AK28
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
AD31
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
AD30
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
Y28
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
Y27
PS_DDR4_DQS6_N
PS_DDR_DQS_N6_504
AB34
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
AB33
PS_DDR4_DQS7_N
PS_DDR_DQS_N7_504
W32
PS_DDR4_DQS7_P
PS_DDR_DQS_P7_504
W31

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PS_DDR4_DQ0
PS_DDR_DQ0_504
AP27
PS_DDR4_DQ1
PS_DDR_DQ1_504
AP25
PS_DDR4_DQ2
PS_DDR_DQ2_504
AP26
PS_DDR4_DQ3
PS_DDR_DQ3_504
AM26
PS_DDR4_DQ4
PS_DDR_DQ4_504
AP24
PS_DDR4_DQ5
PS_DDR_DQ5_504
AL25
PS_DDR4_DQ6
PS_DDR_DQ6_504
AM25
PS_DDR4_DQ7
PS_DDR_DQ7_504
AM24
PS_DDR4_DQ8
PS_DDR_DQ8_504
AM28
PS_DDR4_DQ9
PS_DDR_DQ9_504
AN28
PS_DDR4_DQ10
PS_DDR_DQ10_504
AP29
PS_DDR4_DQ11
PS_DDR_DQ11_504
AP28
PS_DDR4_DQ12
PS_DDR_DQ12_504
AM31
PS_DDR4_DQ13
PS_DDR_DQ13_504
AP31
PS_DDR4_DQ14
PS_DDR_DQ14_504
AN31
PS_DDR4_DQ15
PS_DDR_DQ15_504
AM30
PS_DDR4_DQ16
PS_DDR_DQ16_504
AF25
PS_DDR4_DQ17
PS_DDR_DQ17_504
AG25
PS_DDR4_DQ18
PS_DDR_DQ18_504
AG26
PS_DDR4_DQ19
PS_DDR_DQ19_504
AJ25
PS_DDR4_DQ20
PS_DDR_DQ20_504
AG24
PS_DDR4_DQ21
PS_DDR_DQ21_504
AK25
PS_DDR4_DQ22
PS_DDR_DQ22_504
AJ24
PS_DDR4_DQ23
PS_DDR_DQ23_504
AK24
PS_DDR4_DQ24
PS_DDR_DQ24_504
AH28
PS_DDR4_DQ25
PS_DDR_DQ25_504
AH27
PS_DDR4_DQ26
PS_DDR_DQ26_504
AJ27
PS_DDR4_DQ27
PS_DDR_DQ27_504
AK27
PS_DDR4_DQ28
PS_DDR_DQ28_504
AL26
PS_DDR4_DQ29
PS_DDR_DQ29_504
AL27
PS_DDR4_DQ30
PS_DDR_DQ30_504
AH29
PS_DDR4_DQ31
PS_DDR_DQ31_504
AL28
PS_DDR4_DQ32
PS_DDR_DQ32_504
AB29
PS_DDR4_DQ33
PS_DDR_DQ33_504
AB30
PS_DDR4_DQ34
PS_DDR_DQ34_504
AC29
PS_DDR4_DQ35
PS_DDR_DQ35_504
AD32