Alinx KINTEX-7 FPGA User manual

KINTEX-7 FPGA
Development Board
AV7K300
User Manual

KINTEX-7 FPGA Development Board AV7K300 User Manual
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Version Record
Version
Date
Release By
Rev 1.1
2022-09-07

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Table of Contents
Version Record ............................................................................................. 2
Part 1: FPGA Development Board Introduction ...........................................5
Part 2: AC7K325B Core Board .....................................................................8
Part 2.1: AC7K325 Core Board Introduction ........................................ 8
Part 2.2: FPGA Chip ..............................................................................9
Part 2.3: DDR3 DRAM ........................................................................ 10
Part 2.4: QSPI Flash ........................................................................... 14
Part 2.5: Clock Configuration ..............................................................15
Part 2.5.1: 200Mhz Active Differential clock .......................................15
Part 2.5.2: GTX Reference Clock ....................................................... 16
Part 2.6: LED Light on Core Board .....................................................17
Part 2.7: Power Supply ....................................................................... 17
Part 2.8: Size Dimension .................................................................... 19
Part 2.9: Board to Board Connectors pin assignment ....................... 19
Part 3: Carrier Board .................................................................................. 27
Part 3.1: Carrier Board Introduction ....................................................27
Part 3.2: SFP Interface ....................................................................... 28
Part 3.3.: PCIe Card Slot .................................................................... 29
Part 3.4: SDI Output Interface ............................................................ 31
Part 3.5: SDI Input Interface............................................................... 33
Part 3.6: USB to Serial Port ................................................................ 34
Part 3.7: SD Card Slot ........................................................................ 34
Part 3.9: 40-Pin Expansion Port ......................................................... 35
Part 3.9: Keys and LEDs .....................................................................37
Part 3.10: JTAG debug port ................................................................ 39
Part 3.11: Power Supply ..................................................................... 39
Part 3.12: Size Dimension .................................................................. 41

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The AV7K300 FPGA development board, it is the XILINX KINTEX-7 FPGA
development platform.
The AV7K300 FPGA development platform uses XILINX's KINTEX-7 chip
XC7K325 solution. The FPGA development board mounts four pieces of
512MB high-speed DDR3 SDRAM chips, and a 128Mb QSPI FLASH chip.
In the design of expansion board, we have extended a wealth of interfaces
for users, such as 1 PCIex8 interface, 4 SFP interface, 2 SDI Output Interface,
2 SDI Input Interface,1 UART serial port, 1 SD card slot, 2 40-pin expansion
ports. It meets users' requirements for high-speed data exchange, data storage,
video transmission processing and industrial control. It is a "professional"
FPGA development platform, for high-speed data transmission and exchange,
pre-verification and post-application of data processing is possible. This
product is very suitable for students, engineers and other groups engaged in
KINTEX-7FPGA development.

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Part 1: FPGA Development Board Introduction
The entire structure of the development board is designed by inheriting our
usual core board + expansion board model. Use high-speed inter-board
connectors to connect between the core board and the expansion board.
The core board is the smallest system mainly composed of XC7K325 + 4
DDR3 + QSPI FLASH. Adopt Xilinx's KINTEX-7 series chip, model
XC7K325TFFG900. Four DDR3 memory chips are connected to the HP port of
the FPGA chip. Each DDR3 has a capacity of up to 512M bytes, forming a
64-bit data bandwidth. A 128Mb QSPI FLASH is used to statically store the
configuration file of the FPGA chip or other user data.
The carrier board expands a wealth of peripheral interfaces for the core
board, including 1 PCIex8 interface, 4 SFP interfaces, 2 SDI Output interface, 2
SDI Input interface, 2 40-pin expansion interface and some keys LEDs.
Figure 1-1: The Schematic Diagram of the AV7K300

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Through this diagram, you can see the interfaces and functions that the
AV7K300 FPGA Development Board contains:
FPGA Core Board
The smallest system consisting of XC7K325 + 4 DDR3 + QSPI FLASH,
there are two crystal oscillators to provide the clock, a single-ended
200MHz crystal oscillator provides the DDR control reference clock of
the FPGA logic, and the other differential 125MHz crystal oscillator
provides the GTX transceiver reference clock.
PCIe x8 interface
It supports the PCI Express 2.0 standard, provides a standard PCIe x8
high-speed data transmission interface, and the single-channel
communication rate can be as high as 5GBaud.
4 SFP interfaces
The four high-speed transceivers of the GTX transceiver of the FPGA
are connected to the transmission and reception of four optical modules
to realize four high-speed optical fiber communication interfaces. Each
fiber optic data communication receives and transmits at speeds of up
to 10 Gb/s.
SDI Video Output
2 channels of SDI video output interface, used SEMTECH's GV8500
SDI driver chip, which supports different formats of data output HDcctv
1.0, HD-SDI (ST 292), 3G_SDI (ST-424) and SD_SDI (ST259).
SDI Video Input
2 channels of SDI video input interface, used SEMTECH's GV8601 SDI
equalizer chip, which supports different formats of data input HDcctv 1.0,
HD-SDI (ST 292), 3G_SDI (ST-424) and SD_SDI (ST259). The input
interface is adaptive to video reception at three rates.
USB Uart Interface

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1 Uart to USB interface, used for communication with computer,
convenient for users to debug. The serial port chip adopts Silicon Labs
CP2102GM USB-UART chip, and the USB interface adopts MINI USB
interface.
Micro SD slot
1 Micro SD card slot, used to store operating system image and file
system.
40-pin expansion port
Two 40-pin 0.1 spacing pitch expansion port can be connected to
various ALINX modules (binocular camera, TFT LCD screen,
high-speed AD module, etc.). Expansion ports include 1 5V power
supply, 2 3.3V power supplies, 3 ground, and 34 IO ports.
JTAG Interface
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download FPGA through XILINX
down loader.
LED Light
7 LEDs, 2 LEDs on the core board and 7 LEDs on the carrier board. 1
power indicator on the core board; 1 DONE configuration indicator.
There are 1 power indicator light, 4 user indicator lights and 2 serial
port indicator lights on the carrier board.
Key
4 user keys on the carrier board

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Part 2: AC7K325B Core Board
Part 2.1: AC7K325 Core Board Introduction
AC7K325B (core board model, the same below) FPGA core board, it is
based on XILINX Kintex-7 XC7K325 series chip XC7K325TFFG900100T. The
core board uses 4 Micron's 512MB DDR3 chips MT41J256M16HA-125, with a
total capacity of 2GB. In addition, a 128MBit QSPI FLASH is also integrated on
the core board for boot storage configuration and system files.
The four board-to-board connectors of the core board AC7K325B expand
276 IOs, of which 92 IO levels of BANK17 and BANK18 can be modified by
replacing the LDO chip on the core board to meet the user's requirement of no
level interface; In addition, the core board also extended 16 pairs of high-speed
transceiver GTX interfaces. For users who need a lot of IO, this core board will
be a good choice. And the IO connection part, the FPGA chip to the interface
between the equal length and differential processing, and the core board size is
only 80 * 60 (mm), very suitable for secondary development.
Figure 2.1-1: AC7K325B Core Board (Front View)

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Part 2.2: FPGA Chip
As mentioned above, the FPGA model we use is XC7K325T-2FFG900I,
which belongs to Xilinx's KINTEX-7 series. The speed grade is 2, and the
temperature grade is industry grade. This model is a FGG900 package with
900 pins. Xilinx KINTEX-7 FPGA chip naming rules as below
Figure 2.2-1: The Specific Chip Model Definition of Kintex-7 Series
Figure 2.2-2: FPGA chip on board
The main parameters of the FPGA chip XC7K325T are as follows
Name
Specific parameters
Logic Cells
326,080
Slices
50,950
CLB flip-flops
407,600
Block RAM（kb）
16,020
DSP Slices
840
PCIe Gen2
1
XADC
1 XADC, 12bit, 1Mbps AD
GTP Transceiver
16 GTP, 12.5Gb/s max
Speed Grade
-2
Temperature Grade
Industrial

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Part 2.3: DDR3 DRAM
The FPGA core board AC7K325B is equipped with four Micron 4Gbit
(512MB) DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125). Four DDR3 SDRAMs make up a 64-bit bus width.
Because 4 DDR3 chips are connected to the HP port of the FPGA, the
maximum operating speed of DDR3 SDRAM can reach 800MHz (data rate
1600Mbps). Four DDR3 memory systems are directly connected to the
BANK32, BANK33, and BANK34 interfaces of the FPGA. The specific
configuration of DDR3 SDRAM is shown in Table 2.3-1 below.
Bit Number
Chip Model
Capacity
Factory
U4,U5, U6, U7
MT41K256M16HA-125 or
MT41J256M16HA-125
256M x 16bit
Micron
Table 2.3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 2.3-1: The DDR3 DRAM Schematic
DDR3 DRAM pin assignment:

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Net Name
FPGA PIN Name
FPGA P/N
DDR3_D0
IO_L13P_T2_MRCC_32
AD18
DDR3_D1
IO_L16N_T2_32
AB18
DDR3_D2
IO_L14P_T2_SRCC_32
AD17
DDR3_D3
IO_L17P_T2_32
AB19
DDR3_D4
IO_L14N_T2_SRCC_32
AD16
DDR3_D5
IO_L17N_T2_32
AC19
DDR3_D6
IO_L13N_T2_MRCC_32
AE18
DDR3_D7
IO_L18P_T2_32
AB17
DDR3_D8
IO_L8P_T1_32
AG19
DDR3_D9
IO_L7N_T1_32
AK19
DDR3_D10
IO_L10P_T1_32
AD19
DDR3_D11
IO_L7P_T1_32
AJ19
DDR3_D12
IO_L11P_T1_SRCC_32
AF18
DDR3_D13
IO_L8N_T1_32
AH19
DDR3_D14
IO_L10N_T1_32
AE19
DDR3_D15
IO_L11N_T1_SRCC_32
AG18
DDR3_D16
IO_L1N_T0_32
AK15
DDR3_D17
IO_L5N_T0_32
AJ17
DDR3_D18
IO_L2N_T0_32
AH15
DDR3_D19
IO_L4P_T0_32
AF15
DDR3_D20
IO_L4N_T0_32
AG14
DDR3_D21
IO_L5P_T0_32
AH17
DDR3_D22
IO_L2P_T0_32
AG15
DDR3_D23
IO_L1P_T0_32
AK16
DDR3_D24
IO_L19P_T3_32
AE15
DDR3_D25
IO_L24P_T3_32
Y16
DDR3_D26
IO_L22P_T3_32
AC14
DDR3_D27
IO_L20P_T3_32
AA15
DDR3_D28
IO_L23P_T3_32
AA17
DDR3_D29
IO_L22N_T3_32
AD14
DDR3_D30
IO_L23N_T3_32
AA16
DDR3_D31
IO_L20N_T3_32
AB15
DDR3_D32
IO_L22N_T3_34
AK6
DDR3_D33
IO_L23P_T3_34
AJ8

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DDR3_D34
IO_L22P_T3_34
AJ6
DDR3_D35
IO_L19P_T3_34
AF8
DDR3_D36
IO_L24N_T3_34
AK4
DDR3_D37
IO_L23N_T3_34
AK8
DDR3_D38
IO_L24P_T3_34
AK5
DDR3_D39
IO_L20N_T3_34
AG7
DDR3_D40
IO_L10P_T1_34
AE4
DDR3_D41
IO_L8N_T1_34
AF1
DDR3_D42
IO_L11P_T1_SRCC_34
AE5
DDR3_D43
IO_L8P_T1_34
AE1
DDR3_D44
IO_L12P_T1_MRCC_34
AF6
DDR3_D45
IO_L10N_T1_34
AE3
DDR3_D46
IO_L11N_T1_SRCC_34
AF5
DDR3_D47
IO_L7N_T1_34
AF2
DDR3_D48
IO_L13P_T2_MRCC_34
AH4
DDR3_D49
IO_L16N_T2_34
AJ2
DDR3_D50
IO_L14N_T2_SRCC_34
AH5
DDR3_D51
IO_L13N_T2_MRCC_34
AJ4
DDR3_D52
IO_L16P_T2_34
AH2
DDR3_D53
IO_L17N_T2_34
AK1
DDR3_D54
IO_L14P_T2_SRCC_34
AH6
DDR3_D55
IO_L17P_T2_34
AJ1
DDR3_D56
IO_L2P_T0_34
AC2
DDR3_D57
IO_L4P_T0_34
AC5
DDR3_D58
IO_L1N_T0_34
AD3
DDR3_D59
IO_L6P_T0_34
AC7
DDR3_D60
IO_L5N_T0_34
AE6
DDR3_D61
IO_L5P_T0_34
AD6
DDR3_D62
IO_L2N_T0_34
AC1
DDR3_D63
IO_L4N_T0_34
AC4
DDR3_DM0
IO_L16P_T2_32
AA18
DDR3_DM1
IO_L12P_T1_MRCC_32
AF17
DDR3_DM2
IO_L6P_T0_32
AE16
DDR3_DM3
IO_L24N_T3_32
Y15
DDR3_DM4
IO_L20P_T3_34
AF7

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DDR3_DM5
IO_L7P_T1_34
AF3
DDR3_DM6
IO_L18P_T2_34
AJ3
DDR3_DM7
IO_L1P_T0_34
AD4
DDR3_DQS0_P
IO_L15P_T2_DQS_32
Y19
DDR3_DQS0_N
IO_L15N_T2_DQS_32
Y18
DDR3_DQS1_P
IO_L9P_T1_DQS_32
AJ18
DDR3_DQS1_N
IO_L9N_T1_DQS_32
AK18
DDR3_DQS2_P
IO_L3P_T0_DQS_32
AH16
DDR3_DQS2_N
IO_L3N_T0_DQS_32
AJ16
DDR3_DQS3_P
IO_L21P_T3_DQS_32
AC16
DDR3_DQS6_N
IO_L15N_T2_DQS_34
AH1
DDR3_DQS7_P
IO_L3P_T0_DQS_34
AD2
DDR3_DQS7_N
IO_L3N_T0_DQS_34
AD1
DDR3_A0
IO_L1P_T0_33
AA12
DDR3_A1
IO_L1N_T0_33
AB12
DDR3_A2
IO_L2P_T0_33
AA8
DDR3_A3
IO_L2N_T0_33
AB8
DDR3_A4
IO_L3P_T0_DQS_33
AB9
DDR3_A5
IO_L3N_T0_DQS_33
AC9
DDR3_A6
IO_L6N_T0_VREF_33
AB13
DDR3_A7
IO_L4N_T0_33
Y10
DDR3_A8
IO_L5P_T0_33
AA11
DDR3_A9
IO_L5N_T0_33
AA10
DDR3_A10
IO_L6P_T0_33
AA13
DDR3_A11
IO_L8P_T1_33
AD8
DDR3_A12
IO_L7P_T1_33
AB10
DDR3_A13
IO_L7N_T1_33
AC10
DDR3_A14
IO_L15P_T2_DQS_33
AJ9
DDR3_BA0
IO_L8N_T1_33
AE8
DDR3_BA1
IO_L9P_T1_DQS_33
AC12
DDR3_BA2
IO_L9N_T1_DQS_33
AC11
DDR3_WE
IO_L10P_T1_33
AD9
DDR3_RAS
IO_L10N_T1_33
AE9
DDR3_CAS
IO_L11P_T1_SRCC_33
AE11
DDR3_S0
IO_L11N_T1_SRCC_33
AF11

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DDR3_CKE0
IO_L12P_T1_MRCC_33
AD12
DDR3_ODT
IO_L12N_T1_MRCC_33
AD11
DDR3_CLK0_P
IO_L13P_T2_MRCC_33
AG10
DDR3_CLK0_N
IO_L13N_T2_MRCC_33
AH10
DDR3_RESET
IO_L4P_T0_33
Y11
Part 2.4: QSPI Flash
The FPGA core board AX7K325 is equipped with one 128MBit QSPI
FLASH, and the model is W25Q128A, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. The specific
models and related parameters of QSPI FLASH are shown in Table 2.4-1.
Position
Model
Capacity
Factory
U14
N25Q128
128M Bit
Numonyx
Table 2.4-1: QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pin of BANK14
respectively. Figure 2.4-1 shows the hardware connection of QSPI Flash.
Figure 2.4-1: QSPI Flash Schematic
QSPI Flash pin assignments:

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Net Name
FPGA PIN Name
FPGA P/N
FPGA_CCLK
CCLK_0
B10
FLASH_CE_B
IO_L6P_T0_FCS_B_14
U19
FLASH_D0
IO_L1P_T0_D00_MOSI_14
P24
FLASH_D1
IO_L1N_T0_D01_DIN_14
R25
FLASH_D2
IO_L2P_T0_D02_14
R20
FLASH_D3
IO_L2N_T0_D03_14
R21
Part 2.5: Clock Configuration
The AC7K325B core board is equipped with two Sitime active differential
crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main
clock for FPGA and used to generate DDR3 control clock; the other is 125MHz,
model is SiT9102 -125MHz, reference clock input for GTP transceivers.
Figure 2.5-1: Core Board Clock Sourece
Part 2.5.1: 200Mhz Active Differential clock
G1 in Figure 2.5-2 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK33 global clock pin MRCC of the FPGA. This 200Mhz differential clock
can be used to drive the DDR3 controller and user logic in the FPGA.

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Figure 2.5-2: System clock source
200Mhz Differential Clock Pin Assignment
Signal Name
FPGA PIN
SYS_CLK_P
AE10
SYS_CLK_N
AF10
Part 2.5.2: GTX Reference Clock
G2 in Figure 2.5-3 is the 125Mhz active differential crystal. The reference
clock is connected to the reference clock input REFCLK1P / REFCLK1N of
BANK117. The schematic diagram of this clock source is shown in Figure 5-3
Figure 2.5-3: 125Mhz Active Differential Crystal Schematic
GTX Reference Clock

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Net Name
FPGA PIN
BANK117_CLK1_P
J8
BANK117_CLK1_N
J7
Part 2.6: LED Light on Core Board
There are 2 red LED lights on the AC7K325B FPGA core board, one of
which is the power indicator light (PWR), one is the configuration LED light
(DONE). When the core board is powered, the power indicator will illuminate;
when the FPGA is configured, the configuration LED will illuminate. The
schematic diagram of the LED light hardware connection is shown in Figure
2.6-1:
Figure 2-6-1: LED lights on core board Schematic
Part 2.7: Power Supply
The power supply voltage of AC7K325B core board is DC5V, which is
supplied by connecting the carrier board. The schematic diagram of the power
supply design on the core board is shown in Figure 2.7-1 below:

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Figure 2.7-1: Power Interface in Schematic
+ 5V generates + 1.0V FPGA core power through the DCDC power chip
MYMGK1R820FRSR. The output current of the MYMGK1R820FRSR is as
high as 20A, which far meets the core voltage current demand. The + 5V power
is generated by the DCDC chip ETA1471 to generate four power sources: +
1.5V, + 3.3V, +1.8V,+ 1.5V and MGTAVTT. The + 1.0V used by the GTX
transceiver is generated by the DCDC chip ETA8156. The GTX auxiliary power
+ 1.8V through an LDO chip SPX3819-1-8. The VTT and VREF voltages for
DDR3 are generated by the TPS51200. In addition, two SPX3819M5-3-3 are
used to generate the IO power of BANK17 and BANK18. Users can change the
LDO chip to make the IO input and output of these two banks to other voltage

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standards.
Because the power supply of the FPGA requires the power-on sequence,
in the circuit design, according to the power requirements of the chip, the
power-on sequence is + 1.0V-> + 1.8V-> (+ 1.5 V, + 3.3V, VCCIO17, VCCIO18,
Ensure that the chip works properly.
Part 2.8: Size Dimension
Figure 2.8-1: Top View
Part 2.9: Board to Board Connectors pin assignment
The core board expands a total of four high-speed expansion connectors,
and uses four 120-Pin inter-board connectors (J29 ~ J32) to connect to the
carrier board. The connector uses Panasonic's AXK5A2137YG. Among them,
J29 is connected to the GTX transceiver signal, J30 is connected to the JTAG,
and the IOs of BANK17 and BANK18, J31 is connected to the IO of BANK15

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and BANK16, J32 is connected to the IO of BANK12 and BANK13 and + 5V
power.
Pin assignment of J29 connector
J29 Pin
Signal Name
FPGA Pin
J29 Pin
Signal Name
FPGA Pin
1
BANK115_TX0_N
Y1
2
BANK115_RX0_N
AA3
3
BANK115_TX0_P
Y2
4
BANK115_RX0_P
AA4
5
GND
-
6
GND
-
7
BANK115_TX1_N
V1
8
BANK115_RX1_N
Y5
9
BANK115_TX1_P
V2
10
BANK115_RX1_P
Y6
11
GND
-
12
GND
-
13
BANK115_TX2_N
U3
14
BANK115_RX2_N
W3
15
BANK115_TX2_P
U4
16
BANK115_RX2_P
W4
17
GND
-
18
GND
-
19
BANK115_TX3_N
T1
20
BANK115_RX3_N
V5
21
BANK115_TX3_P
T2
22
BANK115_RX3_P
V6
23
GND
-
24
GND
-
25
BANK115_CLK0_N
R7
26
BANK115_CLK1_N
U7
27
BANK115_CLK0_P
R8
28
BANK115_CLK1_N
U8
29
GND
-
30
GND
-
31
BANK116_TX0_N
P1
32
BANK116_RX0_N
T5
33
BANK116_TX0_P
P2
34
BANK116_RX0_P
T6
35
GND
-
36
GND
-
37
BANK116_TX1_N
N3
38
BANK116_RX1_N
R3
39
BANK116_TX1_P
N4
40
BANK116_RX1_P
R4
41
GND
-
42
GND
-
43
BANK116_TX2_N
M1
44
BANK116_RX2_N
P5
45
BANK116_TX2_P
M2
46
BANK116_RX2_P
P6
47
GND
-
48
GND
-
49
BANK116_TX3_N
L3
50
BANK116_RX3_N
M5
51
BANK116_TX3_P
L4
52
BANK116_RX3_P
M6
53
GND
-
54
GND
-
55
BANK116_CLK0_N
L7
56
BANK116_CLK1_N
N7
57
BANK116_CLK0_P
L8
58
BANK116_CLK1_P
N8