Alinx AX7202 User manual

ARTIX-7 FPGA
Development Board
AX7202
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.2
2023-02-23
Rachel Zhou
First Release

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Table of Contents
Version Record .............................................................................................2
Part 1: FPGA Development Board Introduction .......................................... 6
Part 2: AC7200 Core Board Introduction ...................................................10
Part 2.1: FPGA Chip ........................................................................... 12
Part 2.2: Active Differential Crystal .....................................................13
Part 2.3: 200Mhz Active Differential clock ..........................................14
Part 2.4: 148.5Mhz Active Differential Crystal ................................... 15
Part 2.5: DDR3 DRAM ........................................................................16
Part 2.6: QSPI Flash ...........................................................................21
Part 2.7: LED Light on Core Board .................................................... 23
Part 2.8: Reset Button ........................................................................ 24
Part 2.9: JTAG Interface .....................................................................25
Part 2.10: Power Interface on the Core Board .................................. 26
Part 2.11: Board to Board Connectors ............................................... 27
Part 2.12: Power Supply .....................................................................34
Part 2.13: Structure Diagram ..............................................................35
Part 3: Carrier Board ..................................................................................36
Part 3.1: Carrier Board Introduction ................................................... 36
Part 3.2: Gigabit Ethernet Interface ................................................... 37
Part 3.3: SFP Interface ....................................................................... 39
Part 3.4: VGA display interface .......................................................... 42
Part 3.5: USB2.0 Interface ................................................................. 44
Part 3.6: SD Card Slot ........................................................................46
Part 3.7: USB to Serial Port ................................................................48
Part 3.8: RS232 Interface ...................................................................50
Part 3.9: EEPROM 24LC04 ................................................................51
Part 3.10: Real time clock DS1302 .................................................... 52

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Part 3.11: Expansion Header ............................................................. 53
Part 3.12: JTAG Interface ...................................................................56
Part 3.13: keys ....................................................................................57
Part 3.14: LED Light ........................................................................... 58
Part 3.15: Power Supply .....................................................................59

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This ARTIX-7 FPGA development platform adopts the core board + carrier
board mode, which is convenient for users to use the core board for secondary
development.
In the design of carrier board, we have extended a wealth of interfaces for
users, such as 2 fiber interfaces, 1 Gigabit Ethernet interfaces, 1 USB2.0 , VGT
output interface, RS232 interface etc. It meets user's requirements for
high-speed data exchange, video transmission processing and industrial
control. It is a "Versatile" ARTIX-7 FPGA development platform. It provides the
possibility for high-speed video transmission, pre-validation and
post-application of network and fiber communication and data processing. This
product is very suitable for students, engineers and other groups engaged in
ARTIX-7FPGA development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AX7202 FPGA development board is inherited
from our consistent core board + carrier board model. A high-speed inter-board
connector is used between the core board and the carrier board.
The core board is mainly composed of FPGA + 2 DDR3 + QSPI FLASH,
which undertakes the functions of high-speed data processing and storage of
FPGA, high-speed data reading and writing between FPGA and two DDR3s,
data bit width is 32 bits, and the bandwidth of the whole system is up to 25Gb.
/s(800M*32bit); The two DDR3 capacities are up to 8Gbit, which meets the
need for high buffers during data processing. The selected FPGA is the
XC7A200T chip of XILINX's ARTIX-7 series, in BGA 484 package. The
communication frequency between the XC7A200T and DDR3 reaches 400Mhz
and the data rate is 800Mhz, which fully meets the needs of high-speed
multi-channel data processing. In addition, the XC7A200T FPGA features four
GTP high-speed transceivers with speeds up to 6.6Gb/s per channel, making it
ideal for fiber-optic communications and PCIe data communications.
The AX7202 carrier board expands its rich peripheral interface, including 2
SFP interfaces, 1 Gigabit Ethernet interfaces, 1 USB2.0 HOST interfaces, 1
VGA output interface, 1 RS232 interface, 1 UART serial interface. 1 SD card
interface, 2-way 40-pin expansion header, some keys and RTC circuit.

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Figure 1-1-1: The Schematic Diagram of the AX7202
Through this diagram, you can see the interfaces and functions that the
AX7202 FPGA Development Board contains:
Artix-7 FPGA core board
The core board consists of XC7A200T + 8Gb DDR3 + 128Mb QSPI
FLASH. There are two high-precision Sitime LVDS differential crystals,
one at 200MHz and the other at 148.5MHz, providing stable clock input
for FPGA systems and GTP modules.
1-channel Gigabit Ethernet Interface RJ-45 interface
The Gigabit Ethernet interface chip uses Realtek's RTL8211EG
Ethernet PHY chip to provide network communication services to users.

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RTL8211EG chip supports 10/100/1000 Mbps network transmission
rate. Full duplex and adaptive
2-channel high-speed SFP Interface
The two high-speed transceivers of the GTP transceiver of ARTIX-7
FPGA are connected to the transmission and reception of two optical
modules to realize two high-speed optical fiber communication
interfaces. Each fiber optic data communication receives and transmits
at speeds up to 6.6 Gb/s.
1-channel VGA Output interface
The development board uses ADI's ADV7123 chip to achieve VGA
output, realizing 24-bit true color RGB digital signal analog conversion,
resolution up to 1080p@60Hz output.
1-channel USB2.0 Interface
USB2.0 high-speed communication between FPGA development board
and PC is realized by Cypress CY7C68013A USB2.0 controller chip;
1-channel Uart to USB interface
1 Uart to USB interface for communication with the computer for user
debugging. The serial port chip is the USB-UAR chip of Silicon Labs
CP2102GM, and the USB interface is the MINI USB interface.
1-channel RS232 interface
Uart to RS232 interface for data communication with a computer or
other settings. The RS232 conversion chip is the MAX323, and the
RS232 interface uses the standard DB9 interface.
Micro SD card slot
1-port Micro SD card holder, support SD mode and SPI mode
RTC real time clock
Onboard RTC real time clock with battery holder, battery model
CR1220
EEPROM

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Onboard an IIC interface EEPROM 24LC04
2-way 40-pin expansion port
2-way 40-pin 0.1inch spacing expansion port can be connected to
various ALINX modules (binocular camera, TFT LCD screen,
high-speed AD module, etc.). The expansion port contains 1 channel
5V power supply, 2 channel 3.3V power supply, 3 way ground, 34 IOs
port.
JTAG Interface
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging.
keys
4 keys; 1 reset key (on the core board)
LED Light
5 user LEDs (1 on the core board and 4 on the carrier board)

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Part 2: AC7200 Core Board Introduction
AC7200 (core board model, the same below) FPGA core board, it is based
on XILINX's ARTIX-7 series 200T AC7200-2FGG484I. It is a high-performance
core board with high speed, high bandwidth and high capacity. It is suitable for
high-speed data communication, video image processing, high-speed data
acquisition, etc.
This AC7200 core board uses two pieces of MICRON's
MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two
DDR chips are combined into a 32-bit data bus width, and the read/write data
bandwidth between FPGA and DDR3 is up to 25Gb; such a configuration can
meet the needs of high bandwidth data processing.
The AC7200 core board expands 180 standard IO ports of 3.3V level, 15
standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX
differential signals. For users who need a lot of IO, this core board will be a
good choice. Moreover, the routing between the FPGA chip and the interface is
equal length and differential processing, and the core board size is only 45*55
(mm), which is very suitable for secondary development.

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AC7200 Core Board (Front View)
AC7200 Core Board (Rear View)

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Part 2.1: FPGA Chip
As mentioned above, the FPGA model we use is AC7200-2FGG484I,
which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the
temperature grade is industry grade. This model is a FGG484 package with
484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below
The Specific Chip Model Definition of ARTIX-7 Series
FPGA chip on board
The main parameters of the FPGA chip AC7200 are as follows
Name
Specific parameters
Logic Cells
215360
Slices
33650
CLB flip-flops
269200
Block RAM（kb）
13140
DSP Slices
740

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PCIe Gen2
1
XADC
1 XADC,12bit, 1Mbps AD
GTP Transceiver
4 GTP，6.6Gb/s max
Speed Grade
-2
Temperature Grade
Industrial
FPGA power supply system
Artix-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCO, VMGTAVCC and
VMGTAVTT. VCCINT is the FPGA core power supply pin, which needs to be connected
to 1.0V; VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V;
VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of
each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On
AC7200 FPGA core board, BANK34 and BANK35 need to be connected to
DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK
is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can
be changed by replacing the LDO chip. VMGTAVCC is the supply voltage of
the FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the
termination voltage of the GTP transceiver, connected to 1.2V.
The Artix-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If
VCCINT and VCCBRAM have the same voltage, they can be powered up at
the same time. The order of power outages is reversed. The power-up
sequence of the GTP transceiver is VCCINT, then VMGTAVCC, then
VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage, they can be
powered up at the same time. The power-off sequence is just the opposite of
the power-on sequence.
Part 2.2: Active Differential Crystal
The AC7200 core board is equipped with two Sitime active differential
crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main

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clock for FPGA and used to generate DDR3 control clock; the other is 125MHz,
model is SiT9102 -125MHz, reference clock input for GTP transceivers.
Part 2.3: 200Mhz Active Differential clock
G1 in Figure 3-1 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz
differential clock can be used to drive the user logic in the FPGA. Users can
configure the PLLs and DCMs inside the FPGA to generate clocks of different
frequencies.
200Mhz Active Differential Crystal Schematic
200Mhz Active Differential Crystal on the Core Board
200Mhz Differential Clock Pin Assignment

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Signal Name
FPGA PIN
SYS_CLK_P
R4
SYS_CLK_N
T4
Part 2.4: 148.5Mhz Active Differential Crystal
G2 is the 148.5Mhz active differential crystal, which is the reference input
clock provided to the GTP module inside the FPGA. The crystal output is
connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and
MGTREFCLK0N (E6) of the FPGA.
148.5Mhz Active Differential Crystal Schematic

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1148.5Mhz Active Differential Crystal on the Core Board
125Mhz Differential Clock Pin Assignment
Net Name
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6
Part 2.5: DDR3 DRAM
The FPGA core board AC7200 is equipped with two Micron 4Gbit (512MB)
DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed
of 800MHz (data rate 1600Mbps). The DDR3 memory system is directly
connected to the memory interface of the BANK 34 and BANK35 of the FPGA.
The specific configuration of DDR3 SDRAM is shown in Table 4-1.
Bit Number
Chip Model
Capacity
Factory
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,

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trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
The DDR3 DRAM Schematic

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The DDR3 on the Core Board
DDR3 DRAM pin assignment:
Net Name
FPGA PIN Name
FPGA P/N
DDR3_DQS0_P
IO_L3P_T0_DQS_AD5P_35
E1
DDR3_DQS0_N
IO_L3N_T0_DQS_AD5N_35
D1
DDR3_DQS1_P
IO_L9P_T1_DQS_AD7P_35
K2
DDR3_DQS1_N
IO_L9N_T1_DQS_AD7N_35
J2
DDR3_DQS2_P
IO_L15P_T2_DQS_35
M1
DDR3_DQS2_N
IO_L15N_T2_DQS_35
L1
DDR3_DQS3_P
IO_L21P_T3_DQS_35
P5
DDR3_DQS3_N
IO_L21N_T3_DQS_35
P4
DDR3_DQ[0]
IO_L2P_T0_AD12P_35
C2
DDR3_DQ [1]
IO_L5P_T0_AD13P_35
G1
DDR3_DQ [2]
IO_L1N_T0_AD4N_35
A1
DDR3_DQ [3]
IO_L6P_T0_35
F3
DDR3_DQ [4]
IO_L2N_T0_AD12N_35
B2
DDR3_DQ [5]
IO_L5N_T0_AD13N_35
F1

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DDR3_DQ [6]
IO_L1P_T0_AD4P_35
B1
DDR3_DQ [7]
IO_L4P_T0_35
E2
DDR3_DQ [8]
IO_L11P_T1_SRCC_35
H3
DDR3_DQ [9]
IO_L11N_T1_SRCC_35
G3
DDR3_DQ [10]
IO_L8P_T1_AD14P_35
H2
DDR3_DQ [11]
IO_L10N_T1_AD15N_35
H5
DDR3_DQ [12]
IO_L7N_T1_AD6N_35
J1
DDR3_DQ [13]
IO_L10P_T1_AD15P_35
J5
DDR3_DQ [14]
IO_L7P_T1_AD6P_35
K1
DDR3_DQ [15]
IO_L12P_T1_MRCC_35
H4
DDR3_DQ [16]
IO_L18N_T2_35
L4
DDR3_DQ [17]
IO_L16P_T2_35
M3
DDR3_DQ [18]
IO_L14P_T2_SRCC_35
L3
DDR3_DQ [19]
IO_L17N_T2_35
J6
DDR3_DQ [20]
IO_L14N_T2_SRCC_35
K3
DDR3_DQ [21]
IO_L17P_T2_35
K6
DDR3_DQ [22]
IO_L13N_T2_MRCC_35
J4
DDR3_DQ [23]
IO_L18P_T2_35
L5
DDR3_DQ [24]
IO_L20N_T3_35
P1
DDR3_DQ [25]
IO_L19P_T3_35
N4
DDR3_DQ [26]
IO_L20P_T3_35
R1
DDR3_DQ [27]
IO_L22N_T3_35
N2
DDR3_DQ [28]
IO_L23P_T3_35
M6
DDR3_DQ [29]
IO_L24N_T3_35
N5
DDR3_DQ [30]
IO_L24P_T3_35
P6
DDR3_DQ [31]
IO_L22P_T3_35
P2
DDR3_DM0
IO_L4N_T0_35
D2
DDR3_DM1
IO_L8N_T1_AD14N_35
G2
DDR3_DM2
IO_L16N_T2_35
M2
DDR3_DM3
IO_L23N_T3_35
M5
DDR3_A[0]
IO_L11N_T1_SRCC_34
AA4
DDR3_A[1]
IO_L8N_T1_34
AB2
DDR3_A[2]
IO_L10P_T1_34
AA5
DDR3_A[3]
IO_L10N_T1_34
AB5
DDR3_A[4]
IO_L7N_T1_34
AB1
DDR3_A[5]
IO_L6P_T0_34
U3

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DDR3_A[6]
IO_L5P_T0_34
W1
DDR3_A[7]
IO_L1P_T0_34
T1
DDR3_A[8]
IO_L2N_T0_34
V2
DDR3_A[9]
IO_L2P_T0_34
U2
DDR3_A[10]
IO_L5N_T0_34
Y1
DDR3_A[11]
IO_L4P_T0_34
W2
DDR3_A[12]
IO_L4N_T0_34
Y2
DDR3_A[13]
IO_L1N_T0_34
U1
DDR3_A[14]
IO_L6N_T0_VREF_34
V3
DDR3_BA[0]
IO_L9N_T1_DQS_34
AA3
DDR3_BA[1]
IO_L9P_T1_DQS_34
Y3
DDR3_BA[2]
IO_L11P_T1_SRCC_34
Y4
DDR3_S0
IO_L8P_T1_34
AB3
DDR3_RAS
IO_L12P_T1_MRCC_34
V4
DDR3_CAS
IO_L12N_T1_MRCC_34
W4
DDR3_WE
IO_L7P_T1_34
AA1
DDR3_ODT
IO_L14N_T2_SRCC_34
U5
DDR3_RESET
IO_L15P_T2_DQS_34
W6
DDR3_CLK_P
IO_L3P_T0_DQS_34
R3
DDR3_CLK_N
IO_L3N_T0_DQS_34
R2
DDR3_CKE
IO_L14P_T2_SRCC_34
T5