Alinx KINTEX UltraScale FPGA AXKU042 User manual

KINTEX UltraScale FPGA
Development Board
AXKU042
User Manual

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Table of Contents
Version Record................................................................................................................. 2
Part 1 AXKU042 Development Board ..........................................................................................7
Part 1.1: FPGA Development Board Introduction.......................................................7
Part 1.2: FPGA Chip................................................................................................................8
Part 1.3: DDR4 DRAM........................................................................................................... 8
Part 1.4: QSPI Flash..............................................................................................................13
Part 1.5: Clock configuration........................................................................................... 14
Part 1.6: LED Light................................................................................................................15
Part 1.7: Power Supply....................................................................................................... 15
Part 1.8: Size Dimension....................................................................................................17
Part 1.9: Board to Board Connectors pin assignment............................................17
Part 2: Carrier Board ......................................................................................................................27
Part 2.1: Introduction..........................................................................................................27
Part 2.2: PCIE X8 interface................................................................................................ 28
Part 2.3: SFP+ Optical fiber interface........................................................................... 30
Part 2.4: Gigabit Ethernet Interface...............................................................................31
Part 2.5: USB to Serial Port............................................................................................... 32
Part 2.6: FMC Expansion Port .......................................................................................... 33
Part 2.7: SD Card Slot......................................................................................................... 42
Part 2.8: SMA Interface...................................................................................................... 43
Part 2.9: Temperature Sensor and EEPROM...............................................................44
Part 2.10: LED Light............................................................................................................. 44
Part 2.11: Keys.......................................................................................................................46
Part 2.12: JTAG Interface................................................................................................... 47
Part 2.13: Power Supply.....................................................................................................47
Part 2.14: Fan......................................................................................................................... 48
Part 2.15:Size Dimension...................................................................................................49

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Alinx Electronic Technology (Shanghai) Co., Ltd, based on KINTEX UltraSacale series
development platform for the architecture (model: AXKU042) has been officially released. In order
to let you quickly understand this development platform, we have compiled this user manual.
AXKU042 adopts a core board and expansion board model, which facilitates users' secondary
development and utilization of the core board. The core board is equipped with four 1GB
high-speed DDR4 SDRAM chips and two 128Mb QSPI FLASH chips.
In terms of expansion board design, we have extended a variety of interfaces for users: two
10G SFP+fiber optic interfaces, 3 FMC expansion interfaces (1 HPC, 2 LPC), 1 gigabit network port, 1
UART serial port, 1 SD card interface, LED buttons, and so on.
The following figure is a schematic diagram of the entire development system structure:

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Through this diagram, you can see the interfaces and functions that the AXKU042 Development
Board contains:
FPGA Core Board：
1) FPGA chip：Xilinx KINTEX UltraSacale chip XCKU040.
2) DDR4：With four large-capacity 1GB (4 GB total) high-speed DDR4 SDRAM, can be used
as data storage for FPGA, image analysis cache, and data processing;
3) QSPI FLASH：two 128Mbit QSPI NOR FLASH memory chip can be used as a storage for
configuration files and user data;
4) One differential crystal vibration of 200 Mhz;
5) Two diode LEDs, 1 power indicator, 1 DONE configuration indicator.
Development Board
1) Two SFP and optical fiber communication interfaces ，each fiber optical data
communication receives and transmits at speeds of up to 16.3 Gb/s.
2) One PCIE3.0 X8 interface，endpoint mode，use to communicate datas between PC and
PCIE.
3) USB Uart interface， used for communication with the computer for user debugging. The
serial port chip adopts the USB-UAR chip of Silicon Labs CP2102GM, and the USB
interface adopts the MINI USB interface.
4) 1 channel 10/100M/1000MEthernet RJ45 interface for Ethernet data exchange with
computers or other network devices. The network interface chip uses Micrel's KSZ9031

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industrial grade GPHY chip.
5) 3 standard FMC expansion port, including 2 LPC FMC expansion ports and 1 HPC FMC
expansion port, which can be connected to various FMC modules of Xilinx or Alinx(HDMI
input and output modules, binocular camera modules,high-speed AD modules, etc. )
6) 1Micro SD card holder, used to store operating system image and file system.
7) 2 SMA external interfaces, the pins are connected to the transceiver for external
high-speed input and output signals.
8) Onboard a temperature and humidity sensor chip LM75 for detecting the temperature
and humidity of the environment around the board.
9) One EEPROM, used for IIC bus communication and storage of some customer-defined
information.
10) A 10-pin 2.54mm spacing standard JTAG ports for FPGA program download and
debugging. Users can debug and download FPGAs through XILINX downloader.
11) Two 156.25Mhz differential crystal onboard provides reference clock for transceiver.
12) 7 LEDs,1 power indicator, 4 user indicators,1 pair of panel indicator.

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Part 1 AXKU042 Development Board
Part 1.1: FPGA Development Board Introduction
AXKU042(core board model, the same below) FPGA core board,FPGA chip is based
on XCKU040-2FFVA1156I of XILINX company XC7K325 series.This core board uses
four Micron's MT40A512M16LY-062EIT, each of which has a capacity of 1GB, total
capacity is 4 GB. In addition, FPGA chip configuration uses two128MBit QSPI FLASH,
used as FPGA data storage and system files.
The six board-to-board connectors of the core board AXKU042 expand 359 IOs,
Of which 104 IO levels of BANK64 and BANK65 is 3.3V, while other IOs levels of bank
is 1.8V; In addition,the core board also extended 20 pairs of high-speed Transceiver
GTH interfaces. For users who need a lot of IO, this core board will be a good choice.
And IO connection part, the line between the chip and the interface have been done
the equal length and differential processing, and the core board size is only 80 * 60
(mm), very suitable for secondary development.
AXKU042 Core Board (Front View)

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Part 1.2: FPGA Chip
The FPGA development board uses Xilinx's KINTEX UltraScale chip, model number
XCKU040-2FFVA1156I. The speed class is 2 and the temperature class is industrial.
This model is a FFVA1156 package with 1156 pins and a 1.0mm pitch. The chip
naming rules for Xilinx KINTEX UltraScale FPGA are shown in Figure 1-2-1 below:
Figure 1-2-1 The Chip Model Definition of KINTEX UltraScale Series
The main parameters of AXKU042 are as follows：
Name
Specific parameters
Logic Cells
530,250
CLB LUTs
242,400
CLB flip-flops
484,800
Block RAM（Mb）
21.1
DSP Slices
1,920
PCIe Gen3 x8
3
GTH Transceiver
20 个，16.3Gb/s max
Speed Grade
-2
Temperature Grade
Industrial
Part 1.3: DDR4 DRAM
The AXKU042 FPGA development board is equipped with four Micron 1GB DDR4
chips, model MT40A512M16LY-062EIT. Four DDR4 SDRAMs form a 64-bit bus width.

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Because four DDR4 chips are connected to the FPGA, the DDR4 SDRAM can run at
speeds up to 1200MHz, and four DDR4 memory systems are directly connected to
the BANK44, BANK45, and BANK46 interfaces of the FPGA. The specific configuration
of DDR4 SDRAM is shown in Table 3-1.
Figure 3-1 DDR4 SDRAM Configuration
Bit Number
Chip Model
Capacity
Factory
U45,U47,U48,U49
MT40A512M16LY-062EIT
512M x 16bit
Micron
The hardware design of DDR4 requires strict consideration of signal integrity. We
have fully considered the matching resistor/terminal resistance, trace impedance
control, and trace length control in circuit design and PCB design to ensure
high-speed and stable operation of DDR3.
The hardware connection mode of FPGA and DDR4 DRAM is shown in Figure
1-3-1:
Figure1-3-1 DDR4 DRAM schematic diagram
4 pieces DDR4 DRAM pin assignments:
Signal Name
FPGA Pin Name
FPGA Pin
PL_DDR4_DQ0
IO_L3N_T0L_N5_AD15N_44
AE20
PL_DDR4_DQ1
IO_L2N_T0L_N3_44
AG20

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PL_DDR4_DQ2
IO_L2P_T0L_N2_44
AF20
PL_DDR4_DQ3
IO_L5P_T0U_N8_AD14P_44
AE22
PL_DDR4_DQ4
IO_L3P_T0L_N4_AD15P_44
AD20
PL_DDR4_DQ5
IO_L6N_T0U_N11_AD6N_44
AG22
PL_DDR4_DQ6
IO_L6P_T0U_N10_AD6P_44
AF22
PL_DDR4_DQ7
IO_L5N_T0U_N9_AD14N_44
AE23
PL_DDR4_DQ8
IO_L8N_T1L_N3_AD5N_44
AF24
PL_DDR4_DQ9
IO_L11P_T1U_N8_GC_44
AJ23
PL_DDR4_DQ10
IO_L8P_T1L_N2_AD5P_44
AF23
PL_DDR4_DQ11
IO_L12N_T1U_N11_GC_44
AH23
PL_DDR4_DQ12
IO_L9N_T1L_N5_AD12N_44
AG25
PL_DDR4_DQ13
IO_L11N_T1U_N9_GC_44
AJ24
PL_DDR4_DQ14
IO_L9P_T1L_N4_AD12P_44
AG24
PL_DDR4_DQ15
IO_L12P_T1U_N10_GC_44
AH22
PL_DDR4_DQ16
IO_L14P_T2L_N2_GC_44
AK22
PL_DDR4_DQ17
IO_L17P_T2U_N8_AD10P_44
AL22
PL_DDR4_DQ18
IO_L15N_T2L_N5_AD11N_44
AM20
PL_DDR4_DQ19
IO_L17N_T2U_N9_AD10N_44
AL23
PL_DDR4_DQ20
IO_L14N_T2L_N3_GC_44
AK23
PL_DDR4_DQ21
IO_L18N_T2U_N11_AD2N_44
AL25
PL_DDR4_DQ22
IO_L15P_T2L_N4_AD11P_44
AL20
PL_DDR4_DQ23
IO_L18P_T2U_N10_AD2P_44
AL24
PL_DDR4_DQ24
IO_L20P_T3L_N2_AD1P_44
AM22
PL_DDR4_DQ25
IO_L23P_T3U_N8_44
AP24
PL_DDR4_DQ26
IO_L20N_T3L_N3_AD1N_44
AN22
PL_DDR4_DQ27
IO_L21N_T3L_N5_AD8N_44
AN24
PL_DDR4_DQ28
IO_L24P_T3U_N10_44
AN23
PL_DDR4_DQ29
IO_L23N_T3U_N9_44
AP25
PL_DDR4_DQ30
IO_L24N_T3U_N11_44
AP23
PL_DDR4_DQ31
IO_L21P_T3L_N4_AD8P_44
AM24
PL_DDR4_DQ32
IO_L2P_T0L_N2_46
AM26
PL_DDR4_DQ33
IO_L6P_T0U_N10_AD6P_46
AJ28
PL_DDR4_DQ34
IO_L2N_T0L_N3_46
AM27
PL_DDR4_DQ35
IO_L6N_T0U_N11_AD6N_46
AK28
PL_DDR4_DQ36
IO_L5P_T0U_N8_AD14P_46
AH27

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PL_DDR4_DQ37
IO_L5N_T0U_N9_AD14N_46
AH28
PL_DDR4_DQ38
IO_L3P_T0L_N4_AD15P_46
AK26
PL_DDR4_DQ39
IO_L3N_T0L_N5_AD15N_46
AK27
PL_DDR4_DQ40
IO_L9N_T1L_N5_AD12N_46
AN28
PL_DDR4_DQ41
IO_L12N_T1U_N11_GC_46
AM30
PL_DDR4_DQ42
IO_L8P_T1L_N2_AD5P_46
AP28
PL_DDR4_DQ43
IO_L11N_T1U_N9_GC_46
AM29
PL_DDR4_DQ44
IO_L9P_T1L_N4_AD12P_46
AN27
PL_DDR4_DQ45
IO_L12P_T1U_N10_GC_46
AL30
PL_DDR4_DQ46
IO_L11P_T1U_N8_GC_46
AL29
PL_DDR4_DQ47
IO_L8N_T1L_N3_AD5N_46
AP29
PL_DDR4_DQ48
IO_L14P_T2L_N2_GC_46
AK31
PL_DDR4_DQ49
IO_L18P_T2U_N10_AD2P_46
AH34
PL_DDR4_DQ50
IO_L14N_T2L_N3_GC_46
AK32
PL_DDR4_DQ51
IO_L15N_T2L_N5_AD11N_46
AJ31
PL_DDR4_DQ52
IO_L15P_T2L_N4_AD11P_46
AJ30
PL_DDR4_DQ53
IO_L17P_T2U_N8_AD10P_46
AH31
PL_DDR4_DQ54
IO_L18N_T2U_N11_AD2N_46
AJ34
PL_DDR4_DQ55
IO_L17N_T2U_N9_AD10N_46
AH32
PL_DDR4_DQ56
IO_L21P_T3L_N4_AD8P_46
AN31
PL_DDR4_DQ57
IO_L24P_T3U_N10_46
AL34
PL_DDR4_DQ58
IO_L23N_T3U_N9_46
AN32
PL_DDR4_DQ59
IO_L20P_T3L_N2_AD1P_46
AN33
PL_DDR4_DQ60
IO_L23P_T3U_N8_46
AM32
PL_DDR4_DQ61
IO_L24N_T3U_N11_46
AM34
PL_DDR4_DQ62
IO_L21N_T3L_N5_AD8N_46
AP31
PL_DDR4_DQ63
IO_L20N_T3L_N3_AD1N_46
AP33
PL_DDR4_DM0
IO_L1P_T0L_N0_DBC_44
AD21
PL_DDR4_DM1
IO_L7P_T1L_N0_QBC_AD13P_44
AE25
PL_DDR4_DM2
IO_L13P_T2L_N0_GC_QBC_44
AJ21
PL_DDR4_DM3
IO_L19P_T3L_N0_DBC_AD9P_44
AM21
PL_DDR4_DM4
IO_L1P_T0L_N0_DBC_46
AH26
PL_DDR4_DM5
IO_L7P_T1L_N0_QBC_AD13P_46
AN26
PL_DDR4_DM6
IO_L13P_T2L_N0_GC_QBC_46
AJ29
PL_DDR4_DM7
IO_L19P_T3L_N0_DBC_AD9P_46
AL32

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PL_DDR4_DQS0_P
IO_L4P_T0U_N6_DBC_AD7P_44
AG21
PL_DDR4_DQS0_N
IO_L4N_T0U_N7_DBC_AD7N_44
AH21
PL_DDR4_DQS1_P
IO_L10P_T1U_N6_QBC_AD4P_44
AH24
PL_DDR4_DQS1_N
IO_L10N_T1U_N7_QBC_AD4N_44
AJ25
PL_DDR4_DQS2_P
IO_L16P_T2U_N6_QBC_AD3P_44
AJ20
PL_DDR4_DQS2_N
IO_L16N_T2U_N7_QBC_AD3N_44
AK20
PL_DDR4_DQS3_P
IO_L22P_T3U_N6_DBC_AD0P_44
AP20
PL_DDR4_DQS3_N
IO_L22N_T3U_N7_DBC_AD0N_44
AP21
PL_DDR4_DQS4_P
IO_L4P_T0U_N6_DBC_AD7P_46
AL27
PL_DDR4_DQS4_N
IO_L4N_T0U_N7_DBC_AD7N_46
AL28
PL_DDR4_DQS5_P
IO_L10P_T1U_N6_QBC_AD4P_46
AN29
PL_DDR4_DQS5_N
IO_L10N_T1U_N7_QBC_AD4N_46
AP30
PL_DDR4_DQS6_P
IO_L16P_T2U_N6_QBC_AD3P_46
AH33
PL_DDR4_DQS6_N
IO_L16N_T2U_N7_QBC_AD3N_46
AJ33
PL_DDR4_DQS7_P
IO_L22P_T3U_N6_DBC_AD0P_46
AN34
PL_DDR4_DQS7_N
IO_L22N_T3U_N7_DBC_AD0N_46
AP34
PL_DDR4_A0
IO_L18N_T2U_N11_AD2N_45
AG14
PL_DDR4_A1
IO_L23N_T3U_N9_45
AF17
PL_DDR4_A2
IO_L20P_T3L_N2_AD1P_45
AF15
PL_DDR4_A3
IO_L16N_T2U_N7_QBC_AD3N_45
AJ14
PL_DDR4_A4
IO_L19N_T3L_N1_DBC_AD9N_45
AD18
PL_DDR4_A5
IO_L15P_T2L_N4_AD11P_45
AG17
PL_DDR4_A6
IO_L23P_T3U_N8_45
AE17
PL_DDR4_A7
IO_L11N_T1U_N9_GC_45
AK18
PL_DDR4_A8
IO_L24P_T3U_N10_45
AD16
PL_DDR4_A9
IO_L13P_T2L_N0_GC_QBC_45
AH18
PL_DDR4_A10
IO_L19P_T3L_N0_DBC_AD9P_45
AD19
PL_DDR4_A11
IO_L24N_T3U_N11_45
AD15
PL_DDR4_A12
IO_L14P_T2L_N2_GC_45
AH16
PL_DDR4_A13
IO_L10N_T1U_N7_QBC_AD4N_45
AL17
PL_DDR4_BA0
IO_L18P_T2U_N10_AD2P_45
AG15
PL_DDR4_BA1
IO_L10P_T1U_N6_QBC_AD4P_45
AL18
PL_DDR4_BG0
IO_L16P_T2U_N6_QBC_AD3P_45
AJ15
PL_DDR4_WE_B
IO_L9N_T1L_N5_AD12N_45
AL15
PL_DDR4_RAS_B
IO_L8N_T1L_N3_AD5N_45
AM19

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PL_DDR4_CAS_B
IO_L8P_T1L_N2_AD5P_45
AL19
PL_DDR4_CKE
IO_L14N_T2L_N3_GC_45
AJ16
PL_DDR4_ACT_B
IO_L21N_T3L_N5_AD8N_45
AF18
PL_DDR4_CLK_N
IO_L22N_T3U_N7_DBC_AD0N_45
AE15
PL_DDR4_CLK_P
IO_L22P_T3U_N6_DBC_AD0P_45
AE16
PL_DDR4_CS_B
IO_L21P_T3L_N4_AD8P_45
AE18
PL_DDR4_OTD
IO_L17P_T2U_N8_AD10P_45
AG19
PL_DDR4_PAR
IO_L20N_T3L_N3_AD1N_45
AF14
PL_DDR4_RST
IO_L15N_T2L_N5_AD11N_45
AG16
Part 1.4: QSPI Flash
The AXKU042 FPGA development board is equipped with two 128MBit Quad-SPI
FLASH, and the model is N25Q128A, which uses the 3.3V CMOS voltage standard.
Due to the non-volatile nature of QSPI FLASH, it can store FPGA configuration Bin
files and other user data files in use. The specific models and related parameters of
QSPI FLASH are shown in Figure 4-1.
Position
Model
Capacity
Factory
U14
N25Q128A
128Mbit
Numonyx
Figure 4-1 QSPI Flash Specification
QSPI FLASH is connected to the dedicated pins of BANK0 of the FPGA chip. The
clock pin is connected to CCLK0 of BANK0, and other data signals are connected to
D00~D03 and FCS pins. Figure 4-2 shows the hardware connection of QSPI Flash and
FPGA Chip.
Figure 1-4-2 QSPI Flash Schematic
QSPI Flash pin assignments：

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Signal Name
FPGA Pin Name
FPGA Pin
QSPI_CCLK
CCLK_0
AA9
QSPI0_CS_B
RDWR_FCS_B_0
U7
QSPI0_IO0
D00_MOSI_0
AC7
QSPI0_IO1
D01_DIN_0
AB7
QSPI0_IO2
D02_0
AA7
QSPI0_IO3
D03_0
Y7
Signal Name
FPGA Pin Name
FPGA Pin
QSPI_CCLK
CCLK_0
AA9
QSPI1_CS_B
IO_L2N_T0L_N3_FWE_FCS2_B_65
G26
QSPI1_IO0
IO_L22P_T3U_N6_DBC_AD0P_D04_65
M20
QSPI1_IO1
IO_L22N_T3U_N7_DBC_AD0N_D05_65
L20
QSPI1_IO2
IO_L21P_T3L_N4_AD8P_D06_65
R21
QSPI1_IO3
IO_L21N_T3L_N5_AD8N_D07_65
R22
Part 1.5: Clock configuration
200Mhz differential clock source
A differential 200MHz clock source is provided on the FPGA development board
to provide the system clock to the FPGA. The crystal differential output is connected
to the FPGA BANK45, which can be used to drive the DDR controller operating clock
and other user logic in the FPGA. The schematic diagram of the clock source is shown
in Figure 1-5-1.
Figure 1-5-1

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System Clock pin assignments：
Signal Name
FPGA Pin
PL_CLK0_P
AK17
PL_CLK0_N
AK16
Part 1.6: LED Light
There are two red LEDs on the AXKU042 FPGA development board, one of which
is the power indicator (PWR), one is DONE indicator. When the AXKU042 FPGA board
is powered on, the power indicator and DONE indicator will light up; when the
AXKU042 FPGA is configured, the DONE LED will light up;
The LEDs hardware connection is shown in Figure 1-6-1.
Figure 1-6-1 The LED lights hardware connection diagram
Part 1.7: Power Supply
The power input voltage of the AXKU042 FPGA development board is DC12V,
and the power supply is provided by carrier board. The power supply design diagram
on the board is shown in Figure 1-7-1 below:

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Figure 1-7-1 Power Supply schematic diagram
+12V generates+0.95V FPGA core power through the DCDC power chip
MYMGK1R820ERSR. The output current of the MYMGK1R820FRSR is as high as 20A,
which far meets the core voltage current demand.Then + 12V power supply through
the DCDC chip ETA1471 is generated four power supplies:+1.2V,+1.8V+3.3V, and
MGTAVTT. The MGTAVCC used in the GTX transceiver is generated by the DCDC chip
ETA8156, and an LDO chip SPX3819-1-8 is used to generate the auxiliary power
supply of the GTX+1.8V. The VTT and VREF voltages of DDR4 are generated by
TPS51200.

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Part 1.8: Size Dimension
Top View
Part 1.9: Board to Board Connectors pin assignment
The core board expands a total of six high-speed expansion connectors, and uses
four 120-Pin inter-board connectors (J1,J3,J4,J5) and the two 80-Pin inter-board
connectors (J2,J6) to connect to the carrier board. The connector uses Panasonic's
AXK5A2137YG and AXK580137YG. The connectors of corresponding carrier plates are
AXK6A2337YG and AXK680337YG. J1 is connected to the IO of BANK66 and BANK68,
and the power is 1.8V.
Pin assignment of J1 connector
J1 Pin
Signal Name
FPGA Pin
J1 Pin
Signal Name
FPGA Pin
1
B66_L3_N
C8
2
B66_L1_N
E8
3
B66_L3_P
D8
4
B66_L1_P
F8
5
B66_L7_N
K8
6
B66_L2_N
A9
7
B66_L7_P
L8
8
B66_L2_P
B9

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9
GND
-
10
GND
-
11
B66_L9_N
H8
12
B66_L4_N
A10
13
B66_L9_P
J8
14
B66_L4_P
B10
15
B66_L8_N
H9
16
B66_L11_N
F9
17
B66_L8_P
J9
18
B66_L11_P
G9
19
GND
-
20
GND
-
21
B66_L10_N
J10
22
B66_L12_N
F10
23
B66_L10_P
K10
24
B66_L12_P
G10
25
B66_L5_N
C9
26
B66_L6_N
D10
27
B66_L5_P
D9
28
B66_L6_P
E10
29
GND
-
30
GND
-
31
B66_L17_N
K12
32
B66_L13_N
G11
33
B66_L17_P
L12
34
B66_L13_P
H11
35
B66_L19_N
D11
36
B66_L15_N
J11
37
B66_L19_P
E11
38
B66_L15_P
K11
39
GND
-
40
GND
-
41
B66_L16_N
K13
42
B66_L14_N
G12
43
B66_L16_P
L13
44
B66_L14_P
H12
45
B66_L20_N
B12
46
B66_L18_N
H13
47
B66_L20_P
C12
48
B66_L18_P
J13
49
GND
-
50
GND
-
51
B66_L22_N
E13
52
B66_L21_N
B11
53
B66_L22_P
F13
54
B66_L21_P
C11
55
B66_L24_N
C13
56
B66_L23_N
A12
57
B66_L24_P
D13
58
B66_L23_P
A13
59
GND
-
60
GND
-
61
B68_L9_N
F14
62
B68_L19_N
J14
63
B68_L9_P
F15
64
B68_L19_P
J15
65
B68_L8_N
D15
66
B68_L21_N
K15
67
B68_L8_P
E15
68
B68_L21_P
L15
69
GND
-
70
GND
-
71
B68_L15_N
G14
72
B68_L11_N
D16
73
B68_L15_P
G15
74
B68_L11_P
E16
75
B68_L20_N
K17
76
B68_L23_N
J16
77
B68_L20_P
K18
78
B68_L23_P
K16

KINTEX UltraScale+ FPGA Board AXKU042User Manual
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79
GND
-
80
GND
-
81
B68_L16_N
F19
82
B68_L10_N
D18
83
B68_L16_P
G19
84
B68_L10_P
D19
85
B68_L18_N
H18
86
B68_L1_N
A14
87
B68_L18_P
H19
88
B68_L1_P
B14
89
GND
-
90
GND
-
91
B68_L22_N
J18
92
B68_L3_N
A15
93
B68_L22_P
J19
94
B68_L3_P
B15
95
B68_L24_N
L18
96
B68_L5_N
B16
97
B68_L24_P
L19
98
B68_L5_P
B17
99
GND
-
100
GND
-
101
B68_L13_N
G16
102
B68_L7_N
C14
103
B68_L13_P
G17
104
B68_L7_P
D14
105
B68_L14_N
F17
106
B68_L6_N
C17
107
B68_L14_P
F18
108
B68_L6_P
C18
109
GND
-
110
GND
-
111
B68_L12_N
E17
112
B68_L2_N
A18
113
B68_L12_P
E18
114
B68_L2_P
A19
115
B68_L17_N
H16
116
B68_L4_N
B19
117
B68_L17_P
H17
118
B68_L4_P
C19
119
GND
-
120
GND
-
J2 connector 80 Pin, connect the high speed differential signal of transceiver BANK226~228.
Pin assignment of J2 connector
J2 Pin
Signal Name
FPGA Pin
J2 Pin
Signal Name
FPGA Pin
1
GND
-
2
GND
-
3
226_TX2_N
U3
4
226_RX2_N
T1
5
226_TX2_P
U4
6
226_RX2_P
T2
7
GND
-
8
GND
-
9
226_TX3_N
R3
10
226_RX3_N
P1
11
226_TX3_P
R4
12
226_RX3_P
P2
13
GND
-
14
GND
-
15
226_CLK1_N
T5
16
226_CLK0_N
V5
17
226_CLK1_P
T6
18
226_CLK0_P
V6
19
GND
-
20
GND
-

KINTEX UltraScale+ FPGA Board AXKU042 User Manual
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21
227_TX0_P
N4
22
227_RX0_P
M2
23
227_TX0_N
N3
24
227_RX0_N
M1
25
GND
-
26
GND
-
27
227_TX1_P
L4
28
227_RX1_P
K2
29
227_TX1_N
L3
30
227_RX1_N
K1
31
GND
-
32
GND
-
33
227_TX2_P
J4
34
227_RX2_P
H2
35
227_TX2_N
J3
36
227_RX2_N
H1
37
GND
-
38
GND
-
39
227_TX3_P
G4
40
227_RX3_P
F2
41
227_TX3_N
G3
42
227_RX3_N
F1
43
GND
-
44
GND
-
45
227_CLK1_P
M6
46
227_CLK0_P
P6
47
227_CLK1_N
M5
48
227_CLK0_N
P5
49
GND
-
50
GND
-
51
228_TX0_P
F6
52
228_RX0_P
E4
53
228_TX0_N
F5
54
228_RX0_N
E3
55
GND
-
56
GND
-
57
228_TX1_P
D6
58
228_RX1_P
D2
59
228_TX1_N
D5
60
228_RX1_N
D1
61
GND
-
62
GND
-
63
228_TX2_P
C4
64
228_RX2_P
B2
65
228_TX2_N
C3
66
228_RX2_N
B1
67
GND
-
68
GND
-
69
228_TX3_P
B6
70
228_RX3_P
A4
71
228_TX3_N
B5
72
228_RX3_N
A3
73
GND
-
74
GND
-
75
228_CLK1_P
H6
76
228_CLK0_P
K6
77
228_CLK1_N
H5
78
228_CLK0_N
K5
79
GND
-
80
GND
-
J3 is the high-speed difference signal of the transceiver BANK224~226 and the partial signal of
BANK64, BANK65
Pin assignment of J3 connector
J3 Pin
Signal Name
FPGA Pin
J3 Pin
Signal Name
FPGA Pin
1
B64_L7_N
AF13
2
B64_L21_N
AL9