Alinx ZYNQ7000 FPGA User manual

ZYNQ7000 FPGA
Development Board
AC7021BB
System on Module

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Version Record
Version
Date
Release By
Description
Rev 1.0
2020-06-29
Rachel Zhou
First Release

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Table of Contents
Version Record 2
Part 1: AC7021B Core Board Introduction 4
Part 2: ZYQN Chip 6
Part 3 DDR3 DRAM 8
Part 4 QSPI Flash 11
Part 5: eMMC Flash 12
Part 6: Clock configuration 14
Part 7: USB to serial port 16
Part 8: LED 17
Part 9: Reset button 19
Part 10: JTAGE Interface 20
Part 11: DIP switch configuration 21
Part 12: Power 21
Part 13 Structure diagram: 24
Part 14: Connector pin definition 24

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Part 1: AC7021B Core Board Introduction
The AC7021B (core board model, the same below) core board is an FPGA
development board based on the Zynq chip XC7Z020-2CLG484I of the XILINX
ZYNQ7000 series. The ZYNQ chip's PS system integrates two ARM CortexTM-
A9 processors, AMBA® interconnects, internal memory, external memory
interfaces and peripherals. The ZYNQ FPGA chip contains a wide range of
programmable logic cells, DSP and internal RAM.
The core board uses two SK Hynix DDR3 chips (H5TQ4G63AFR-PBI),
each with a 4Gbit DDR capacity; two DDR chips form a 32-bit data bus width,
and the read and write data clock frequency between ZYNQ FPGA and DDR3
is up to 533Mhz; such a configuration can meet the system's high bandwidth
data processing needs
In order to connect to the carrier board, the four board-to-board connectors
of the core board extend the USB interface of the PS side, the Gigabit Ethernet
interface, the SD card interface and other remaining MIO ports. As well as
almost all IO ports (198) of BANK13, BANK33, BAN34 and BANK35 on the PL
side, the level of IO of BANK33 and BANK34 can be modified by replacing the
LDO chip on the core board to meet the requirements of users with different
level interfaces. For users who need a lot of IOs, this core board will be a good
choice. Moreover, the IOs connection part, the routing between the ZYNQ
FPGA chip and the interface is equal length and differential processing. The
core board size is only 2.36 inch* 2.36 inch, which is very suitable for
secondary development.

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Figure 1-1: AC7021BCore board Front View
Figure 1-2:AC7021B core board rear view

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Part 2: ZYQN Chip
The development board uses Xilinx's Zynq7000 series chip, model
XC7Z020-2CLG484I. The chip's PS system integrates two ARM CortexTM-A9
processors, AMBA® interconnects, internal memory, external memory
interfaces and peripherals. These peripherals mainly include USB bus interface,
Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface,
UART interface, GPIO, etc. The PS can operate independently and start up at
power up or reset. Figure 2-1 detailed the Overall Block Diagram of the
ZYNQ7000 Chip.
Figure 2-1: Overall Block Diagram of the ZYNQ7000 Chip
The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 1GHz
32KB level 1 instruction and data cache per CPU, 512KB level 2 cache 2
CPU shares
On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3 interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,

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SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
4 groups of 32bit GPIO, 54 (32+22) as PS system IO, 64 connected to
PL
High bandwidth connection within PS and PS to PL
The main parameters of the PL logic part are as follows:
LogicCells: 85K
Look-up-tables (LUTs):53,200
Flip-flops:106,400
18x25MACCs：220;
 BlockRAM ： 4.9Mb
Two AD converters for on-chip voltage, temperature sensing and up
to 17 external differential input channels, 1MBPS
XC7Z020-2CLG484I chip speed grade is -2, industrial grade, package is
BGA484, pin pitch is 0.024 inch, the specific chip model definition of ZYNQ7000
series is shown in Figure 2-2
Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series

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Figure 2-3: TheXC7Z020 chip used on the Core Board
Part 3 DDR3 DRAM
The AC7021B core board is equipped with two SK Hynix DDR3 SDRAM
chips (1GB total), model H5TQ4G63AFR-PBI. The bus width of DDR3 SDRAM
is 32 bits in total. DDR3 SDRAM has a maximum operating speed of 533MHz
(data rate 1066Mbps). The DDR3 memory system is directly connected to the
memory interface of the BANK 502 of the ZYNQ Processing System (PS). The
specific configuration of DDR3 SDRAM is shown in Table 3-1
Table 3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Bit Number
Chip Model
Capacity
Factory
U5,U6
H5TQ4G63AFR-PBI
256M x 16bit
SK Hynix

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The hardware connection of DDR3 DRAM is shown in Figure 3-1:
Figure 3-1: The Schematic part of DDR3 DRAM
Figure 3-2: DDR3 DRAM on the Core Board

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DDR3 DRAM Pin Assignment
Signal Name
ZYNQ Pin Name
Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C2
DDR3_DQS0_N
PS_DDR_DQS_N0_502
D2
DDR3_DQS1_P
PS_DDR_DQS_P1_502
H2
DDR3_DQS1_N
PS_DDR_DQS_N1_502
J2
DDR3_DQS2_P
PS_DDR_DQS_P2_502
N2
DDR3_DQS2_N
PS_DDR_DQS_N2_502
P2
DDR3_DQS3_P
PS_DDR_DQS_P3_502
V2
DDR3_DQS4_N
PS_DDR_DQS_N3_502
W2
DDR3_D0
PS_DDR_DQ0_502
D1
DDR3_D1
PS_DDR_DQ1_502
C3
DDR3_D2
PS_DDR_DQ2_502
B2
DDR3_D3
PS_DDR_DQ3_502
D3
DDR3_D4
PS_DDR_DQ4_502
E3
DDR3_D5
PS_DDR_DQ5_502
E1
DDR3_D6
PS_DDR_DQ6_502
F2
DDR3_D7
PS_DDR_DQ7_502
F1
DDR3_D8
PS_DDR_DQ8_502
G2
DDR3_D9
PS_DDR_DQ9_502
G1
DDR3_D10
PS_DDR_DQ10_502
L1
DDR3_D11
PS_DDR_DQ11_502
L2
DDR3_D12
PS_DDR_DQ12_502
L3
DDR3_D13
PS_DDR_DQ13_502
K1
DDR3_D14
PS_DDR_DQ14_502
J1
DDR3_D15
PS_DDR_DQ15_502
K3
DDR3_D16
PS_DDR_DQ16_502
M1
DDR3_D17
PS_DDR_DQ17_502
T3
DDR3_D18
PS_DDR_DQ18_502
N3
DDR3_D19
PS_DDR_DQ19_502
T1
DDR3_D20
PS_DDR_DQ20_502
R3
DDR3_D21
PS_DDR_DQ21_502
T2
DDR3_D22
PS_DDR_DQ22_502
M2
DDR3_D23
PS_DDR_DQ23_502
R1
DDR3_D24
PS_DDR_DQ24_502
AA3
DDR3_D25
PS_DDR_DQ25_502
U1
DDR3_D26
PS_DDR_DQ26_502
AA1
DDR3_D27
PS_DDR_DQ27_502
U2
DDR3_D28
PS_DDR_DQ28_502
W1
DDR3_D29
PS_DDR_DQ29_502
Y3
DDR3_D30
PS_DDR_DQ30_502
W3
DDR3_D31
PS_DDR_DQ31_502
Y1
DDR3_DM0
PS_DDR_DM0_502
B1
DDR3_DM1
PS_DDR_DM1_502
H3
DDR3_DM2
PS_DDR_DM2_502
P1
DDR3_DM3
PS_DDR_DM3_502
AA2
DDR3_A0
PS_DDR_A0_502
M4
DDR3_A1
PS_DDR_A1_502
M5
DDR3_A2
PS_DDR_A2_502
K4
DDR3_A3
PS_DDR_A3_502
L4
DDR3_A4
PS_DDR_A4_502
K6
DDR3_A5
PS_DDR_A5_502
K5
DDR3_A6
PS_DDR_A6_502
J7
DDR3_A7
PS_DDR_A7_502
J6
DDR3_A8
PS_DDR_A8_502
J5

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DDR3_A9
PS_DDR_A9_502
H5
DDR3_A10
PS_DDR_A10_502
J3
DDR3_A11
PS_DDR_A11_502
G5
DDR3_A12
PS_DDR_A12_502
H4
DDR3_A13
PS_DDR_A13_502
F4
DDR3_A14
PS_DDR_A14_502
G4
DDR3_BA0
PS_DDR_BA0_502
L7
DDR3_BA1
PS_DDR_BA1_502
L6
DDR3_BA2
PS_DDR_BA2_502
M6
DDR3_S0
PS_DDR_CS_B_502
P6
DDR3_RAS
PS_DDR_RAS_B_502
R5
DDR3_CAS
PS_DDR_CAS_B_502
P3
DDR3_WE
PS_DDR_WE_B_502
R4
DDR3_ODT
PS_DDR_ODT_502
P5
DDR3_RESET
PS_DDR_DRST_B_502
F3
DDR3_CLK0_P
PS_DDR_CKP_502
N4
DDR3_CLK0_N
PS_DDR_CKN_502
N5
DDR3_CKE
PS_DDR_CKE_502
V3
Table 3-2: DDR3 DRAM Pin Assignment
Part 4 QSPI Flash
The core board is equipped with a 256MBit Quad-SPI FLASH chip, model
W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the non-
volatile nature of QSPI FLASH, it can be used as a boot device for the system
to store the boot image of the system. These images mainly include FPGA bit
files, ARM application code, and other user data files. The specific models and
related parameters of QSPI FLASH are shown in Table 4-1.
Position
Model
Capacity
Factory
U7
W25Q256FVEI
32M Byte
Winbond
Table 4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure 4-1
shows the QSPI Flash in the schematic.

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ZYNQ QSPI FLASH
(W25Q256F)
QSPI_CS
U7
U1
BANK
500
QSPI_SCK
QSPI_D0~QSPI_D3
Figure 4-1: QSPI Flash in the schematic
Figure 4-2: QSPI Flash on the Core Board
Pin Assignment of QSPI Flash
Signal Name
ZYNQ Pin Name
Pin Number
QSPI_SCK
PS_MIO6_500
A4
QSPI_CS
PS_MIO1_500
A1
QSPI_D0
PS_MIO2_500
A2
QSPI_D1
PS_MIO3_500
F6
QSPI_D2
PS_MIO4_500
E4
QSPI_D3
PS_MIO5_500
A3
Table 4-2: Pin Assignment of QSPI FLASH
Part 5: eMMC Flash
The core board is equipped with a large capacity 32GB eMMC FLASH chip,
model THGBMFG8C2LBAIL, which supports the JEDEC e-MMC V5.0 standard
HS-MMC interface with level support of 1.8V or 3.3V. The data width of the

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eMMC FLASH and ZYNQ connections is 4 bits. Due to the large capacity and
non-volatile nature of eMMC FLASH, it can be used as a large-capacity storage
device for the ZYNQ system, such as ARM-based applications, system files,
and other user data files. The specific models and related parameters of eMMC
FLASH are shown in Table 5-1：
Position
Model
Capacity
Factory
U33
THGBMFG8C2LBAIL
32G Byte
TOSHIBA
Table 5-1: eMMC FLASH Specification
eMMC FLASH is connected to the GPIO port of the BANK501 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the SD interface. Figure 5-1 shows the
eMMC Flash in the schematic.
ZYNQ eMMC
(THGBMFG8C2
LBAIL)
MMC_CCLK
U33
U1
BANK
501
MMC_CMD
MMC_DAT0~MMC_DAT3
Figure 5-1: eMMC Flash in the Schematic

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Figure 5-2: eMMC Flash on the Core Board
Pin Assignment of eMMC Flash
Signal Name
ZYNQ Pin Name
Pin Number
MMC_CCLK
PS_MIO48_501
D11
MMC_CMD
PS_MIO47_501
B10
MMC_D0
PS_MIO46_501
D12
MMC_D1
PS_MIO49_501
C14
MMC_D2
PS_MIO50_501
D13
MMC_D3
PS_MIO51_501
C10
Table 5-2: Pin Assignment of eMMC FLASH
Part 6: Clock configuration
The AC7021B core board provides active clocks for the PS system and the
PL logic sections, respectively, so that the PS system and the PL logic can
work independently.
PS system clock source
The ZYNQ chip provides a 33.333 MHz clock input to the PS section
through the X1 crystal on the development board. The input of the clock is
connected to the pins of PS_CLK_500 of the BANK500 of the ZYNQ chip. The
schematic diagram is shown in Figure 6-1:

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Figure 6-1: Active crystal oscillator to the PS section
Figure 6-2: 33.333Mhz active Crystal Oscillator on the Core Board
PS Clock pin assignment:
Signal Name
Pin
PS_CLK_500
F7
Table 6-1: PS Clock pin assignment
PL system clock source
The AC7021B core board provides a single-ended 50MHz PL system clock
source with 3.3V power supply. The crystal output is connected to the global
clock (MRCC) of the FPGA BANK13, which can be used to drive user logic
within the FPGA. The schematic diagram of the clock source is shown in Figure
6-3:
Figure 6-3: PL system clock source

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Figure 6-4: 50Mhz active crystal oscillator on the Core Board
PL Clock pin assignment:
Signal Name
Pin
PL_GCLK
Y9
Table 6-2: PL Clock pin assignment
Part 7: USB to serial port
For the AC7021B core board to work and debug separately, we have a
Uart to USB interface for the core board. Used for separate power supply and
debugging of the core board. The conversion chip uses the USB-UART chip of
Silicon Labs CP2102GM. The USB interface uses the MINI USB interface. It
can be connected to the USB port of the upper PC with a USB cable for
separate power supply and serial data communication of the core board.
Micro USB
ZYNQ UART-USB
(CP2102-GM)
UART_TXD
U13
U1
BANK
500 UART_RXD
J2
TXD
RXD
D+/-
VBUS
REGIN
Figure 7-1: USB to Serial Port

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Figure 7-2: USB to Serial Port on the Core Board
At the same time, two LED indicators are set on the serial port signal, and
the LEDs on the PCB are printed as RX and TX LEDs (D5 and D6). The RX
and TX LEDs indicate whether the serial port has data received or sent, as
shown in the Figure 7-3 below.
Figure 7-3: USB to serial port signal indicator
Uart Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
UART_RXD
PS_MIO14_500
B6
Uart data output
UART_TXD
PS_MIO15_500
E6
Uart data input
Table 7-1: Uart Pin Assignment
Part8: LED
There are 6 red LED lights on the AC7021B core board, one of which is the
power indicator light (PWR), one is the configuration LED light (DONE), two are

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the user LED lights (LED1~LED2), and the other two are the UART transmit
and receive indicators (TX, RX). When the core board is powered, the power
indicator will illuminate; when the FPGA is configured, the configuration LED
will illuminate. Two user LED lights are connected to the MIO of the PS, one is
connected to the IO of the PL, the user can control the lighting and off by the
program, when the IO voltage connected to the user LED light is high, the user
LED light is off. When the connection IO voltage is low, the user LED will be
illuminated. The schematic diagram of the LED light hardware connection is
shown in Figure 8-1:
ZYNQ
U1
BANK
500
BANK
13
3.3V 3.3V
LED1 LED2
BANK
0
3.3V
DONE
PWR
3.3V
Figure 8-1: The schematic diagram of the LED light hardware connection

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Figure 8-2: The LEDs on the Core Board
LED Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
MIO0_LED
PS_MIO0_500
G6
User LED1
PL_LED
IO_0_13
R7
User LED2
Table 8-1: LED Pin Assignment
Part 9: Reset button
The AC7021B has a reset button RESET and circuitry on the core board.
The reset signal is connected to the PS reset pin of the ZYNQ chip. The reset
button can be used by the user to reset the ZYNQ system. When the reset
button is pressed, the reset chip will generate a low level reset signal to the
ZYNQ chip. The schematic diagram of the reset button and reset chip
connection is shown in Figure 9-1:

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ZYNQ
U1
BANK
500
RESET
Reset
chip
(TCM811)
PS_POR_B
U3
Figure 9-1: Reset button connection diagram
Figure 9-2: Reset Button on the Core Board
Reset Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PS_POR_B
PS_POR_B_500
B5
Reset Key
Table 9-1: Reset Pin Assignment
Part 10: JTAGE Interface
The JTAG test socket J1 is reserved on the AC7021B core board for
separate JTAG download and debugging of the core board. Figure 10-1 is the
schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK, GND. ,
+3.3V these six signals.
Figure 10-1: JTAG interface part of the core board schematic