Alinx ZYNQ UltraScale+ AXU5EV-E User manual

ZYNQ UltraScale+
FPGA Development Board
AXU5EV-E
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.1
2021-04-23
Rachel Zhou
First Release

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Table of Contents
Version Record.......................................................................................................2
Part 1: FPGA Development Board Introduction............................................... 6
Part 2: ACU5EV Core Board............................................................................. 10
Part 2.1: ACU5EV Core Board Introduction........................................... 10
Part 2.2: ZYNQ Chip................................................................................... 11
Part 2.3: DDR4 DRAM............................................................................... 13
Part 2.4: QSPI Flash...................................................................................20
Part 2.5: eMMC Flash.................................................................................21
Part 2.6: Clock configuration..................................................................... 23
Part 2.7: LED................................................................................................25
Part 2.8: Power Supply...............................................................................26
Part 2.9: ACU5EV Core Board Size Dimension.................................... 27
Part 2.10: Board to Board Connectors pin assignment........................27
Part 3: Carrier Board...........................................................................................36
Part 3.1: Carrier Board Introduction.........................................................36
Part 3.2: M.2 Interface................................................................................37
Part 3.3: DP Interface................................................................................. 38
Part 3.4: USB3.0 interface.........................................................................40
Part 3.5: Gigabit Ethernet Interface......................................................... 41
Part 3.6: USB to Serial Port.......................................................................43
Part 3.7: SD Card Slot Interface...............................................................44
Part 3.8: 40-Pin Expansion Header......................................................... 45
Part 3.9: CAN communication interface..................................................47
Part 3.10: 485 communication interface................................................. 48
Part 3.11: MIPI camera interface..............................................................49
Part 3.12: JTAG Debug Port......................................................................50
Part 3.13: Real-time clock..........................................................................51

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Part 3.14: EEPROM and Temperature sensor.......................................51
Part 3.15: User LEDs..................................................................................52
Part 3.16: Keys............................................................................................ 53
Part 3.17: DIP Switch Configuration........................................................ 54
Part 3.18: Power Supply............................................................................ 54
Part 3.19: ALINX Customized Fan........................................................... 55
Part 3.20: Carrier Board Size Dimension................................................56

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This MPSoCs FPGA development platform adopts the core board + carrier
board mode, which is convenient for users to use the core board for secondary
development. The core board uses XILINX Zynq UltraScale+ EV chip ZU5EV
solution, uses Processing System(PS)+Programmable Logic(PL) technology to
integrate dual-core ARM ARM Cortex-A53 and FPGA programmable logic on a
single chip. In addition, the PS side of the core board has 4 pieces of 1GB
high-speed DDR4 SDRAM chips, 1 piece of 8GB eMMC memory chip and 1
piece of 256Mb QSPI FLASH chip; the PL side of the core board has 1 piece of
1GB DDR4 SDRAM chip
In the design of carrier board, we have extended a wealth of interfaces for
users, such as 1 SATA M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2
Gigabit Ethernet interfaces, 1 SD card slot,2-Channel 40-pin expansion header,
2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI
Camera Interface. It meets users' requirements for high-speed data exchange,
data storage, Video transmission processing, deep learning, artificial
intelligence and industrial control. It is a "professional" ZYNQ development
platform. For high-speed data transmission and exchange, pre-verification and
post-application of data processing is possible. This product is very suitable for
students, engineers and other groups engaged in MPSoCs development.

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Part 1: FPGA Development Board Introduction
The entire structure of the AXU5EV-E FPGA development board is
inherited from our consistent core board + carrier board model. A high-speed
inter-board connector is used between the core board and the carrier board.
The core board is mainly composed of the smallest system of ZU5EV + 5
DDR4 + eMMC + QSPI FLASH, ACU5EV uses Xilinx's Zynq UltraScale+
MPSoCs EV chip, the model number isXCZU5EV-2SFVC784I. ZU5EV chip
can be divided into processor system part Processor System (PS) and
programmable logic part Programmable Logic (PL). On the PS side and PL
side of the ZU5EV chip, there are 4 DDR4 and 1 DDR4 respectively, each with
a capacity of up to 1GB, which enables the ARM system and FPGA system to
independently process and store data. The 8GB eMMC FLASH memory chip
and a 256Mb QSPI FLASH which are on the PS side, used to statically store
the operating system, file system and user data of MPSoCs.
The AXU5EV-E carrier board expands its rich peripheral interface,
including 1 SATA M.2 interface, 1 DP interface, 4 USB 3.0 Interface, 2 Gigabit
Ethernet interfaces, 1 SD card slot, 2-Channel 40-pin expansion header,
2-Channel CAN bus interfaces, 2-Channel RS485 bus interfaces, 1 MIPI
Camera Interface and some keys and LEDs.
The following figure shows the structure of the entire development system:

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Figure 1-1-1: The Schematic Diagram of the AXU5EV-E
Through this diagram, you can see the interfaces and functions that the
AXU5EV-E FPGA Development Board contains:
ACU5EV core board
It consists of ZU5EV +4GB DDR4（PS）+1GB DDR4（PL）+8GB eMMC
FLASH + 256Mb QSPI FLASH, and there are 2 crystal oscillators to
provide the clock, a single-ended 33.3333MHz crystal oscillator for the
PS system, and a differential 200MHz crystal oscillator for the PL logic
DDR reference clock.
M.2 Interface
1 PCIEx1 standard M.2 interface, used to connect M.2 SSD solid state
drives, with a communication speed of up to 6Gbps.
DP Output Interface
1 standard Display Port output display interface, used for video image
display. Supports up to 4K@30Hz or 1080P@60Hz output

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USB 3.0 Interface
4-channel USB3.0 HOST interface, USB interface type is TYPE A. Used
to connect external USB peripherals, such as connecting a mouse,
keyboard, U disk, etc.
Gigabit Ethernet Interface
2-Channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses Micrel's KSZ9031 industrial grade GPHY chip.
USB Uart Interface
2-Channel Uart to USB interfaces for communication with the computer,
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon Labs CP2102GM, and the USB interface adopts the MINI USB
interface.
SD Card Slot Interface
1 Micro SD card holder, used to store operating system image and file
system.
40-pin expansion port
2 40-pin 0.1-inch pitch expansion port can be connected to various
ALINX modules (binocular camera, TFT LCD screen, high-speed AD
module, etc.). The expansion port contains 1-channel 5V power supply,
2-channel 3.3V power supply, 3-channel way ground, 34 IOs port.
CAN Communication Interface
Two-way CAN bus interface, using TI's SN65HVD232 chip, the
interface uses 4Pin green terminal blocks.
485 Communication Interface
Two-way 485 communication interface, using MAX3485 chip of MAXIM
company. The interface uses 6Pin green terminal blocks.
MIPI Interface
MIPI camera input interfaces, used to connect MIPI camera module

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(AN5641).
JTAG debug port
A 10-pin 0.1 spacing standard JTAG ports for FPGA program download
and debugging. Users can debug and download the ZU5EV system
through the XILINX downloader.
Temperature and humidity sensor chip LM75
On-board temperature and humidity sensor chip LM75, used to detect
the temperature and humidity of the surrounding environment around
the FPGA development board
EEPROM
One EEPROM 24LC04 with I2C interface
Real Time Clock (RTC)
1 built-in RTC real-time clock
LED Lights
5 LEDs, include 2 LEDs on the core board, 3 LED on the carrier board.
There are 1 power indicator and 1 DONE Configuration indicator on the
core board, 1 power indicator on the carrier board. There are 1 power
indicator and 2 user indicators on the carrier board.
KEYs
3 KEYs, include 1 Rest KEY and 2 User KEYs.

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Part 2: ACU5EV Core Board
Part 2.1: ACU5EV Core Board Introduction
ACU5EV (core board model, the same below) FPGA core board, ZYNQ
chip is based on XCZU5EV-2SFVC784I of XILINX company Zynq UltraScale+
MPSoCs EV Family.
This core board uses 5 Micron DDR4 chips MT40A512M16GE, of which 4
DDR4 chips are mounted on the PS side to form a 64-bit data bus bandwidth
and 4GB capacity. One DDR4 chip is mounted on the PL end, which is a 16-bit
data bus width and a capacity of 1GB. The highest operating speed of DDR4
SDRAM on the PS side can reach 1200MHz (data rate 2400Mbps), and the
highest operating speed of DDR4 SDRAM on the PL side can reach 1066MHz
(data rate 2132Mbps). In addition, a 256MBit QSPI FLASH and an 8GB eMMC
FLASH chip are also integrated on the core board to start storage configuration
and system files.
In order to connect with the carrier board, the four board-to-board
connectors of this core board expand the PS side USB2.0 interface, Gigabit
Ethernet interface, SD card interface and other remaining MIO ports; also
expand 4 pairs of PS MGT high-speed transceiver interface; and almost all IO
ports on the PL side (HP I/O: 96, HD I/O: 84). The wiring between the
XCZU5EV chip and the interface has been processed with equal length and
differential, and the core board size is only 3.15*2.36 (inch), which is very
suitable for secondary development.