Alinx AX7035 User manual

ARTIX-7 FPGA
Development Board
AX7035
User Manual

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Version Record
Version
Date
Release By
Description
Rev 1.0
2019-04-26
Rachel Zhou
First Release
The English version was translated by Shanghai Tianhui Trading
Company. They has not been officially Review by ALINX and are for reference
only. If there are any errors, please send email to [e-mail]
for correction.
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Customer Service Information
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Technical Email:supp[email protected]om
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Table of Contents
Version Record .............................................................................................2
Part 1: FPGA Development Board Introduction .......................................... 5
Part 2: Structure Diagram ............................................................................8
Part 3: Power Supply ................................................................................... 9
Part 4: FPGA Chip ..................................................................................... 10
Part 5: 50M active crystal oscillator ........................................................... 11
Part 6:DDR3 DRAM ...................................................................................12
Part 7: QSPI Flash .....................................................................................15
Part 8: Gigabit Ethernet Interface ..............................................................17
Part 9: HDMI1 Output interface ................................................................. 19
Part 10: HDMI1 input interface (also used as an output) ..........................22
Part 11: USB 2.0 Communication Interface .............................................. 25
Part 12: SD Card Slot ................................................................................ 26
Part 13: USB to Serial Port ........................................................................28
Part 14: EEPROM 24LC04 ........................................................................29
Part 15: Digital Tube .................................................................................. 30
Part 16: Temperature Sensor .................................................................... 33
Part 17: Expansion Header ....................................................................... 34
Part 18: FPC Expansion Ports ...................................................................37
Part 19: JTAG Interface ............................................................................. 39
Part 20: User Keys .....................................................................................40
Part 21: LED Light ......................................................................................42

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The AX7035 FPGA development board, it is the ARTIX-7 FPGA
development platform.
The ARTIX-7 FPGA development platform uses XILINX's ARTIX-7 chip,
and theAX7035 FPGA development board are designed with a rich peripheral
interface. For example, one HDMI input interface, one HDMI output interface,
one Gigabit Ethernet interface, one USB2.0 interface, Uart interface,
downloader interface and two 40-pin expansion ports, and so on.It meets
user's requirements for high-speed data transmission, video processing and
industrial control. It is a "Versatile" ARTIX-7 FPGA development platform. It
provides the possibility for pre-verification and post-application of high-speed
video transmission, data communication, image processing and data
processing. This product is very suitable for students, engineers and other
groups engaged in FPGA development.

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Part 1: FPGA Development Board Introduction
The AX7035 FPGA development board uses Xilinx's ARTIX-7 series of
FPGA chipsXC7A35T-2FGG484I, 484-pin FBGA package. The FPGA chip is
connected with a 256M byte DDR3 memory chip to achieve high-speed data
reading and writing between FPGA and DDR3. The data bit width is 16 bits, the
DDR read/write clock frequency reaches 400Mhz, and the bandwidth of the
whole system is up to 12.8Gb/s. (800M*16bit), which satisfies the data buffer
requirement during data processing. A 128Mbit QSPI FLASH is used as an
FPGA configuration chip to store FPGA configuration files and some user data.
The AX7035 FPGA development board has expanded a wide range of
peripheral interfaces, including one HDMI output interface, one HDMI input
interface, one Gigabit Ethernet interface, one USB2.0 interface, one UART
serial interface, one SD card interface, two 40-pin Expansion port, keys, LEDs,
EEPROM and sensor circuits.

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Figure 1-1: TheSchematic Diagram of the AX7035
Through this diagram, you can see the interfaces and functions that the
AX7035FPGA Development Board contains:
Xilinx ARTIX-7 Series FPGA Chip XC7A35T-2FGG484I
A large-capacity 2Gbit (256MB) high-speed DDR3 SDRAM can be used
as a buffer for FPGA chip data
A 50Mhz active crystal onboard provides a stable clock source for the
FPGA system
1-channelGigabit Ethernet InterfaceRJ-45 interface
The Gigabit Ethernet interface chip uses Micrel's KSZ9031RNX
Ethernet PHY chip to provide network communication services to users.
KSZ9031RNX chip supports 10/100/1000 Mbps network transmission
rate; full duplex and adaptive
1-channel HDMI image video output interface

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Supports up to 1080P@60Hz output and supports data output in
different formats
1-channel HDMI image video input interface
Supports up to 720P@60Hz input and supports data input in different
formats
1-channel high speed USB2.0 interface
Using FT232H single-channel USB chip of FTDI, it can be used for
USB2.0 high-speed communication between development board and
PC, with a maximum speed of 480Mb/s.
1-channel USB Uart interface
1-channel Uart to USB interface for communication with the computer
for user debugging. The serial port chip adopts the USB-UAR chip of
Silicon LabsCP2102GM, and the USB interface adopts the MINI USB
interface.
Micro SD slot
1-channel Micro SDslot, supports SD mode and SPI mode.
A 6-digit digital tube that dynamically displays 6 digits.
Temperature and humidity sensor
Onboard a temperature and humidity sensor chip LM75 for detecting
the temperature and humidity of the environment around the board
2-channel40-pin expansion port
Reserve 2 40-pin 2.54mm pitch expansion ports, which can be
connected to various ALINX modules (binocular camera, TFT LCD
screen, high-speed AD module, etc.). The expansion port contains 1
channel 5V power supply, 2 channel 3.3V power supply, 3 way ground,
34 IOs port.
1-channel FPC expansion port
A 15-pin FPC expansion port is reserved for connecting the user's MIPI
camera module.

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JTAG Interface
A 10-pin0.1 spacing standard JTAG ports for FPGA program download
and debugging.
Key
1 reset key, 4 user keys
LED Light
6LEDs, 1 power indicator, 1 DONE configuration indicator, 2 serial
transmit and receive indicators, 4 user LEDs.
Part 2: Structure Diagram
The size of the development board is a compact 130mm x 90mm, and the
PCB is designed with an 8-layer board. There are 4 screw positioning holes
around the FPGA board for fixing the development board. The hole diameter of
the positioning hole is 3.5mm (diameter)
Figure 2-1: Structure Diagram

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Part 3: Power Supply
The power supply voltage of the AX7035 FPGA development board is
DC5V, and Figure 3-1 is the power supply schematic:
Figure 3-1: Power Supply Schematic
The development board is powered by +5V and converted to +3.3V, +1.5V,
+1.8V, +1.0V four-way power supply through four DC/DC power supply chip
TLV62130RGT. The output current can be up to 3A per channel. VCCIO is
generated by one LDOSPX3819M5-3-3. VCCIO mainly supplies power to
BANK16 of FPGA. Users can change the IO of BANK16 to different voltage
standards by replacing their LDO chip. 1.5V generates the VTT and VREF
voltages required by DDR3 via TI's TPS51200.In addition, 1.5V generates 1.2V
to power the network interface chip through an LDO chip TPS74701. The
functions of each power distribution are shown in the following table:

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Power Supply
Function
+1.0V
FPGACore VoltageVCCINT, VCCBRAM
+1.8V
FPGA auxiliary voltageVCCAUX, VCCBATT,ADC power supply VCCADC
+3.3V
VCCIO ofFPGA, Ethernet, Serial port, HDMI, Sensor, FLASH, EEPROM,
and SD Card
+1.5V
DDR3, Bank34 of FPGA
VREF,VTT
DDR3
VCCIO
FPGA Bank16
Because the power supply of Artix-7 FPGA has the power-on sequence
requirement, in the circuit design, we have designed according to the power
requirements of the chip, and the power-on is 1.0V->1.8V->1.5
V->3.3V->VCCIO.
Part 4: FPGA Chip
As mentioned above, the FPGA model we use is XC7A35T-2FGG484I,
which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the
temperature grade is industry grade. This model is a FGG484 package with
484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below
Figure 4-1: The Specific Chip Model Definition of ARTIX-7 Series
Figure 4-2: FPGA chip on board

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The main parameters of the FPGA chip XC7A35T are as follows
Name
Specific parameters
Logic Cells
33,280
Slices
5,200
CLB flip-flops
41,600
Block RAM（kb）
1,800
DSP Slices
90
Speed Grade
-2
Temperature Grade
Industrial
FPGA power supply system
Artix-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX,VCCO, VMGTAVCC and
VMGTAVTT. VCCINT is the FPGA core power supply pin, which needs to be connected
to 1.0V; VCCBRAM is the power supply pin of FPGA block RAM, connect to 1.0V;
VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of
each BANK of FPGA, including BANK0, BANK14~16, BANK34~35. On
AX7035 FPGA development board, BANK34 need to be connected to DDR3,
the voltage connection of BANK is 1.5V, and the voltage of other BANK is 3.3V.
The VCCO of BANK16 is powered by the LDO, and can be changed by replacing
the LDO chip. Because the GTP transceiver function is not used here, the
development board does not provide GTP power.
The Artix-7 FPGA system requires that the power-up sequence be
powered by VCCINT, then VCCBRAM, then VCCAUX and finally VCCO. If VCCINT and VCCBRAM
have the same voltage, they can be powered up at the same time. The order of
power outages is reversed.
Part 5: 50M active crystal oscillator
The Sitime 50M active crystal is provided on the development board to the
FPGA as the system clock input. The crystal output is connected to the FPGA's
global clock (GCLK Pin Y18). This GCLK can be used to drive the user logic

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within the FPGA. The user can configure the FPGA's internal PLL and MMCM
to achieve a higher clock.
Figure 5-1: 50M active crystal oscillator
Figure 5-2: 50M active crystal oscillator on the FPGA Board
Clock Pin Assignment
Net Name
FPGA PIN
FPGA_GCLK1
V10
Part 6:DDR3 DRAM
TheAX7035 FPGA development board is equipped with one Micron 2Gbit
(256MB) DDR3 chips, model MT41J128M16HA-125. DDR bus width is 16bit.
The DDR3 SDRAM has a maximum operating speed of 400MHz (data rate
800Mbps). The DDR3 memory system is directly connected to the memory

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interface of the BANK 34 of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 6-1.
Bit Number
Chip Model
Capacity
Factory
U4
MT41J128M16HA-125
128M x 16bit
Micron
Table 6-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 6-1: The DDR3 DRAM Schematic
Figure 6-2: The DDR3 on the FPGA Board

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DDR3 DRAM pin assignment:
Net Name
FPGA PIN Name
FPGA P/N
DDR3_LDQS_P
IO_L9P_T1_DQS_34
Y3
DDR3_LDQS_N
IO_L9N_T1_DQS_34
AA3
DDR3_UDQS_P
IO_L3P_T0_DQS_34
R3
DDR3_UDQS_N
IO_L3N_T0_DQS_34
R2
DDR3_DQ[0]
IO_L12P_T1_MRCC_34
V4
DDR3_DQ [1]
IO_L8N_T1_34
AB2
DDR3_DQ [2]
IO_L8P_T1_34
AB3
DDR3_DQ [3]
IO_L7P_T1_34
AA1
DDR3_DQ [4]
IO_L10P_T1_34
AA5
DDR3_DQ [5]
IO_L11P_T1_SRCC_34
Y4
DDR3_DQ [6]
IO_L10N_T1_34
AB5
DDR3_DQ [7]
IO_L11N_T1_SRCC_34
AA4
DDR3_DQ [8]
IO_L2N_T0_34
V2
DDR3_DQ [9]
IO_L5N_T0_34
Y1
DDR3_DQ [10]
IO_L1N_T0_34
U1
DDR3_DQ [11]
IO_L4N_T0_34
Y2
DDR3_DQ [12]
IO_L1P_T0_34
T1
DDR3_DQ [13]
IO_L5P_T0_34
W1
DDR3_DQ [14]
IO_L2P_T0_34
U2
DDR3_DQ [15]
IO_L6P_T0_34
U3
DDR3_LDM
IO_L7N_T1_34
AB1
DDR3_UDM
IO_L4P_T0_34
W2
DDR3_A[0]
IO_L22P_T3_34
AA8
DDR3_A[1]
O_L14N_T2_SRCC_34
U5
DDR3_A[2]
IO_L24N_T3_34
Y9
DDR3_A[3]
IO_L23P_T3_34
Y8
DDR3_A[4]
IO_L16N_T2_34
V5
DDR3_A[5]
IO_L19N_T3_VREF_34
W7
DDR3_A[6]
IO_L16P_T2_34
U6
DDR3_A[7]
IO_L19P_T3_34
V7
DDR3_A[8]
IO_L14P_T2_SRCC_34
T5
DDR3_A[9]
O_L24P_T3_34
W9
DDR3_A[10]
IO_L18N_T2_34
AA6
DDR3_A[11]
IO_L17N_T2_34
T6

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DDR3_A[12]
IO_L18P_T2_34
Y6
DDR3_A[13]
IO_L17P_T2_34
R6
DDR3_BA[0]
IO_L22N_T3_34
AB8
DDR3_BA[1]
IO_L15N_T2_DQS_34
W5
DDR3_BA[2]
IO_L23N_T3_34
Y7
DDR3_S0
IO_25_34
U7
DDR3_RAS
IO_L20P_T3_34
AB7
DDR3_CAS
IO_L13N_T2_MRCC_34
T4
DDR3_WE
IO_L15P_T2_DQS_34
W6
DDR3_ODT
IO_L20N_T3_34
AB6
DDR3_RESET
IO_0_34
T3
DDR3_CLK_P
IO_L21P_T3_DQS_34
V9
DDR3_CLK_N
IO_L21N_T3_DQS_34
V8
DDR3_CKE
IO_L13P_T2_MRCC_34
R4
Part 7: QSPI Flash
The AX7035 FPGA development board is equipped with one128MBit
QSPI FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, core application
code and other user data files. The specific models and related parameters of
QSPI FLASH are shown in Table 7-1.
Position
Model
Capacity
Factory
U8
N25Q128
128M Bit
Numonyx
Table 7-1: QSPI FLASH Specification
QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of
the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data
and chip select signals are connected to D00~D03 and FCS pins of BANK14
respectively. Figure 7-1 shows the hardware connection of QSPI Flash.

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Figure 7-1: QSPI Flash Schematic
QSPI Flash pin assignments:
Net Name
FPGA PIN Name
FPGA P/N
QSPI_CLK
CCLK_0
L12
QSPI_CS
IO_L6P_T0_FCS_B_14
T19
QSPI_DQ0
IO_L1P_T0_D00_MOSI_14
P22
QSPI_DQ1
IO_L1N_T0_D01_DIN_14
R22
QSPI_DQ2
IO_L2P_T0_D02_14
P21
QSPI_DQ3
IO_L2N_T0_D03_14
R21
Figure 7-2: QSPI on the FPGA Board

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Part 8: Gigabit Ethernet Interface
The AX7035 development board provides network communication
services to users through a Micrel KSZ9031RNX Ethernet PHY chip. The
Ethernet PHY chip is connected to the IO interface of the ARTIX7 FPGA. The
KSZ9031RNX chip supports 10/100/1000 Mbps network transmission rate and
communicates with the FPGA through the RGMII interface. KSZ9031RNX
supports MDI/MDX adaptation, various speed adaptation, Master/Slave
adaptation, supports MDIO bus for PHY register management.
TheKSZ9031RNXwill detect the level status of some specific IOs to
determine their working mode after powered on. Table 8-1 describes the default
setup information after the GPHY chip is powered on.
Configuration Pin
Instructions
Configuration value
PHYAD[2:0]
MDIO/MDC Mode PHY Address
PHY Address011
CLK125_EN
Enable 125Mhz clock output
selection
Enable
LED_MODE
LED light mode configuration
Single LED light mode
MODE0~MODE
Link adaptation and full duplex
configuration
10/100/1000 adaptive, compatible
with full-duplex, half-duplex
Table 8-1: PHY chip default configuration value
When the network is connected to Gigabit Ethernet, the data transmission
of FPGA and PHY chip KSZ9031RNXis communicated through the RGMII bus,
the transmission clock is 125Mhz, and the data is sampled on the rising and
falling of the clock.
When the network is connected to 100M Ethernet, the data transmission of
FPGA and PHY chip KSZ9031RNXis communicated through the RMII bus, the
transmission clock is 25Mhz,and the data is sampled on the rising and falling of
the clock.

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Figure 8-1: Gigabit Ethernet Interface Schematic
Figure 8-2: Gigabit Ethernet interface on the board
Ethernet chip pin assignments are as follows：
Signal Name
FPGA Pin
Description
E1_GTXC
L14
RGMII transmit clock
E1_TXD0
J21
Transmit Data bit0
E1_TXD1
M20
Transmit Data bit1
E1_TXD2
L18
Transmit Data bit2

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E1_TXD3
L20
Transmit Data bit3
E1_TXEN
L19
Transmit enable signal
E1_RXC
K18
RGMII receive clock
E1_RXD0
K19
Receive Data Bit0
E1_RXD1
M15
Receive Data Bit1
E1_RXD2
J17
Receive Data Bit2
E1_RXD3
J20
Receive Data Bit3
E1_RXDV
M21
Receive data valid signal
E1_MDC
K17
MDIO Management Clock
E1_MDIO
K16
MDIO Management Data
E1_RESET
L15
PHY Reset Signal
Part 9: HDMI1 Output interface
The implementation of the HDMI output interface on the AX7035
development board is to directly connect the differential signal and clock of the
HDMI interface through the differential IO of the FPGA, realize the differential
output of the HMDI signal after the data is encoded and parallel-to-differentially
converted in the FPGA, and realize the HDMI digital video. The output
transmission solution supports up to 1080P@60Hz output.
The differential drive signal of HDMI passes through the IO output of FPGA
BANK35, and the ESD protection device is added to the signal interface. In
addition, the HPD (hot plug detect) signal is used to detect whether the external
HDMI display device is inserted. Figure 9-1 is detailed the HDMI output
Interface schematic

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Figure 9-1: HDMI Output Interface Schematic
When the development board is used as an output device for HDMI display,
it needs to provide a +5V power supply to the HDMI display device. When the
HDMI1_OUT_EN signal is high, it outputs +5V power to the external HDMI
device. The power output control circuit is shown in Figure 9-2.
Figure 9-2: HDMI +5V Output Schematic
In addition, the HMDI master device reads the EDID device information of
the HDMI display device through the IIC bus. The pin level of the FPGA is 3.3V,
but the level of HDMI is +5V. Here, the level conversion chip GTL2002D is
required to connect. The conversion circuit of IIC is shown in Figure 9-3