Alinx AXKU041 User manual

KINTEX UltraScale
development Board
User Manual
AXKU041

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Version Record
Version
Date
REV1.0
2020-2-1

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Table of Contents
Part 1 FPGA Development Board Introduction 4
Part 2 FPGA Chip 8
Part 3 FPGA power supply system 9
Part4 DDR4 DRAM
10
Prat 5 QSPI Flash 15
Part6 Clock configuration 17
Part 7 USB to Serial Port 20
Part 8 SFP+Fiber Interface 21
Part 9 Ethernet interface 23
Part 10 PCIE X8 Interface 25
Part 11 FMC connector 27
Part 11 SD Card Slot 46
Part 12 SMA、SATA Interface 47
Part 13 temperature sensor 48
Part 14 JTAG 49
Part 15 LED 50
Part 16 Buttons 52
Part 17 Power Supply 53
Part 18 FAN 55
Part 19 Structural dimension drawing 56

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Part 1 FPGA Development Board Introduction
AXKU041 is a development board based on XILINX development platform
KINTEX UltraSacale architecture provided by Xinye Electronic Technology (Shanghai)
Co., LTD. It can meet users' requirements of various high-speed data exchange, data
storage, video transmission processing and industrial control. It is a "professional-
grade" FPGA development platform. It is possible for high speed data transmission
and exchange, early validation and late application of data processing. I believe that
such a product is very suitable for students and engineers engaged in FPGA
development. To give you a quick overview of this development platform, we have
written this user manual.
The AXKU041 development board is mounted with four 1GB high-speed DDR4
SDRAM chips, and the FPGA chip configuration uses two 256Mb QSPI NOR FLASH
chips.
In terms of peripheral circuit, we have extended a variety of interfaces for users: 2
10G SFP+ optical fiber interfaces, 3 FMC expansion interfaces, 1 UART serial

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interface, 1 SD card interface, 1 road network interface, SMA and so on.
The diagram below is the schematic diagram of the whole development system：
Through this diagram, we can see the interfaces and functions that our
development platform can contain
Xilinx KINTEX UltraSacale chip XCKU040
DDR4
It comes with four high-speed DDR4 SDRAM with a large capacity of 1 gigabyte
(4GB). Can be used as FPGA data storage, image analysis cache, data processing.
QSPI FLASH
Two 256Mbit QSPI NOR FLASH memory chips, which can be used to store FPGA
chip configuration files and user data;
2 SFP+Fiber Interface

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The two-channel high-speed transceiver of THE GTH transceiver of FPGA is
connected to the transmitting and receiving of two optical modules to realize the
two-channel high-speed optical communication interface. Each channel of optical
fiber data communication receives and sends up to 16.3Gb/s
USB Uart interface
1 Uart to USB interface, used for communication with computer, convenient user
debugging. Serial port chip adopts USB-UAR chip of Silicon Labs CP2102GM, USB
interface adopts MINI USB interface.
Ethernet interface
One 10/100m /1000M Ethernet RJ45 port, used for Ethernet data exchange with
computers or other network devices. The network interface chip adopts Micrel
KSZ9031 industrial grade GPHY chip.
FMC Interface
Three standard FMC expansions, including two LPC expansions and one HPC
expansions. XILINX or our black gold can be connected to various FMC modules
(HDMI input/output module, binocular camera module, high-speed AD module and
so on.
Micro SD
1 Micro SD card holder, used for FPGA to read and write SD card data and
storage
SMA
2 channels SMA external interface, pin connection common clock signal, used
for external input and output signals.
Temperature and humidity sensor EEPROM
The onboard TEMPERATURE and humidity sensor chip LM75 is used to detect
the ambient temperature and humidity of the board.
An ONBOARD EEPROM is used to communicate with IIC bus and store some
customized information.
JTAG
A 10-pin 2.54mm standard JTAG port is used for downloading and debugging of
FPGA programs. Users can debug and download FPGA through XILINX downloader.
CLK
A 200Mhz differential crystal oscillator provides a stable clock source for FPGA

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system；
A 156.25mhz differential crystal oscillator is onboard to provide a reference
clock for the optical fiber.
Onboard is a 156.25mhz differential crystal oscillator that gives the transceiver a
reference clock.
LED Light
6 leds, 1 power indicator; 1 DONE configuration indicator; 4 user indicators and
a pair of panel indicators.
Button
2 user buttons, 1 reset button, and 1 normal IO connected to FPGA

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Part 2 FPGA Chip
The development board uses Xilinx's KINTEX UltraSacale chip, model XCKU040-
2FFVA1156I. The speed grade is 2 and the temperature grade is industrial grade.
This model is FFVA1156 package, 1156 pins, pin spacing 1.0mm. Figure 2-1 shows
the chip naming rules of Xilinx KINTEX UltraSacale：
Figure 2-1 KINTEX UltraSacale FPGA
The main parameters of XCKU040 are as follows：
Name
Specific parameters
Logic Cells
530,250
CLB LUTs
242,400
CLB flip-flops
484,800
Block RAM（Mb）
21.1
DSP Slices
1,920
PCIe Gen3 x8
3
GTH Transceiver
20 个，16.3Gb/s max
Speed Grade
-2
Temperature Grade
Industrial

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Part 3 FPGA power supply system
XCKU040 FPGA power supply has VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO VCCO,
VMGTAVCC,VMGTAVTT, VMGTVCCAUX, VMGTAVTTRCAL, VCCADC。VCCINT is the
FPGA core power supply pin, which needs to be connected to 0.95V；VCCBRAM is
the power supply pin of FPGA Block RAM, connect to 0.95V；VCCAUX&VCCAUX_IO
is FPGA auxiliary power supply pin, connect 1.8V；VCCO is the voltage of each BANK
of FPGA, including BANK0,BANK44~48, BANK64~68. VMGTAVCC For the supply voltage
of GTH and GTY transceiver in FPGA, connect1.0V；VMGTAVTT Is the terminal voltage
of GTH sending and receiving, connected to 1.2V. VMGTAVTTRCAL Calibrate voltage for
transceiver resistor, connected to 1.2V；VCCADC Supply voltage for XADC, 1.8V。
Figure 2-2 shows the sequence for powering on the XCKU040 FPGA system
Figure 2-2

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Part4 DDR4 DRAM
The AXKU040 development board is equipped with four Micron 1GB DDR4 chips,
model mt40A512M16LY-062EIT. Four DDR4 SDRAM chips form a 64-bit bus width.
Because the four DDR4 chips are connected to the FPGA, DDR4 SDRAM has a
maximum operating clock of 1200Mhz, and the four DDR4 storage systems are
directly connected to the BANK44, BANK45, and BANK46 interfaces of the FPGA. The
following table describes the configuration of DDR4 SDRAM 3-1.
Table 3-1 DDR4 SDRAM configuration
Bit Number
Chip Model
Capacity
Factory
U45,U47,U48,U49
MT40A512M16LY-
062EIT
512M x 16bit
Micron
DDR4 hardware design requires strict consideration of signal integrity, we have
fully considered the circuit design and PCB design of the matching
resistance/terminal resistance, wiring impedance control, line length control, to
ensure the high-speed and stable operation of DDR4
Figure 3-1 shows the hardware connections of FPGA and DDR4 DRAM:

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Figure 3-1 DDR4 DRAM
4 DDR4 DRAM pins allocated：
Signal Name
FPGA Pin Name
FPGA Pin
PL_DDR4_DQ0
IO_L3N_T0L_N5_AD15N_44
AE20
PL_DDR4_DQ1
IO_L2N_T0L_N3_44
AG20
PL_DDR4_DQ2
IO_L2P_T0L_N2_44
AF20
PL_DDR4_DQ3
IO_L5P_T0U_N8_AD14P_44
AE22
PL_DDR4_DQ4
IO_L3P_T0L_N4_AD15P_44
AD20
PL_DDR4_DQ5
IO_L6N_T0U_N11_AD6N_44
AG22
PL_DDR4_DQ6
IO_L6P_T0U_N10_AD6P_44
AF22
PL_DDR4_DQ7
IO_L5N_T0U_N9_AD14N_44
AE23
PL_DDR4_DQ8
IO_L8N_T1L_N3_AD5N_44
AF24
PL_DDR4_DQ9
IO_L11P_T1U_N8_GC_44
AJ23
PL_DDR4_DQ10
IO_L8P_T1L_N2_AD5P_44
AF23
PL_DDR4_DQ11
IO_L12N_T1U_N11_GC_44
AH23
PL_DDR4_DQ12
IO_L9N_T1L_N5_AD12N_44
AG25
PL_DDR4_DQ13
IO_L11N_T1U_N9_GC_44
AJ24
PL_DDR4_DQ14
IO_L9P_T1L_N4_AD12P_44
AG24
PL_DDR4_DQ15
IO_L12P_T1U_N10_GC_44
AH22

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PL_DDR4_DQ16
IO_L14P_T2L_N2_GC_44
AK22
PL_DDR4_DQ17
IO_L17P_T2U_N8_AD10P_44
AL22
PL_DDR4_DQ18
IO_L15N_T2L_N5_AD11N_44
AM20
PL_DDR4_DQ19
IO_L17N_T2U_N9_AD10N_44
AL23
PL_DDR4_DQ20
IO_L14N_T2L_N3_GC_44
AK23
PL_DDR4_DQ21
IO_L18N_T2U_N11_AD2N_44
AL25
PL_DDR4_DQ22
IO_L15P_T2L_N4_AD11P_44
AL20
PL_DDR4_DQ23
IO_L18P_T2U_N10_AD2P_44
AL24
PL_DDR4_DQ24
IO_L20P_T3L_N2_AD1P_44
AM22
PL_DDR4_DQ25
IO_L23P_T3U_N8_44
AP24
PL_DDR4_DQ26
IO_L20N_T3L_N3_AD1N_44
AN22
PL_DDR4_DQ27
IO_L21N_T3L_N5_AD8N_44
AN24
PL_DDR4_DQ28
IO_L24P_T3U_N10_44
AN23
PL_DDR4_DQ29
IO_L23N_T3U_N9_44
AP25
PL_DDR4_DQ30
IO_L24N_T3U_N11_44
AP23
PL_DDR4_DQ31
IO_L21P_T3L_N4_AD8P_44
AM24
PL_DDR4_DQ32
IO_L2P_T0L_N2_46
AM26
PL_DDR4_DQ33
IO_L6P_T0U_N10_AD6P_46
AJ28
PL_DDR4_DQ34
IO_L2N_T0L_N3_46
AM27
PL_DDR4_DQ35
IO_L6N_T0U_N11_AD6N_46
AK28
PL_DDR4_DQ36
IO_L5P_T0U_N8_AD14P_46
AH27
PL_DDR4_DQ37
IO_L5N_T0U_N9_AD14N_46
AH28
PL_DDR4_DQ38
IO_L3P_T0L_N4_AD15P_46
AK26
PL_DDR4_DQ39
IO_L3N_T0L_N5_AD15N_46
AK27
PL_DDR4_DQ40
IO_L9N_T1L_N5_AD12N_46
AN28
PL_DDR4_DQ41
IO_L12N_T1U_N11_GC_46
AM30
PL_DDR4_DQ42
IO_L8P_T1L_N2_AD5P_46
AP28
PL_DDR4_DQ43
IO_L11N_T1U_N9_GC_46
AM29
PL_DDR4_DQ44
IO_L9P_T1L_N4_AD12P_46
AN27
PL_DDR4_DQ45
IO_L12P_T1U_N10_GC_46
AL30
PL_DDR4_DQ46
IO_L11P_T1U_N8_GC_46
AL29
PL_DDR4_DQ47
IO_L8N_T1L_N3_AD5N_46
AP29
PL_DDR4_DQ48
IO_L14P_T2L_N2_GC_46
AK31
PL_DDR4_DQ49
IO_L18P_T2U_N10_AD2P_46
AH34
PL_DDR4_DQ50
IO_L14N_T2L_N3_GC_46
AK32

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PL_DDR4_DQ51
IO_L15N_T2L_N5_AD11N_46
AJ31
PL_DDR4_DQ52
IO_L15P_T2L_N4_AD11P_46
AJ30
PL_DDR4_DQ53
IO_L17P_T2U_N8_AD10P_46
AH31
PL_DDR4_DQ54
IO_L18N_T2U_N11_AD2N_46
AJ34
PL_DDR4_DQ55
IO_L17N_T2U_N9_AD10N_46
AH32
PL_DDR4_DQ56
IO_L21P_T3L_N4_AD8P_46
AN31
PL_DDR4_DQ57
IO_L24P_T3U_N10_46
AL34
PL_DDR4_DQ58
IO_L23N_T3U_N9_46
AN32
PL_DDR4_DQ59
IO_L20P_T3L_N2_AD1P_46
AN33
PL_DDR4_DQ60
IO_L23P_T3U_N8_46
AM32
PL_DDR4_DQ61
IO_L24N_T3U_N11_46
AM34
PL_DDR4_DQ62
IO_L21N_T3L_N5_AD8N_46
AP31
PL_DDR4_DQ63
IO_L20N_T3L_N3_AD1N_46
AP33
PL_DDR4_DM0
IO_L1P_T0L_N0_DBC_44
AD21
PL_DDR4_DM1
IO_L7P_T1L_N0_QBC_AD13P_44
AE25
PL_DDR4_DM2
IO_L13P_T2L_N0_GC_QBC_44
AJ21
PL_DDR4_DM3
IO_L19P_T3L_N0_DBC_AD9P_44
AM21
PL_DDR4_DM4
IO_L1P_T0L_N0_DBC_46
AH26
PL_DDR4_DM5
IO_L7P_T1L_N0_QBC_AD13P_46
AN26
PL_DDR4_DM6
IO_L13P_T2L_N0_GC_QBC_46
AJ29
PL_DDR4_DM7
IO_L19P_T3L_N0_DBC_AD9P_46
AL32
PL_DDR4_DQS0_P
IO_L4P_T0U_N6_DBC_AD7P_44
AG21
PL_DDR4_DQS0_N
IO_L4N_T0U_N7_DBC_AD7N_44
AH21
PL_DDR4_DQS1_P
IO_L10P_T1U_N6_QBC_AD4P_44
AH24
PL_DDR4_DQS1_N
IO_L10N_T1U_N7_QBC_AD4N_44
AJ25
PL_DDR4_DQS2_P
IO_L16P_T2U_N6_QBC_AD3P_44
AJ20
PL_DDR4_DQS2_N
IO_L16N_T2U_N7_QBC_AD3N_44
AK20
PL_DDR4_DQS3_P
IO_L22P_T3U_N6_DBC_AD0P_44
AP20
PL_DDR4_DQS3_N
IO_L22N_T3U_N7_DBC_AD0N_44
AP21
PL_DDR4_DQS4_P
IO_L4P_T0U_N6_DBC_AD7P_46
AL27
PL_DDR4_DQS4_N
IO_L4N_T0U_N7_DBC_AD7N_46
AL28
PL_DDR4_DQS5_P
IO_L10P_T1U_N6_QBC_AD4P_46
AN29
PL_DDR4_DQS5_N
IO_L10N_T1U_N7_QBC_AD4N_46
AP30
PL_DDR4_DQS6_P
IO_L16P_T2U_N6_QBC_AD3P_46
AH33
PL_DDR4_DQS6_N
IO_L16N_T2U_N7_QBC_AD3N_46
AJ33

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PL_DDR4_DQS7_P
IO_L22P_T3U_N6_DBC_AD0P_46
AN34
PL_DDR4_DQS7_N
IO_L22N_T3U_N7_DBC_AD0N_46
AP34
PL_DDR4_A0
IO_L18N_T2U_N11_AD2N_45
AG14
PL_DDR4_A1
IO_L23N_T3U_N9_45
AF17
PL_DDR4_A2
IO_L20P_T3L_N2_AD1P_45
AF15
PL_DDR4_A3
IO_L16N_T2U_N7_QBC_AD3N_45
AJ14
PL_DDR4_A4
IO_L19N_T3L_N1_DBC_AD9N_45
AD18
PL_DDR4_A5
IO_L15P_T2L_N4_AD11P_45
AG17
PL_DDR4_A6
IO_L23P_T3U_N8_45
AE17
PL_DDR4_A7
IO_L11N_T1U_N9_GC_45
AK18
PL_DDR4_A8
IO_L24P_T3U_N10_45
AD16
PL_DDR4_A9
IO_L13P_T2L_N0_GC_QBC_45
AH18
PL_DDR4_A10
IO_L19P_T3L_N0_DBC_AD9P_45
AD19
PL_DDR4_A11
IO_L24N_T3U_N11_45
AD15
PL_DDR4_A12
IO_L14P_T2L_N2_GC_45
AH16
PL_DDR4_A13
IO_L10N_T1U_N7_QBC_AD4N_45
AL17
PL_DDR4_BA0
IO_L18P_T2U_N10_AD2P_45
AG15
PL_DDR4_BA1
IO_L10P_T1U_N6_QBC_AD4P_45
AL18
PL_DDR4_BG0
IO_L16P_T2U_N6_QBC_AD3P_45
AJ15
PL_DDR4_WE_B
IO_L9N_T1L_N5_AD12N_45
AL15
PL_DDR4_RAS_B
IO_L8N_T1L_N3_AD5N_45
AM19
PL_DDR4_CAS_B
IO_L8P_T1L_N2_AD5P_45
AL19
PL_DDR4_CKE
IO_L14N_T2L_N3_GC_45
AJ16
PL_DDR4_ACT_B
IO_L21N_T3L_N5_AD8N_45
AF18
PL_DDR4_CLK_N
IO_L22N_T3U_N7_DBC_AD0N_45
AE15
PL_DDR4_CLK_P
IO_L22P_T3U_N6_DBC_AD0P_45
AE16
PL_DDR4_CS_B
IO_L21P_T3L_N4_AD8P_45
AE18
PL_DDR4_OTD
IO_L17P_T2U_N8_AD10P_45
AG19
PL_DDR4_PAR
IO_L20N_T3L_N3_AD1N_45
AF14
PL_DDR4_RST
IO_L15N_T2L_N5_AD11N_45
AG16

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Prat 5 QSPI Flash
The development board is equipped with two 256MBit quad-SPI FLASH chips,
model mt25QU256ABa1EW9-0SIT, which uses the 1.8V CMOS voltage standard. Due
to the non-volatile nature of QSPI FLASH, it can store FPGA configuration Bin files
and other user data files in use. Table 4-1 lists the QSPI FLASH models and related
parameters.
Position
Model
Capacity
Factory
U5
MT25QU256ABA1EW9-
0SIT
256Mbit
Micron
U11
MT25QU256ABA1EW9-
0SIT
256Mbit
Micron
Table 4-1 QSPI Flash models and parameters
QSPI FLASH is connected to the pins of BANK0 and BANK65 of FPGA chip,
wherein the clock pin is connected to the CCLK0 of BANK0. Figure 4-2 shows the
connection diagram of QSPI FLASH and FPGA chip.
Figure 4-2 QSPI Flash
Signal Name
FPGA Pin Name
FPGA Pin
Number
QSPI_CCLK
CCLK_0
AA9
QSPI0_CS_B
RDWR_FCS_B_0
U7

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QSPI0_IO0
D00_MOSI_0
AC7
QSPI0_IO1
D01_DIN_0
AB7
QSPI0_IO2
D02_0
AA7
QSPI0_IO3
D03_0
Y7
Signal Name
FPGA Pin Name
FPGA Pin
Number
QSPI1_CS_B
IO_L2N_T0L_N3_FWE_FCS2_B_65
G26
QSPI1_IO0
IO_L22P_T3U_N6_DBC_AD0P_D04_65
M20
QSPI1_IO1
IO_L22N_T3U_N7_DBC_AD0N_D05_65
L20
QSPI1_IO2
IO_L21P_T3L_N4_AD8P_D06_65
R21
QSPI1_IO3
IO_L21N_T3L_N5_AD8N_D07_65
R22

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Part6 Clock configuration
A differential 200MHz clock source is provided on the FPGA development board
to provide the system clock to the FPGA。The crystal oscillator differential output is
connected to FPGA BANK45, which can be used to drive the DDR controller working
clock in FPGA and other user logic circuits
Figuer 5-1
System Clock pin assignments：
Signal Name
FPGA Pin
PL_CLK0_P
AK17
PL_CLK0_N
AK16
156.25mhz differential clock source
A differential 156.25mhz clock source is provided on the board to provide the clock
for the transceiver GTH. The crystal oscillator differential output is connected to
FPGA BANK226, this clock is used for the clock required for 2 channels of optical
fiber. Figure 5-2 shows the working principle of the clock

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source
Figure 5-2
Clock pin assignments：
Signal Name
FPGA Pin
SFP_CLK0_P
V6
SFP_CLK0_N
V5
156.25Mhz Differential clock source
A differential 156.25mhz clock source is provided on the board to provide the
clock for the transceiver GTH. Crystal oscillator differential output connected to
FPGA BANK228. Figure 5-3 shows the working principle of the clock source
Figure 5-3

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Clock pin assignments：
Signal Name
FPGA Pin
HDMI_DRU_CLOCK_P
H6
HDMI_DRU_CLOCK_N
H5

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Part 7 USB to Serial Port
AXKU040 development board is equipped with a Uart to USB interface for
development board serial communication and debugging. The conversion chip is
usB-UAR chip of Silicon Labs CP2102GM, and a level conversion chip is used to
connect CP2102 serial port chip and FPGA to adapt to different FPGA BANK voltages.
USB interface with MINI USB interface, you can use a USB cable to connect it to the
USB port of the PC for serial port data communication of the development board.
The schematic diagram of USB Uart circuit design is shown in Figure 6-1 below:
图 6-1 USB to serial port schematic
USB to serial port pin assignment：
Signal Name
FPGA Name
FPGA pin
Description
UART_RXD
IO_L7N_T1L_N1_QBC_AD13N_48
AG32
Uart Data input
UART_TXD
IO_L7P_T1L_N0_QBC_AD13P_48
AG31
Uart Data output