Alinx AXKU041 User manual

KINTEX UltraScale
development Board
User Manual
AXKU041

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Version Record
Version
Date
REV1.0
2020-2-1

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Table of Contents
Part 1 FPGA Development Board Introduction 4
Part 2 FPGA Chip 8
Part 3 FPGA power supply system 9
Part4 DDR4 DRAM
10
Prat 5 QSPI Flash 15
Part6 Clock configuration 17
Part 7 USB to Serial Port 20
Part 8 SFP+Fiber Interface 21
Part 9 Ethernet interface 23
Part 10 PCIE X8 Interface 25
Part 11 FMC connector 27
Part 11 SD Card Slot 46
Part 12 SMA、SATA Interface 47
Part 13 temperature sensor 48
Part 14 JTAG 49
Part 15 LED 50
Part 16 Buttons 52
Part 17 Power Supply 53
Part 18 FAN 55
Part 19 Structural dimension drawing 56

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Part 1 FPGA Development Board Introduction
AXKU041 is a development board based on XILINX development platform
KINTEX UltraSacale architecture provided by Xinye Electronic Technology (Shanghai)
Co., LTD. It can meet users' requirements of various high-speed data exchange, data
storage, video transmission processing and industrial control. It is a "professional-
grade" FPGA development platform. It is possible for high speed data transmission
and exchange, early validation and late application of data processing. I believe that
such a product is very suitable for students and engineers engaged in FPGA
development. To give you a quick overview of this development platform, we have
written this user manual.
The AXKU041 development board is mounted with four 1GB high-speed DDR4
SDRAM chips, and the FPGA chip configuration uses two 256Mb QSPI NOR FLASH
chips.
In terms of peripheral circuit, we have extended a variety of interfaces for users: 2
10G SFP+ optical fiber interfaces, 3 FMC expansion interfaces, 1 UART serial

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interface, 1 SD card interface, 1 road network interface, SMA and so on.
The diagram below is the schematic diagram of the whole development system：
Through this diagram, we can see the interfaces and functions that our
development platform can contain
Xilinx KINTEX UltraSacale chip XCKU040
DDR4
It comes with four high-speed DDR4 SDRAM with a large capacity of 1 gigabyte
(4GB). Can be used as FPGA data storage, image analysis cache, data processing.
QSPI FLASH
Two 256Mbit QSPI NOR FLASH memory chips, which can be used to store FPGA
chip configuration files and user data;
2 SFP+Fiber Interface

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The two-channel high-speed transceiver of THE GTH transceiver of FPGA is
connected to the transmitting and receiving of two optical modules to realize the
two-channel high-speed optical communication interface. Each channel of optical
fiber data communication receives and sends up to 16.3Gb/s
USB Uart interface
1 Uart to USB interface, used for communication with computer, convenient user
debugging. Serial port chip adopts USB-UAR chip of Silicon Labs CP2102GM, USB
interface adopts MINI USB interface.
Ethernet interface
One 10/100m /1000M Ethernet RJ45 port, used for Ethernet data exchange with
computers or other network devices. The network interface chip adopts Micrel
KSZ9031 industrial grade GPHY chip.
FMC Interface
Three standard FMC expansions, including two LPC expansions and one HPC
expansions. XILINX or our black gold can be connected to various FMC modules
(HDMI input/output module, binocular camera module, high-speed AD module and
so on.
Micro SD
1 Micro SD card holder, used for FPGA to read and write SD card data and
storage
SMA
2 channels SMA external interface, pin connection common clock signal, used
for external input and output signals.
Temperature and humidity sensor EEPROM
The onboard TEMPERATURE and humidity sensor chip LM75 is used to detect
the ambient temperature and humidity of the board.
An ONBOARD EEPROM is used to communicate with IIC bus and store some
customized information.
JTAG
A 10-pin 2.54mm standard JTAG port is used for downloading and debugging of
FPGA programs. Users can debug and download FPGA through XILINX downloader.
CLK
A 200Mhz differential crystal oscillator provides a stable clock source for FPGA

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system；
A 156.25mhz differential crystal oscillator is onboard to provide a reference
clock for the optical fiber.
Onboard is a 156.25mhz differential crystal oscillator that gives the transceiver a
reference clock.
LED Light
6 leds, 1 power indicator; 1 DONE configuration indicator; 4 user indicators and
a pair of panel indicators.
Button
2 user buttons, 1 reset button, and 1 normal IO connected to FPGA

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Part 2 FPGA Chip
The development board uses Xilinx's KINTEX UltraSacale chip, model XCKU040-
2FFVA1156I. The speed grade is 2 and the temperature grade is industrial grade.
This model is FFVA1156 package, 1156 pins, pin spacing 1.0mm. Figure 2-1 shows
the chip naming rules of Xilinx KINTEX UltraSacale：
Figure 2-1 KINTEX UltraSacale FPGA
The main parameters of XCKU040 are as follows：
Name
Specific parameters
Logic Cells
530,250
CLB LUTs
242,400
CLB flip-flops
484,800
Block RAM（Mb）
21.1
DSP Slices
1,920
PCIe Gen3 x8
3
GTH Transceiver
20 个，16.3Gb/s max
Speed Grade
-2
Temperature Grade
Industrial

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Part 3 FPGA power supply system
XCKU040 FPGA power supply has VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO VCCO,
VMGTAVCC,VMGTAVTT, VMGTVCCAUX, VMGTAVTTRCAL, VCCADC。VCCINT is the
FPGA core power supply pin, which needs to be connected to 0.95V；VCCBRAM is
the power supply pin of FPGA Block RAM, connect to 0.95V；VCCAUX&VCCAUX_IO
is FPGA auxiliary power supply pin, connect 1.8V；VCCO is the voltage of each BANK
of FPGA, including BANK0,BANK44~48, BANK64~68. VMGTAVCC For the supply voltage
of GTH and GTY transceiver in FPGA, connect1.0V；VMGTAVTT Is the terminal voltage
of GTH sending and receiving, connected to 1.2V. VMGTAVTTRCAL Calibrate voltage for
transceiver resistor, connected to 1.2V；VCCADC Supply voltage for XADC, 1.8V。
Figure 2-2 shows the sequence for powering on the XCKU040 FPGA system
Figure 2-2

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Part4 DDR4 DRAM
The AXKU040 development board is equipped with four Micron 1GB DDR4 chips,
model mt40A512M16LY-062EIT. Four DDR4 SDRAM chips form a 64-bit bus width.
Because the four DDR4 chips are connected to the FPGA, DDR4 SDRAM has a
maximum operating clock of 1200Mhz, and the four DDR4 storage systems are
directly connected to the BANK44, BANK45, and BANK46 interfaces of the FPGA. The
following table describes the configuration of DDR4 SDRAM 3-1.
Table 3-1 DDR4 SDRAM configuration
Bit Number
Chip Model
Capacity
Factory
U45,U47,U48,U49
MT40A512M16LY-
062EIT
512M x 16bit
Micron
DDR4 hardware design requires strict consideration of signal integrity, we have
fully considered the circuit design and PCB design of the matching
resistance/terminal resistance, wiring impedance control, line length control, to
ensure the high-speed and stable operation of DDR4
Figure 3-1 shows the hardware connections of FPGA and DDR4 DRAM: