ARM ETB11 Product manual

Copyright © 2002, 2003 ARM Limited. All rights reserved.
ARM DDI 0275D
ETB11™
Revision: r0p1
Technical Reference Manual

ii Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
ETB11
Technical Reference Manual
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Release Information
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may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
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such information, or any incorrect use of the product.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
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Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
December 2002 A First release
February 2003 B ETB revision has changed to r0p1
May 2003 C Description of ETMv1/ETMv2 supported removed.
August 2003 D Preface and Index updated and corrected, Resets correctly described 2.10.2,
and 3.2.5 RAM Data Register corrected.

ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. iii
Contents
ETB11 Technical Reference Manual
Preface
About this document ...................................................................................... x
Feedback ..................................................................................................... xiv
Chapter 1 Introduction
1.1 About the Embedded Trace Buffer ............................................................. 1-2
1.2 ETM versions and variants .......................................................................... 1-5
1.3 Silicon revision ............................................................................................ 1-6
Chapter 2 Functional Description
2.1 Functional information ................................................................................. 2-2
2.2 Operation .................................................................................................... 2-4
2.3 Control logic ................................................................................................ 2-6
2.4 Data Formatter ............................................................................................ 2-8
2.5 Trigger delay counter .................................................................................. 2-9
2.6 Address generation ................................................................................... 2-10
2.7 BIST interface ........................................................................................... 2-11
2.8 TAP controller ........................................................................................... 2-12
2.9 Trace RAM interface ................................................................................. 2-15
2.10 Clocks, and resets .................................................................................... 2-17
2.11 AHB transfers ............................................................................................ 2-19

Contents
iv Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
Chapter 3 Programmer’s Model
3.1 About the programmer’s model .................................................................. 3-2
3.2 Register descriptions .................................................................................. 3-4
3.3 Software access to the ETB11 using the AHB interface .......................... 3-11
Chapter 4 Timing Requirements
4.1 AHB interface ............................................................................................. 4-2
4.2 CLK domain ................................................................................................ 4-4
4.3 IEEE1149.1 interface .................................................................................. 4-6
Appendix A Signal Descriptions
A.1 Signal properties and requirements ............................................................ A-2
A.2 Signal descriptions ..................................................................................... A-3
Appendix B Integrating the ETB11
B.1 ASIC connections ...................................................................................... B-2
B.2 Connecting to ETM11RV ............................................................................ B-3
B.3 Connecting the ETB11 in a 64-bit AHB system .......................................... B-4
Glossary

ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. v
List of Tables
ETB11 Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 ETM major architecture versions .............................................................................. 1-5
Table 2-1 Supported public instructions .................................................................................. 2-13
Table 2-2 Trace RAM interface signals ................................................................................... 2-15
Table 3-1 Register map ............................................................................................................. 3-2
Table 3-2 Identification register description ............................................................................... 3-4
Table 3-3 RAM Depth Register bit allocations .......................................................................... 3-5
Table 3-4 RAM Width Register bit allocations ........................................................................... 3-5
Table 3-5 Status Register bit allocations ................................................................................... 3-6
Table 3-6 RAM Data Register bit allocations ............................................................................ 3-7
Table 3-7 RAM Read Pointer Register bit allocations ............................................................... 3-7
Table 3-8 RAM Write Pointer Register bit allocations ............................................................... 3-8
Table 3-9 Trigger Counter Register bit allocations .................................................................... 3-9
Table 3-10 Control Register bit allocations ............................................................................... 3-10
Table 3-11 Registers that require software access ................................................................... 3-11
Table 4-1 AHB interface timing requirements ........................................................................... 4-2
Table 4-2 CLK domain timing requirements .............................................................................. 4-4
Table 4-3 IEEE1149.1 interface timing requirements ................................................................ 4-6
Table A-1 Signal descriptions .................................................................................................... A-3
Table B-1 ETB11 connection guide ........................................................................................... B-2
Table B-2 ETB11 to generic trace port interface connections ................................................... B-3

List of Tables
vi Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D

ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. vii
List of Figures
ETB11 Technical Reference Manual
Key to timing diagram conventions ............................................................................. xii
Figure 1-1 System-on-Chip debug implementation .................................................................... 1-2
Figure 2-1 ETB11 module block diagram ................................................................................... 2-3
Figure 2-2 Trace capture operation ............................................................................................ 2-6
Figure 2-3 Trace read operation ................................................................................................. 2-7
Figure 2-4 BIST interface block diagram .................................................................................. 2-11
Figure 2-5 Read access from Trace RAM timing diagram ........................................................ 2-16
Figure 2-6 Write access to Trace RAM timing diagram ............................................................ 2-16
Figure 2-7 Example synchronizer ............................................................................................. 2-17
Figure 2-8 Synchronization logic between HCLK and CLK domains ....................................... 2-20
Figure 2-9 Software read cycle with asynchronous CLK and HCLK ........................................ 2-21
Figure 2-10 Software read cycle with synchronous CLK and HCLK .......................................... 2-22
Figure 2-11 Software write cycle with asynchronous CLK and HCLK ........................................ 2-24
Figure 2-12 Software write cycle with synchronous CLK and HCLK .......................................... 2-25
Figure 4-1 AHB interface signals ................................................................................................ 4-2
Figure 4-2 CLK domain signals .................................................................................................. 4-4
Figure 4-3 IEEE1149.1 interface signals .................................................................................... 4-6

List of Figures
viii Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D

ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. ix
Preface
This preface introduces the ARM11 Embedded Trace Buffer (ETB11™) Techn ical
Reference Manual. It contains the following sections:
•About this document on page x
•Feedback on page xiv.

Preface
xCopyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
About this document
This document is the technical reference manual for the ARM11 Embedded Trace Buffer
(ETB11) r0p1.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This document has been written for experienced hardware and software engineers who
want to design or obtain trace information from chips that use ARM cores with the ETM
facility.
Using this manual
This document is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an overview of the ETB11.
Chapter 2 Functional Description
Read this chapter for a description of the major functional blocks,
configurability, read and write timing information, clocks, and resets.
Chapter 3 Programmer’s Model
Read this chapter for a description of the registers and programming
information.
Chapter 4 Timing Requirements
Read this chapter for a description of the ETB11 AC timing
requirements.
Appendix A Signal Descriptions
This appendix lists the ETB11 signals.

Preface
ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. xi
Appendix B Integrating the ETB11
This appendix describes how to integrate the ETB11 if you are not using
the ETK11 Integration Kit.
Conventions
This section describes the conventions that this manual uses:
•Typographical
•Timing diagrams on page xii
•Signal naming on page xii
•Numbering on page xiii.
Typographical
This manual uses the following typographical conventions:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
ARM processor signal names. Also used for terms in descriptive
lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects which register is accessed.

Preface
xii Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
Timing diagrams
This manual contains one or more timing diagrams. The figure named Key to timing
diagram conventions explains the components used in these diagrams. When variations
occur they have clear labels. You must not assume any timing information that is not
explicit in the diagrams.
Key to timing diagram conventions
Signal naming
The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
signals:
Prefix A Denotes Advanced eXtensible Interface (AXI) global and address
channel signals.
Prefix B Denotes AXI write response channel signals.
Prefix C Denotes AXI low-power interface signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix n Denotes Active-LOW signals except in the case of AHB or Advanced
Peripheral Bus APB reset signals. These are named HRESETn and
PRESETn respectively.
Prefix P Denotes an APB signal.
Prefix R Denotes AXI read channel signals.
Prefix W Denotes AXI write channel signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Preface
ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. xiii
Numbering
<size in bits>’<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• ‘h7B4 is an unsized hexadecimal value.
• ‘o7654 is an unsized octal value.
• 8’d9 is an eight-bit wide decimal value of 9.
• 8’h3F is an eight-bit wide hexadecimal value of
0x3F . This is
equivalent to b00111111.
• 8’b1111 is an eight-bit wide binary value of b00001111.
Further reading
This section lists publications by ARM Limited.
ARM periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and the ARM Frequently Asked
Questions.
ARM publications
This document contains information that is specific to the ETB11. Refer to the
following documents for other relevant information:
•ETB11™Implementation Guide (ARM DII 0067)
•Embedded Trace Buffer (Rev 0) Technical Reference Manual (ARM DDI 0242B)
•Embedded Trace Macrocell Specification (ARM IHI 0014)
•ETM11RV™Technical Reference Manual (ARM DDI 0233)
•ETM11RV Implementation Guide (ARM DII 0061)
•ETM11RV User Guide (ARM DUI 0223)
•ARM1136JF-S and ARM1136J-S Technical Reference Manual (ARM DDI 0211)
•ARM1136JF-S and ARM1136J-S Implementation Guide (ARM DII 0022)
•ARM1136JF-S and ARM1136J-S Test Chip Implementation Guide (ARM DXI
0144)
•ARM Architecture Reference Manual (ARM DDI 0100)
•ARM AMBA®Specification (ARM IHI 0001)
•Multi-ICE System Design Considerations (ARM DAI 0072)
•Multi-ICE®User Guide (ARM DUI 0048)
•Multi-layer AHB Overview (ARM DVI 0045).

Preface
xiv Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
Feedback
ARM Limited welcomes feedback both on the ETB11 r0p1, and on the documentation.
Feedback on the ETB11
If you have any comments or suggestions about this product, contact your supplier
giving:
• the product name
• a concise explanation of your comments.
Feedback on this document
If you have any comments on about this document, send email to
[email protected] giving:
• the document title
• the document number
• the page number(s) to which your comments refer
• a concise explanation of your comments.
General suggestions for additions and improvements are also welcome.

ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 1-1
Chapter 1
Introduction
This chapter introduces the Embedded Trace Buffer (ETB11) and its features. It
contains the following sections:
•About the Embedded Trace Buffer on page 1-2
•ETM versions and variants on page 1-5
•Silicon revision on page 1-6.

Introduction
1-2 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
1.1 About the Embedded Trace Buffer
As process speeds increase it is increasingly difficult to obtain trace information off a
chip from an Embedded Trace Macrocell (ETM). This causes difficulties in maintaining
acceptable signal quality or the signals have to be demultiplexed on to what can become
a very large number of trace port pins.
The solution is to provide a buffer area on-chip where the trace information is stored,
and read from the chip later, at a slower rate.
The ETB11 stores data produced by the ETM11RV. The buffered data can then be
accessed by the debugging tools using a JTAG (IEEE 1149.1) interface, as shown in
Figure 1-1.
Figure 1-1 System-on-Chip debug implementation
System-on-Chip
PC-based
debugging
tool
ETB11ARM processor
Peripherals
EmbeddedICE Trace
RAM
ETM11RV
On-chip
ROM
On-chip
RAM
AHB bus
Trace port
analyzer
Ethernet
JTAG
interface unit
JTAG

Introduction
ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 1-3
Providing an on-chip buffer enables the trace data generated by the ETM11RV (at the
system clock rate) to be read by the debugger at a reduced clock rate. This removes the
requirement for high-speed pads for the trace data.
This buffered data can also be accessed through an AHB slave-based AHB interface
included as part of the ETB11. This enables software running on the processor to read
the trace data generated by the ETM11RV.
The major blocks shown in Figure 1-1 on page 1-2 are:
ETM11RV The ETM11RV monitors the ARM core buses and passes compressed
information in real time to the ETB11 where it is stored for later retrieval.
The data is then passed through the JTAG trace port to an interface unit.
This is an external hardware device that passes the information from the
trace port to a debugging tool, for example, a PC. The debug tool:
• retrieves data from the interface unit
• reconstructs a historical view of processor activity including data
accesses
• configures the macrocell through the JTAG interface unit and port.
User-definable filters enable you to limit the amount of information
captured in search of a bug, reducing upload time from the trace port
analyzer.
EmbeddedICE
EmbeddedICE is a JTAG-based debugging environment for ARM
microprocessors. EmbeddedICE provides the interface between the
ARM source-level symbolic debugger, ARMxd, and an ARM
microprocessor embedded within any ASIC. The ARMxd debugger is
available for PC compatible and Sun workstation platforms.
EmbeddedICE provides:
• real-time address and data-dependent breakpoints
• single stepping
• full access and control of the ARM CPU
• access to the ASIC system.
EmbeddedICE also enables the embedded microprocessor to access the
host system peripherals, for instance screen display, keyboard input and
disk drive storage.

Introduction
1-4 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
JTAG interface unit
Boundary scan is a methodology enabling complete controllability and
observability of the boundary pins of a JTAG-compatible device by
software control. This capability enables in-circuit testing without
requiring specially designed in-circuit test equipment.

Introduction
ARM DDI 0275D Copyright © 2002, 2003 ARM Limited. All rights reserved. 1-5
1.2 ETM versions and variants
The ETB11 is an enhanced version of the ETB that is designed to support the higher
operating speeds of ETM11RV.
Although ETB11 supports older ETM protocols, it is intended for use with ETM11RV
only. For this reason this document only describes details related to storing trace from
ETM11RV. For details on using an ETB with other ETM products see the Embedded
Trace Buffer Technical Reference Manual.
The history of the ETM is listed in Table 1-1.
Table 1-1 ETM major architecture versions
Name
Major
architecture
version
ETM7 ETMv1
ETM9 ETMv1
ETM10 ETMv2
ETM XScale ETMv2
ETM10RV ETMv3
ETM11RV ETMv3

Introduction
1-6 Copyright © 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0275D
1.3 Silicon revision
This manual is for ETB11 r0p1. ETB11 r0p1 includes corrections for errata in ETB11
r0p0. Further information can be found in the ETB11 errata list.