ARM Cortex-M3 DesignStart Product manual

Copyright © 2005-2008 ARM Limited. All rights reserved.
ARM DDI 0337G
Cortex™-M3
r2p0
Technical Reference Manual

ii Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Unrestricted Access
Cortex-M3
Technical Reference Manual
Copyright © 2005-2008 ARM Limited. All rights reserved.
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Change History
Date Issue Confidentiality Change
15 December 2005 A Confidential First Release
13 January 2006 B Non-Confidential Confidentiality status amended
10 May 2006 C Non-Confidential First Release for r1p0
27 September 2006 D Non-Confidential First Release for r1p1
13 June 2007 E Non-Confidential Minor update with no technical changes
11 April 2008 F Confidential Limited release for SC300 r0p0
26 June 2008 G Non-Confidential First Release for r2p0

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Product Status
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Contents
Cortex-M3 Technical Reference Manual
Preface
About this book ............................................................................................. xx
Feedback .................................................................................................... xxv
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Components, hierarchy, and implementation .............................................. 1-4
1.3 Execution pipeline stages ......................................................................... 1-12
1.4 Prefetch Unit ............................................................................................. 1-14
1.5 Branch target forwarding ........................................................................... 1-15
1.6 Store buffers ............................................................................................. 1-18
1.7 Product revisions ...................................................................................... 1-19
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Privileged access and user access ............................................................. 2-3
2.3 Registers ..................................................................................................... 2-4
2.4 Data types ................................................................................................. 2-10
2.5 Memory formats ........................................................................................ 2-11
2.6 Instruction set summary ............................................................................ 2-13

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Chapter 3 System Control
3.1 Summary of processor registers ................................................................. 3-2
Chapter 4 Memory Map
4.1 About the memory map .............................................................................. 4-2
4.2 Bit-banding ................................................................................................. 4-5
4.3 ROM memory table .................................................................................... 4-7
Chapter 5 Exceptions
5.1 About the exception model ......................................................................... 5-2
5.2 Exception types .......................................................................................... 5-4
5.3 Exception priority ........................................................................................ 5-6
5.4 Privilege and stacks .................................................................................... 5-9
5.5 Pre-emption .............................................................................................. 5-11
5.6 Tail-chaining ............................................................................................. 5-14
5.7 Late-arriving .............................................................................................. 5-15
5.8 Exit ............................................................................................................ 5-17
5.9 Resets ...................................................................................................... 5-20
5.10 Exception control transfer ......................................................................... 5-24
5.11 Setting up multiple stacks ......................................................................... 5-25
5.12 Abort model .............................................................................................. 5-27
5.13 Activation levels ........................................................................................ 5-32
5.14 Flowcharts ................................................................................................ 5-34
Chapter 6 Clocking and Resets
6.1 Clocking ...................................................................................................... 6-2
6.2 Resets ........................................................................................................ 6-4
6.3 Cortex-M3 reset modes .............................................................................. 6-5
Chapter 7 Power Management
7.1 About power management ......................................................................... 7-2
7.2 System power management ....................................................................... 7-3
Chapter 8 Nested Vectored Interrupt Controller
8.1 About the NVIC ........................................................................................... 8-2
8.2 NVIC programmer’s model ......................................................................... 8-3
8.3 Level versus pulse interrupts .................................................................... 8-43
Chapter 9 Memory Protection Unit
9.1 About the MPU ........................................................................................... 9-2
9.2 MPU programmer’s model .......................................................................... 9-3
9.3 MPU access permissions ......................................................................... 9-13
9.4 MPU aborts ............................................................................................... 9-15
9.5 Updating an MPU region .......................................................................... 9-16
9.6 Interrupts and updating the MPU .............................................................. 9-19

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Chapter 10 Core Debug
10.1 About core debug ...................................................................................... 10-2
10.2 Core debug registers ................................................................................ 10-3
10.3 Core debug access example .................................................................. 10-12
10.4 Using application registers in core debug ............................................... 10-13
Chapter 11 System Debug
11.1 About system debug ................................................................................. 11-2
11.2 System debug access ............................................................................... 11-3
11.3 System debug programmer’s model ......................................................... 11-5
11.4 FPB ........................................................................................................... 11-6
11.5 DWT ........................................................................................................ 11-13
11.6 ITM .......................................................................................................... 11-30
11.7 AHB-AP ................................................................................................... 11-39
Chapter 12 Bus Interface
12.1 About bus interfaces ................................................................................. 12-2
12.2 AMBA 3 compliance .................................................................................. 12-3
12.3 ICode bus interface ................................................................................... 12-4
12.4 DCode bus interface ................................................................................. 12-6
12.5 System interface ....................................................................................... 12-7
12.6 Unifying the code buses ............................................................................ 12-9
12.7 External private peripheral interface ....................................................... 12-10
12.8 Access alignment .................................................................................... 12-11
12.9 Unaligned accesses that cross regions ................................................... 12-12
12.10 Bit-band accesses ................................................................................... 12-13
12.11 Write buffer ............................................................................................. 12-14
12.12 Memory attributes ................................................................................... 12-15
12.13 AHB timing characteristics ...................................................................... 12-16
Chapter 13 Debug Port
13.1 About the DP ............................................................................................. 13-2
Chapter 14 Embedded Trace Macrocell
14.1 About the ETM .......................................................................................... 14-2
14.2 Data tracing ............................................................................................... 14-7
14.3 ETM resources .......................................................................................... 14-8
14.4 Trace output ............................................................................................ 14-11
14.5 ETM architecture ..................................................................................... 14-12
14.6 ETM programmer’s model ....................................................................... 14-16
Chapter 15 Embedded Trace Macrocell Interface
15.1 About the ETM interface ........................................................................... 15-2
15.2 CPU ETM interface port descriptions ........................................................ 15-3
15.3 Branch status interface ............................................................................. 15-6

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Chapter 16 AHB Trace Macrocell Interface
16.1 About the AHB trace macrocell interface .................................................. 16-2
16.2 CPU AHB trace macrocell interface port descriptions .............................. 16-3
Chapter 17 Trace Port Interface Unit
17.1 About the TPIU ......................................................................................... 17-2
17.2 TPIU registers ........................................................................................... 17-8
17.3 Serial wire output connection ................................................................. 17-21
Chapter 18 Instruction Timing
18.1 About instruction timing ............................................................................ 18-2
18.2 Processor instruction timings .................................................................... 18-3
18.3 Load-store timings .................................................................................... 18-7
Chapter 19 AC Characteristics
19.1 Processor timing parameters .................................................................... 19-2
Appendix A Signal Descriptions
A.1 Clocks ......................................................................................................... A-2
A.2 Resets ........................................................................................................ A-3
A.3 Miscellaneous ............................................................................................. A-4
A.4 Interrupt interface ....................................................................................... A-6
A.5 Low power interface ................................................................................... A-7
A.6 ICode interface ........................................................................................... A-8
A.7 DCode interface .......................................................................................... A-9
A.8 System bus interface ................................................................................ A-10
A.9 Private Peripheral Bus interface ............................................................... A-11
A.10 ITM interface ............................................................................................. A-12
A.11 AHB-AP interface ..................................................................................... A-13
A.12 ETM interface ........................................................................................... A-14
A.13 AHB Trace Macrocell interface ................................................................. A-16
A.14 Test interface ............................................................................................ A-17
A.15 WIC interface ............................................................................................ A-18
Appendix B Revisions
Glossary

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List of Tables
Cortex-M3 Technical Reference Manual
Change History ............................................................................................................. ii
Table 2-1 Application Program Status Register bit assignments .............................................. 2-6
Table 2-2 Interrupt Program Status Register bit assignments .................................................. 2-7
Table 2-3 Bit functions of the EPSR .......................................................................................... 2-8
Table 2-4 16-bit Cortex-M3 instruction summary .................................................................... 2-13
Table 2-5 32-bit Cortex-M3 instruction summary .................................................................... 2-16
Table 3-1 NVIC registers ........................................................................................................... 3-2
Table 3-2 Core debug registers ................................................................................................. 3-5
Table 3-3 Flash patch register summary ................................................................................... 3-6
Table 3-4 DWT register summary ............................................................................................. 3-7
Table 3-5 ITM register summary ............................................................................................... 3-9
Table 3-6 AHB-AP register summary ...................................................................................... 3-10
Table 3-7 Summary of Debug interface port registers ............................................................ 3-10
Table 3-8 MPU registers ......................................................................................................... 3-11
Table 3-9 TPIU registers ......................................................................................................... 3-12
Table 3-10 ETM registers .......................................................................................................... 3-13
Table 4-1 Memory interfaces ..................................................................................................... 4-3
Table 4-2 Memory region permissions ...................................................................................... 4-4
Table 4-3 ROM table ................................................................................................................. 4-7
Table 5-1 Exception types ......................................................................................................... 5-4
Table 5-2 Priority-based actions of exceptions ......................................................................... 5-6
Table 5-3 Priority grouping ........................................................................................................ 5-8
Table 5-4 Exception entry steps .............................................................................................. 5-12

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Table 5-5 Exception exit steps ................................................................................................ 5-17
Table 5-6 Exception return behavior ....................................................................................... 5-19
Table 5-7 Reset actions .......................................................................................................... 5-20
Table 5-8 Reset boot-up behavior .......................................................................................... 5-21
Table 5-9 Transferring to exception processing ...................................................................... 5-24
Table 5-10 Faults ...................................................................................................................... 5-28
Table 5-11 Debug faults ............................................................................................................ 5-30
Table 5-12 Fault status and fault address registers .................................................................. 5-31
Table 5-13 Privilege and stack of different activation levels ..................................................... 5-32
Table 5-14 Exception transitions ............................................................................................... 5-32
Table 5-15 Exception subtype transitions ................................................................................. 5-33
Table 6-1 Cortex-M3 processor clocks ..................................................................................... 6-2
Table 6-2 Cortex-M3 macrocell clocks ...................................................................................... 6-2
Table 6-3 Reset inputs .............................................................................................................. 6-4
Table 6-4 Reset modes ............................................................................................................. 6-5
Table 7-1 Supported sleep modes ............................................................................................ 7-3
Table 8-1 NVIC registers .......................................................................................................... 8-3
Table 8-2 Interrupt Controller Type Register bit assignments .................................................. 8-8
Table 8-3 Auxiliary Control Register bit assignments ............................................................... 8-9
Table 8-4 SysTick Control and Status Register bit assignments ............................................ 8-10
Table 8-5 SysTick Reload Value Register bit assignments .................................................... 8-11
Table 8-6 SysTick Current Value Register bit assignments .................................................... 8-12
Table 8-7 SysTick Calibration Value Register bit assignments .............................................. 8-12
Table 8-8 Interrupt Set-Enable Register bit assignments ....................................................... 8-14
Table 8-9 Interrupt Clear-Enable Register bit assignments .................................................... 8-14
Table 8-10 Interrupt Set-Pending Register bit assignments ..................................................... 8-15
Table 8-11 Interrupt Clear-Pending Registers bit assignments ................................................ 8-16
Table 8-12 Active Bit Register bit assignments ........................................................................ 8-16
Table 8-13 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-18
Table 8-14 CPUID Base Register bit assignments ................................................................... 8-18
Table 8-15 Interrupt Control State Register bit assignments .................................................... 8-20
Table 8-16 Vector Table Offset Register bit assignments ........................................................ 8-22
Table 8-17 Application Interrupt and Reset Control Register bit assignments ......................... 8-23
Table 8-18 System Control Register bit assignments ............................................................... 8-26
Table 8-19 Configuration Control Register bit assignments ..................................................... 8-27
Table 8-20 System Handler Priority Registers bit assignments ................................................ 8-29
Table 8-21 System Handler Control and State Register bit assignments ................................. 8-30
Table 8-22 Memory Manage Fault Status Register bit assignments ........................................ 8-33
Table 8-23 Bus Fault Status Register bit assignments ............................................................. 8-35
Table 8-24 Usage Fault Status Register bit assignments ......................................................... 8-36
Table 8-25 Hard Fault Status Register bit assignments ........................................................... 8-38
Table 8-26 Debug Fault Status Register bit assignments ......................................................... 8-39
Table 8-27 Memory Manage Fault Address Register bit assignments ..................................... 8-40
Table 8-28 Bus Fault Address Register bit assignments .......................................................... 8-41
Table 8-29 Auxiliary Fault Status Register bit assignments ...................................................... 8-42
Table 8-30 Software Trigger Interrupt Register bit assignments .............................................. 8-42
Table 9-1 MPU registers ........................................................................................................... 9-3

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Table 9-2 MPU Type Register bit assignments ......................................................................... 9-4
Table 9-3 MPU Control Register bit assignments ..................................................................... 9-6
Table 9-4 MPU Region Number Register bit assignments ........................................................ 9-7
Table 9-5 MPU Region Base Address Register bit assignments .............................................. 9-8
Table 9-6 MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Table 9-7 MPU protection region size field ............................................................................. 9-10
Table 9-8 TEX, C, B encoding ................................................................................................. 9-13
Table 9-9 Cache policy for memory attribute encoding ........................................................... 9-14
Table 9-10 AP encoding ............................................................................................................ 9-14
Table 9-11 XN encoding ............................................................................................................ 9-14
Table 10-1 Core debug registers ............................................................................................... 10-2
Table 10-2 Debug Halting Control and Status Register ............................................................ 10-4
Table 10-3 Debug Core Register Selector Register .................................................................. 10-7
Table 10-4 Debug Exception and Monitor Control Register ...................................................... 10-9
Table 10-5 Application registers for use in core debug ........................................................... 10-13
Table 11-1 FPB register summary ............................................................................................ 11-7
Table 11-2 Flash Patch Control Register bit assignments ........................................................ 11-8
Table 11-3 COMP mapping ..................................................................................................... 11-10
Table 11-4 Flash Patch Remap Register bit assignments ...................................................... 11-11
Table 11-5 Flash Patch Comparator Registers bit assignments ............................................. 11-12
Table 11-6 DWT register summary ......................................................................................... 11-14
Table 11-7 DWT Control Register bit assignments ................................................................. 11-16
Table 11-8 DWT Current PC Sampler Cycle Count Register bit assignments ........................ 11-19
Table 11-9 DWT CPI Count Register bit assignments ............................................................ 11-20
Table 11-10 DWT Exception Overhead Count Register bit assignments .................................. 11-21
Table 11-11 DWT Sleep Count Register bit assignments ......................................................... 11-22
Table 11-12 DWT LSU Count Register bit assignments ........................................................... 11-23
Table 11-13 DWT Fold Count Register bit assignments ........................................................... 11-23
Table 11-14 DWT Program Counter Sample Register bit assignments .................................... 11-24
Table 11-15 DWT Comparator Registers 0-3 bit assignments .................................................. 11-24
Table 11-16 DWT Mask Registers 0-3 bit assignments ............................................................ 11-25
Table 11-17 Bit functions of DWT Function Registers 0-3 ........................................................ 11-26
Table 11-18 Settings for DWT Function Registers .................................................................... 11-28
Table 11-19 ITM register summary ........................................................................................... 11-30
Table 11-20 ITM Trace Enable Register bit assignments ......................................................... 11-32
Table 11-21 ITM Trace Privilege Register bit assignments ....................................................... 11-33
Table 11-22 ITM Trace Control Register bit assignments ......................................................... 11-34
Table 11-23 ITM Integration Write Register bit assignments .................................................... 11-36
Table 11-24 ITM Integration Read Register bit assignments .................................................... 11-36
Table 11-25 ITM Integration Mode Control Register bit assignments ....................................... 11-37
Table 11-26 ITM Lock Access Register bit assignments .......................................................... 11-37
Table 11-27 ITM Lock Status Register bit assignments ............................................................ 11-38
Table 11-28 AHB-AP register summary .................................................................................... 11-40
Table 11-29 AHB-AP Control and Status Word Register bit assignments ................................ 11-41
Table 11-30 AHB-AP Transfer Address Register bit assignments ............................................ 11-42
Table 11-31 AHB-AP Data Read/Write Register bit assignments ............................................. 11-43
Table 11-32 AHB-AP Banked Data Register bit assignments ................................................... 11-43

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Table 11-33 AHB-AP Debug ROM Address Register bit assignments ..................................... 11-44
Table 11-34 AHB-AP ID Register bit assignments ................................................................... 11-44
Table 12-1 Instruction fetches ................................................................................................... 12-4
Table 12-2 Bus mapper unaligned accesses .......................................................................... 12-11
Table 12-3 Memory attributes ................................................................................................. 12-15
Table 12-4 Interface timing characteristics ............................................................................. 12-16
Table 14-1 ETM core interface inputs and outputs ................................................................... 14-4
Table 14-2 Miscellaneous configuration inputs ......................................................................... 14-4
Table 14-3 Trace port signals ................................................................................................... 14-5
Table 14-4 Other signals ........................................................................................................... 14-5
Table 14-5 Clocks and resets ................................................................................................... 14-6
Table 14-6 APB interface signals .............................................................................................. 14-6
Table 14-7 Cortex-M3 resources .............................................................................................. 14-8
Table 14-8 Exception tracing mapping ................................................................................... 14-13
Table 14-9 ETM registers ....................................................................................................... 14-16
Table 14-10 Boolean function encoding for events ................................................................... 14-22
Table 14-11 Resource identification encoding .......................................................................... 14-23
Table 14-12 Input connections .................................................................................................. 14-23
Table 14-13 Trigger output connections ................................................................................... 14-23
Table 15-1 ETM interface ports ................................................................................................ 15-3
Table 15-2 Branch status signal function .................................................................................. 15-6
Table 15-3 Branches and stages evaluated by the processor .................................................. 15-7
Table 15-4 Example of an opcode sequence ......................................................................... 15-11
Table 16-1 AHB interface ports ................................................................................................. 16-3
Table 17-1 Trace out port signals ............................................................................................. 17-5
Table 17-2 ATB port signals ..................................................................................................... 17-6
Table 17-3 Miscellaneous configuration inputs ......................................................................... 17-6
Table 17-4 APB interface .......................................................................................................... 17-7
Table 17-5 TPIU registers ......................................................................................................... 17-8
Table 17-6 Async Clock Prescaler Register bit assignments ................................................. 17-10
Table 17-7 Selected Pin Protocol Register bit assignments ................................................... 17-11
Table 17-8 Formatter and Flush Status Register bit assignments .......................................... 17-12
Table 17-9 Formatter and Flush Control Register bit assignments ........................................ 17-13
Table 17-10 Integration Test Register-ITATBCTR2 bit assignments ........................................ 17-15
Table 17-11 Integration Test Register-ITATBCTR0 bit assignments ........................................ 17-16
Table 17-12 Integration Mode Control Register bit assignments .............................................. 17-17
Table 17-13 Integration Register : TRIGGER bit assignments ................................................. 17-17
Table 17-14 Integration register : FIFO data 0 bit assignments ................................................ 17-18
Table 17-15 Integration register : FIFO data 1 bit assignments ................................................ 17-19
Table 18-1 Instruction timings ................................................................................................... 18-3
Table 19-1 Miscellaneous input ports timing parameters ......................................................... 19-2
Table 19-2 Low power input ports timing parameters ............................................................... 19-2
Table 19-3 Interrupt input ports timing parameters ................................................................... 19-3
Table 19-4 AHB input ports timing parameters ......................................................................... 19-3
Table 19-5 PPB input port timing parameters ........................................................................... 19-4
Table 19-6 Debug input ports timing parameters ...................................................................... 19-4
Table 19-7 Test input ports timing parameters ......................................................................... 19-5

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Table 19-8 ETM input port timing parameters ........................................................................... 19-5
Table 19-9 Miscellaneous output ports timing parameters ........................................................ 19-5
Table 19-10 Low power output ports timing parameters ............................................................. 19-6
Table 19-11 AHB output ports timing parameters ....................................................................... 19-6
Table 19-12 PPB output ports timing parameters ....................................................................... 19-8
Table 19-13 Debug interface output ports timing parameters ..................................................... 19-8
Table 19-14 ETM interface output ports timing parameters ........................................................ 19-9
Table 19-15 HTM interface output ports timing parameters ........................................................ 19-9
Table 19-16 Test output ports timing parameters ..................................................................... 19-10
Table A-1 Clock signals ............................................................................................................. A-2
Table A-2 Reset signals ............................................................................................................. A-3
Table A-3 Miscellaneous signals ............................................................................................... A-4
Table A-4 Interrupt interface signals .......................................................................................... A-6
Table A-5 Low power interface signals ...................................................................................... A-7
Table A-6 ICode interface .......................................................................................................... A-8
Table A-7 DCode interface ........................................................................................................ A-9
Table A-8 System bus interface ............................................................................................... A-10
Table A-9 Private Peripheral Bus interface .............................................................................. A-11
Table A-10 ITM interface ........................................................................................................... A-12
Table A-11 AHB-AP interface .................................................................................................... A-13
Table A-12 ETM interface .......................................................................................................... A-14
Table A-13 HTM interface .......................................................................................................... A-16
Table A-14 Test interface .......................................................................................................... A-17
Table A-15 WIC interface signals .............................................................................................. A-18
Table B-1 Differences between issue E and issue F ................................................................. B-1
Table B-2 Differences between issue F and issue G ................................................................. B-5

List of Tables
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List of Figures
Cortex-M3 Technical Reference Manual
Key to timing diagram conventions .......................................................................... xxiii
Figure 1-1 Cortex-M3 block diagram .......................................................................................... 1-5
Figure 1-2 Cortex-M3 pipeline stages ...................................................................................... 1-12
Figure 2-1 Processor register set ............................................................................................... 2-4
Figure 2-2 Application Program Status Register bit assignments .............................................. 2-6
Figure 2-3 Interrupt Program Status Register bit assignments .................................................. 2-6
Figure 2-4 Execution Program Status Register .......................................................................... 2-8
Figure 2-5 Little-endian and big-endian memory formats ......................................................... 2-12
Figure 4-1 Processor memory map ............................................................................................ 4-2
Figure 4-2 Bit-band mapping ...................................................................................................... 4-6
Figure 5-1 Stack contents after pre-emption ............................................................................ 5-11
Figure 5-2 Exception entry timing ............................................................................................. 5-13
Figure 5-3 Tail-chaining timing ................................................................................................. 5-14
Figure 5-4 Late-arriving exception timing ................................................................................. 5-15
Figure 5-5 Exception exit timing ............................................................................................... 5-18
Figure 5-6 Interrupt handling flowchart ..................................................................................... 5-34
Figure 5-7 Pre-emption flowchart ............................................................................................. 5-35
Figure 5-8 Return from interrupt flowchart ................................................................................ 5-36
Figure 6-1 Reset signals ............................................................................................................. 6-6
Figure 6-2 Power-on reset .......................................................................................................... 6-6
Figure 6-3 Internal reset synchronization ................................................................................... 6-7
Figure 7-1 SLEEPING power control example ........................................................................... 7-4
Figure 7-2 SLEEPDEEP power control example ........................................................................ 7-5

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Figure 7-3 WIC mode enable sequence .................................................................................... 7-7
Figure 7-4 Power down timing sequence ................................................................................... 7-8
Figure 7-5 PMU, WIC, and Cortex-M3 interconnect .................................................................. 7-9
Figure 8-1 Interrupt Controller Type Register bit assignments .................................................. 8-7
Figure 8-2 Auxiliary Control Register bit assignments ............................................................... 8-8
Figure 8-3 SysTick Control and Status Register bit assignments .............................................. 8-9
Figure 8-4 SysTick Reload Value Register bit assignments .................................................... 8-11
Figure 8-5 SysTick Current Value Register bit assignments .................................................... 8-11
Figure 8-6 SysTick Calibration Value Register bit assignments .............................................. 8-12
Figure 8-7 Interrupt Priority Registers 0-31 bit assignments .................................................... 8-17
Figure 8-8 CPUID Base Register bit assignments ................................................................... 8-18
Figure 8-9 Interrupt Control State Register bit assignments .................................................... 8-20
Figure 8-10 Vector Table Offset Register bit assignments ........................................................ 8-22
Figure 8-11 Application Interrupt and Reset Control Register bit assignments ......................... 8-23
Figure 8-12 System Control Register bit assignments ............................................................... 8-25
Figure 8-13 Configuration Control Register bit assignments ..................................................... 8-27
Figure 8-14 System Handler Priority Registers bit assignments ................................................ 8-29
Figure 8-15 System Handler Control and State Register bit assignments ................................. 8-30
Figure 8-16 Configurable Fault Status Registers bit assignments ............................................. 8-32
Figure 8-17 Memory Manage Fault Status Register bit assignments ........................................ 8-33
Figure 8-18 Bus Fault Status Register bit assignments ............................................................. 8-34
Figure 8-19 Usage Fault Status Register bit assignments ......................................................... 8-36
Figure 8-20 Hard Fault Status Register bit assignments ........................................................... 8-37
Figure 8-21 Debug Fault Status Register bit assignments ......................................................... 8-39
Figure 8-22 Software Trigger Interrupt Register bit assignments .............................................. 8-42
Figure 9-1 MPU Type Register bit assignments ........................................................................ 9-4
Figure 9-2 MPU Control Register bit assignments ..................................................................... 9-5
Figure 9-3 MPU Region Number Register bit assignments ....................................................... 9-7
Figure 9-4 MPU Region Base Address Register bit assignments .............................................. 9-8
Figure 9-5 MPU Region Attribute and Size Register bit assignments ........................................ 9-9
Figure 10-1 Debug Halting Control and Status Register bit assignments .................................. 10-4
Figure 10-2 Debug Core Register Selector Register bit assignments ....................................... 10-6
Figure 10-3 Debug Exception and Monitor Control Register bit assignments ........................... 10-9
Figure 11-1 System debug access block diagram ..................................................................... 11-4
Figure 11-2 Flash Patch Control Register bit assignments ........................................................ 11-8
Figure 11-3 Flash Patch Remap Register bit assignments ...................................................... 11-10
Figure 11-4 Flash Patch Comparator Registers bit assignments ............................................. 11-11
Figure 11-5 DWT Control Register bit assignments ................................................................. 11-16
Figure 11-6 DWT CPI Count Register bit assignments ............................................................ 11-20
Figure 11-7 DWT Exception Overhead Count Register bit assignments ................................. 11-21
Figure 11-8 DWT Sleep Count Register bit assignments ........................................................ 11-21
Figure 11-9 DWT LSU Count Register bit assignments ........................................................... 11-22
Figure 11-10 DWT Fold Count Register bit assignments ........................................................... 11-23
Figure 11-11 DWT Mask Registers 0-3 bit assignments ............................................................ 11-25
Figure 11-12 DWT Function Registers 0-3 bit assignments ...................................................... 11-26
Figure 11-13 ITM Trace Privilege Register bit assignments ...................................................... 11-33
Figure 11-14 ITM Trace Control Register bit assignments ........................................................ 11-34

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Figure 11-15 ITM Integration Write Register bit assignments .................................................... 11-35
Figure 11-16 ITM Integration Read Register bit assignments .................................................... 11-36
Figure 11-17 ITM Integration Mode Control bit assignments ..................................................... 11-37
Figure 11-18 ITM Lock Status Register bit assignments ............................................................ 11-38
Figure 11-19 AHB-AP Control and Status Word Register .......................................................... 11-41
Figure 11-20 AHB-AP ID Register .............................................................................................. 11-44
Figure 12-1 ICode/DCode multiplexer ........................................................................................ 12-9
Figure 14-1 ETM block diagram ................................................................................................. 14-3
Figure 14-2 Return from exception packet encoding ................................................................ 14-12
Figure 14-3 Exception encoding for branch packet .................................................................. 14-14
Figure 15-1 Conditional branch backwards not taken ................................................................ 15-8
Figure 15-2 Conditional branch backwards taken ...................................................................... 15-9
Figure 15-3 Conditional branch forwards not taken .................................................................... 15-9
Figure 15-4 Conditional branch forwards taken .......................................................................... 15-9
Figure 15-5 Unconditional branch without pipeline stalls ......................................................... 15-10
Figure 15-6 Unconditional branch with pipeline stalls .............................................................. 15-10
Figure 15-7 Unconditional branch in execute aligned .............................................................. 15-11
Figure 15-8 Unconditional branch in execute unaligned .......................................................... 15-11
Figure 15-9 Example of an opcode sequence .......................................................................... 15-13
Figure 17-1 TPIU block diagram (non-ETM version) .................................................................. 17-3
Figure 17-2 TPIU block diagram (ETM version) ......................................................................... 17-4
Figure 17-3 Supported Sync Port Size Register bit assignments ............................................. 17-10
Figure 17-4 Async Clock Prescaler Register bit assignments .................................................. 17-10
Figure 17-5 Selected Pin Protocol Register bit assignments ................................................... 17-11
Figure 17-6 Formatter and Flush Status Register bit assignments .......................................... 17-12
Figure 17-7 Formatter and Flush Control Register bit assignments ......................................... 17-13
Figure 17-8 Integration Test Register-ITATBCTR2 bit assignments ........................................ 17-15
Figure 17-9 Integration Test Register-ITATBCTR0 bit assignments ........................................ 17-16
Figure 17-10 Integration Mode Control Register bit assignments .............................................. 17-16
Figure 17-11 Integration Register : TRIGGER bit assignments ................................................. 17-17
Figure 17-12 Integration register : FIFO data 0 bit assignments ................................................ 17-18
Figure 17-13 Integration register : FIFO data 1 bit assignments ................................................ 17-19
Figure 17-14 Dedicated pin used for TRACESWO .................................................................... 17-21
Figure 17-15 SWO shared with TRACEPORT ........................................................................... 17-22
Figure 17-16 SWO shared with JTAG-TDO ............................................................................... 17-22

List of Figures
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Preface
This preface introduces the Cortex-M3 Technical Reference Manual (TRM). It contains
the following sections:
•About this book on page xx
•Feedback on page xxv.

Preface
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About this book
This book is for the Cortex-M3 processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual is written to help system designers, system integrators, and verification
engineers who are implementing a System-on-Chip (SoC) device based on the
Cortex-M3 processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for a description of the components of the processor, and about
the processor instruction set.
Chapter 2 Programmer’s Model
Read this for a description of the processor register set, modes of
operation, and other information for programming the processor.
Chapter 3 System Control
Read this for a description of the registers and programmer’s model for
system control.
Chapter 4 Memory Map
Read this for a description of the processor memory map and bit-banding
feature.
Chapter 5 Exceptions
Read this for a description of the processor exception model.
Chapter 6 Clocking and Resets
Read this chapter for a description of the processor clocking and resets.