ARM ARM926EJ-S Product manual

Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI0198D
ARM926EJ-S
(r0p4/r0p5)
Technical Reference Manual

ii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
ARM926EJ-S
Technical Reference Manual
Copyright © 2001-2003 ARM Limited. All rights reserved.
Release Information
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This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
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such information, or any incorrect use of the product.
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This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
26 September 2001 A First release
29 January 2002 B Second release
5 December 2003 C Third release. Includes r0p5 changes. Defects corrected.
26 January 2004 D Fourth release. Includes r0p4. Technically identical to previous release.

ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. iii
Contents
ARM926EJ-S Technical Reference Manual
Preface
About this manual ........................................................................................ xvi
Feedback ..................................................................................................... xxi
Chapter 1 Introduction
1.1 About the ARM926EJ-S processor ............................................................. 1-2
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3
2.3 Register descriptions .................................................................................. 2-7
Chapter 3 Memory Management Unit
3.1 About the MMU ........................................................................................... 3-2
3.2 Address translation ..................................................................................... 3-5
3.3 MMU faults and CPU aborts ..................................................................... 3-21
3.4 Domain access control .............................................................................. 3-24
3.5 Fault checking sequence .......................................................................... 3-26
3.6 External aborts .......................................................................................... 3-29
3.7 TLB structure ............................................................................................ 3-31

Contents
iv Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Chapter 4 Caches and Write Buffer
4.1 About the caches and write buffer .............................................................. 4-2
4.2 Write buffer ................................................................................................. 4-4
4.3 Enabling the caches ................................................................................... 4-5
4.4 TCM and cache access priorities ............................................................... 4-8
4.5 Cache MVA and Set/Way formats .............................................................. 4-9
Chapter 5 Tightly-Coupled Memory Interface
5.1 About the tightly-coupled memory interface ............................................... 5-2
5.2 TCM interface signals ................................................................................. 5-4
5.3 TCM interface bus cycle types and timing .................................................. 5-8
5.4 TCM programmer’s model ........................................................................ 5-19
5.5 TCM interface examples ........................................................................... 5-20
5.6 TCM access penalties .............................................................................. 5-29
5.7 TCM write buffer ....................................................................................... 5-30
5.8 Using synchronous SRAM as TCM memory ............................................ 5-31
5.9 TCM clock gating ...................................................................................... 5-32
Chapter 6 Bus Interface Unit
6.1 About the bus interface unit ........................................................................ 6-2
6.2 Supported AHB transfers ............................................................................ 6-3
Chapter 7 Noncachable Instruction Fetches
7.1 About noncachable instruction fetches ....................................................... 7-2
Chapter 8 Coprocessor Interface
8.1 About the ARM926EJ-S external coprocessor interface ............................ 8-2
8.2 LDC/STC .................................................................................................... 8-4
8.3 MCR/MRC .................................................................................................. 8-6
8.4 CDP ............................................................................................................ 8-8
8.5 Privileged instructions ................................................................................. 8-9
8.6 Busy-waiting and interrupts ...................................................................... 8-10
8.7 CPBURST ................................................................................................ 8-11
8.8 CPABORT ................................................................................................ 8-12
8.9 nCPINSTRVALID ..................................................................................... 8-13
8.10 Connecting multiple external coprocessors .............................................. 8-14
Chapter 9 Instruction Memory Barrier
9.1 About the instruction memory barrier operation ......................................... 9-2
9.2 IMB operation ............................................................................................. 9-3
9.3 Example IMB sequences ............................................................................ 9-5
Chapter 10 Embedded Trace Macrocell Support
10.1 About Embedded Trace Macrocell support .............................................. 10-2

Contents
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. v
Chapter 11 Debug Support
11.1 About debug support ................................................................................. 11-2
Chapter 12 Power Management
12.1 About power management ........................................................................ 12-2
Appendix A Signal Descriptions
A.1 Signal properties and requirements ............................................................ A-2
A.2 AHB related signals .................................................................................... A-3
A.3 Coprocessor interface signals ..................................................................... A-5
A.4 Debug signals ............................................................................................. A-7
A.5 JTAG signals ............................................................................................... A-9
A.6 Miscellaneous signals ............................................................................... A-10
A.7 ETM interface signals ............................................................................... A-12
A.8 TCM interface signals ............................................................................... A-14
Appendix B CP15 Test and Debug Registers
B.1 About the Test and Debug Registers .......................................................... B-2
Glossary

Contents
vi Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D

ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. vii
List of Tables
ARM926EJ-S Technical Reference Manual
Change history .............................................................................................................. ii
Table 2-1 CP15 register summary ............................................................................................ 2-3
Table 2-2 Address types in ARM926EJ-S ................................................................................. 2-4
Table 2-3 CP15 abbreviations ................................................................................................... 2-5
Table 2-4 Reading from register c0 ........................................................................................... 2-7
Table 2-5 Register 0, ID code ................................................................................................... 2-8
Table 2-6 Ctype encoding ......................................................................................................... 2-9
Table 2-7 Cache size encoding (M=0) .................................................................................... 2-10
Table 2-8 Cache associativity encoding (M=0) ....................................................................... 2-10
Table 2-9 Line length encoding ............................................................................................... 2-11
Table 2-10 Example Cache Type Register format .................................................................... 2-11
Table 2-11 Control bit functions register c1 ............................................................................... 2-13
Table 2-12 Effects of Control Register on caches ..................................................................... 2-15
Table 2-13 Effects of Control Register on TCM interface .......................................................... 2-16
Table 2-14 Domain access control defines ............................................................................... 2-18
Table 2-15 FSR bit field descriptions ........................................................................................ 2-19
Table 2-16 FSR status field encoding ....................................................................................... 2-20
Table 2-17 Function descriptions register c7 ............................................................................ 2-21
Table 2-18 Cache operations c7 ............................................................................................... 2-22
Table 2-19 Register c8 TLB operations ..................................................................................... 2-25
Table 2-20 Cache Lockdown Register instructions ................................................................... 2-27
Table 2-21 Cache Lockdown Register L bits ............................................................................. 2-28
Table 2-22 TCM Region Register instructions .......................................................................... 2-29

List of Tables
viii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Table 2-23 TCM Region Register c9 ........................................................................................ 2-30
Table 2-24 TCM Size field encoding ......................................................................................... 2-30
Table 2-25 Programming the TLB Lockdown Register ............................................................. 2-32
Table 2-26 FCSE PID Register operations ............................................................................... 2-34
Table 2-27 Context ID register operations ................................................................................ 2-35
Table 3-1 MMU program-accessible CP15 registers ................................................................ 3-4
Table 3-2 First-level descriptor bits ........................................................................................... 3-9
Table 3-3 Interpreting first-level descriptor bits [1:0] ............................................................... 3-10
Table 3-4 Section descriptor bits ............................................................................................ 3-11
Table 3-5 Coarse page table descriptor bits ........................................................................... 3-12
Table 3-6 Fine page table descriptor bits ................................................................................ 3-13
Table 3-7 Second-level descriptor bits .................................................................................... 3-15
Table 3-8 Interpreting page table entry bits [1:0] .................................................................... 3-16
Table 3-9 Priority encoding of fault status ............................................................................... 3-22
Table 3-10 FAR values for multi-word transfers ....................................................................... 3-23
Table 3-11 Domain access control register, access control bits ............................................... 3-24
Table 3-12 Interpreting access permission (AP) bits ................................................................ 3-24
Table 4-1 CP15 c1 I and M bit settings for the ICache ............................................................. 4-5
Table 4-2 Page table C bit settings for the ICache ................................................................... 4-5
Table 4-3 CP15 c1 C and M bit settings for the DCache .......................................................... 4-6
Table 4-4 Page table C and B bit settings for the DCache ....................................................... 4-6
Table 4-5 Instruction access priorities to the TCM and cache .................................................. 4-8
Table 4-6 Data access priorities to the TCM and cache ........................................................... 4-8
Table 4-7 Values of S and NSETS ......................................................................................... 4-10
Table 5-1 Relationship between DMDMAEN, DRDMACS, and DRIDLE ................................. 5-6
Table 6-1 Supported HBURST encodings ................................................................................ 6-4
Table 6-2 IHPROT[3:0] and DHPROT[3:0] attributes ............................................................... 6-5
Table 8-1 Handshake signal encoding ...................................................................................... 8-5
Table 8-2 CPBURST encoding ............................................................................................... 8-11
Table 11-1 Scan chain 15 format .............................................................................................. 11-2
Table 11-2 Scan chain 15 mapping to CP15 registers ............................................................. 11-4
Table A-1 AHB related signals .................................................................................................. A-3
Table A-2 Coprocessor interface signals .................................................................................. A-5
Table A-3 Debug signals ........................................................................................................... A-7
Table A-4 JTAG signals ............................................................................................................ A-9
Table A-5 Miscellaneous signals ............................................................................................. A-10
Table A-6 ETM interface signals ............................................................................................. A-12
Table A-7 TCM interface signals ............................................................................................. A-14
Table B-1 Debug Override Register .......................................................................................... B-3
Table B-2 Trace Control Register bit assignments .................................................................... B-5
Table B-3 MMU test operation instructions ............................................................................... B-5
Table B-4 Encoding of the main TLB entry-select bit fields ....................................................... B-6
Table B-5 Encoding of the TLB MVA tag bit fields .................................................................... B-7
Table B-6 Encoding of the TLB entry PA and AP bit fields ....................................................... B-8
Table B-7 Main TLB mapping to MMUxWD .............................................................................. B-9
Table B-8 Encoding of the lockdown TLB entry-select bit fields ............................................. B-11
Table B-9 Cache Debug Control Register bit assignments ..................................................... B-12

List of Tables
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. ix
Table B-10 MMU Debug Control Register bit assignments ....................................................... B-14
Table B-11 Memory Region Remap Register instructions ......................................................... B-15
Table B-12 Encoding of the Memory Region Remap Register .................................................. B-16
Table B-13 Encoding of the remap fields ................................................................................... B-16

List of Tables
xCopyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D

ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xi
List of Figures
ARM926EJ-S Technical Reference Manual
Key to timing diagram conventions ............................................................................ xix
Figure 1-1 ARM926EJ-S block diagram ..................................................................................... 1-3
Figure 1-2 ARM926EJ-S interface diagram (part one) ............................................................... 1-4
Figure 1-3 ARM926EJ-S interface diagram (part two) ............................................................... 1-5
Figure 2-1 CP15 MRC and MCR bit pattern ............................................................................... 2-5
Figure 2-2 Cache Type Register format ..................................................................................... 2-9
Figure 2-3 Dsize and Isize field format ....................................................................................... 2-9
Figure 2-4 TCM Status Register format .................................................................................... 2-12
Figure 2-5 Control Register format ........................................................................................... 2-13
Figure 2-6 TTBR format ............................................................................................................ 2-17
Figure 2-7 Register c3 format ................................................................................................... 2-18
Figure 2-8 FSR format .............................................................................................................. 2-19
Figure 2-9 Register c7 MVA format .......................................................................................... 2-23
Figure 2-10 Register c7 Set/Way format .................................................................................... 2-24
Figure 2-11 Register c8 MVA format .......................................................................................... 2-26
Figure 2-12 Cache Lockdown Register c9 format ...................................................................... 2-27
Figure 2-13 TCM Region Register c9 format .............................................................................. 2-30
Figure 2-14 TLB Lockdown Register format ............................................................................... 2-32
Figure 2-15 Process ID Register format ..................................................................................... 2-34
Figure 2-16 Context ID Register format ...................................................................................... 2-35
Figure 3-1 Translation Table Base Register ............................................................................... 3-6
Figure 3-2 Translating page tables ............................................................................................. 3-7
Figure 3-3 Accessing translation table first-level descriptors ...................................................... 3-8

List of Figures
xii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Figure 3-4 First-level descriptor ................................................................................................. 3-9
Figure 3-5 Section descriptor ................................................................................................... 3-10
Figure 3-6 Coarse page table descriptor .................................................................................. 3-11
Figure 3-7 Fine page table descriptor ...................................................................................... 3-12
Figure 3-8 Section translation .................................................................................................. 3-14
Figure 3-9 Second-level descriptor .......................................................................................... 3-15
Figure 3-10 Large page translation from a coarse page table ................................................... 3-17
Figure 3-11 Small page translation from a coarse page table ................................................... 3-18
Figure 3-12 Tiny page translation from a fine page table ........................................................... 3-19
Figure 3-13 Sequence for checking faults .................................................................................. 3-26
Figure 4-1 Generic virtually indexed virtually addressed cache ................................................. 4-9
Figure 4-2 ARM926EJ-S cache associativity ........................................................................... 4-10
Figure 4-3 ARM926EJ-S cache Set/Way/Word format ............................................................ 4-11
Figure 5-1 Multi-cycle data side TCM access ............................................................................ 5-8
Figure 5-2 Instruction side zero wait state accesses ................................................................. 5-9
Figure 5-3 Data side zero wait state accesses ........................................................................ 5-10
Figure 5-4 Relationship between DRDMAEN, DRDMACS, DRDMAADDR, DRADDR and DRCS ..
5-11
Figure 5-5 DMA access interaction with normal DTCM accesses ........................................... 5-12
Figure 5-6 Generating a single wait state for ITCM accesses using IRWAIT .......................... 5-13
Figure 5-7 State machine for generating a single wait state .................................................... 5-14
Figure 5-8 Loopback of SEQ to produce a single cycle wait state ........................................... 5-14
Figure 5-9 Cycle timing of loopback circuit .............................................................................. 5-15
Figure 5-10 DMA with single wait state for nonsequential accesses ......................................... 5-16
Figure 5-11 Cycle timing of circuit with DMA and single wait state for nonsequential accesses 5-17
Figure 5-12 Zero wait state RAM example ................................................................................. 5-20
Figure 5-13 Byte-banks of RAM example .................................................................................. 5-21
Figure 5-14 Optimizing for power ............................................................................................... 5-23
Figure 5-15 Optimizing for speed ............................................................................................... 5-24
Figure 5-16 TCM subsystem that uses wait states for nonsequential accesses ........................ 5-25
Figure 5-17 Cycle timing of circuit that uses wait states for non sequential accesses ............... 5-26
Figure 5-18 TCM subsystem that uses the DMA interface ........................................................ 5-27
Figure 5-19 TCM test access using BIST .................................................................................. 5-28
Figure 6-1 Multi-layer AHB system example ............................................................................. 6-8
Figure 6-2 Multi-AHB system example ...................................................................................... 6-9
Figure 6-3 AHB clock relationships .......................................................................................... 6-10
Figure 8-1 Producing a coprocessor clock ................................................................................. 8-2
Figure 8-2 Coprocessor clocking ............................................................................................... 8-2
Figure 8-3 LDC/STC cycle timing ............................................................................................... 8-4
Figure 8-4 MCR/MRC cycle timing ............................................................................................. 8-6
Figure 8-5 Interlocked MCR ....................................................................................................... 8-7
Figure 8-6 Latecanceled CDP .................................................................................................... 8-8
Figure 8-7 Privileged instructions ............................................................................................... 8-9
Figure 8-8 Busy waiting and interrupts ..................................................................................... 8-10
Figure 8-9 CPBURST and CPABORT timing ........................................................................... 8-12
Figure 8-10 Arrangement for connecting two coprocessors ...................................................... 8-14
Figure 12-1 Deassertion of STANDBYWFI after an IRQ interrupt ............................................. 12-2

List of Figures
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xiii
Figure 12-2 Logic for stopping ARM926EJ-S clock during wait for interrupt .............................. 12-3
Figure B-1 CP15 MRC and MCR bit pattern ............................................................................... B-2
Figure B-2 Rd format for selecting main TLB entry ..................................................................... B-6
Figure B-3 Rd format for accessing MVA tag of main or lockdown TLB entry ............................ B-7
Figure B-4 Rd format for accessing PA and AP data of main or lockdown TLB entry ................ B-8
Figure B-5 Write to the data RAM ............................................................................................. B-10
Figure B-6 Rd format for selecting lockdown TLB entry ........................................................... B-11
Figure B-7 Cache Debug Control Register format .................................................................... B-12
Figure B-8 MMU Debug Control Register format ...................................................................... B-14
Figure B-9 Memory Region Remap Register format ................................................................. B-15
Figure B-10 Memory region attribute resolution .......................................................................... B-17

List of Figures
xiv Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D

ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xv
Preface
This preface introduces the ARM926EJ-S Revision r0p4/r0p5 Technical Reference
Manual (TRM). It contains the following sections:
•About this manual on page xvi
•Feedback on page xxi.

Preface
xvi Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
About this manual
This is the Technical Reference Manual for the ARM926EJ-S processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This document has been written for experienced hardware and software engineers who
have previous experience of ARM products, and who wish to use an ARM926EJ-S
processor in their system design.
Using this manual
This document is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an overview of the ARM926EJ-S processor.
Chapter 2 Programmer’s Model
Read this chapter for details of the programmer’s model and
ARM926EJ-S registers.
Chapter 3 Memory Management Unit
Read this chapter for details of the Memory Management Unit (MMU)
and address translation process and how to use the CP15 register to
enable and disable the MMU.
Chapter 4 Caches and Write Buffer
Read this chapter for a description of the instruction cache, the data
cache, the write buffer, and the physical address tag RAM.
Chapter 5 Tightly-Coupled Memory Interface
Read this chapter for a description of the Tightly-Coupled Memory
(TCM) interface and how to use the CP15 region register to enable and
disable the caches. It includes examples on how various RAM types can
be connected.

Preface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xvii
Chapter 6 Bus Interface Unit
Read this chapter for a description of the Bus Interface Unit (BIU)
interface to AMBA.
Chapter 7 Noncachable Instruction Fetches
Read this chapter for a description of how speculative noncachable
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
Chapter 8 Coprocessor Interface
Read this chapter for a description of the coprocessor interface. The
chapter includes timing diagrams for coprocessor operations.
Chapter 9 Instruction Memory Barrier
Read this chapter for the Instruction Memory Barrier (IMB) description
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
Chapter 10 Embedded Trace Macrocell Support
Read this chapter to understand how Embedded Trace Macrocell (ETM)
is supported in the ARM926EJ-S processor.
Chapter 11 Debug Support
Read this chapter for a description of the debug interface and
EmbeddedICE-RT.
Chapter 12 Power Management
Read this chapter for a description of the power management facilities
provided by the ARM926EJ-S processor.
Appendix A Signal Descriptions
This appendix lists the ARM926EJ-S processor signals in functional
groups.
Appendix B CP15 Test and Debug Registers
Read this appendix for detailed information on the registers used for test
and debug.

Preface
xviii Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Conventions
This section describes the conventions that this manual uses:
•Typographical
•Timing diagrams
•Signal naming on page xix
•Numbering on page xx.
Typographical
This manual uses the following typographical conventions:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
ARM processor signal names. Also used for terms in descriptive
lists, where appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
•The Opcode_2 value selects which register is accessed.
Timing diagrams
This manual contains one or more timing diagrams. The figure named Key to timing
diagram conventions on page xix on page xix explains the components used in these
diagrams. When variations occur they have clear labels. You must not assume any
timing information that is not explicit in the diagrams.

Preface
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. xix
Key to timing diagram conventions
Signal naming
The level of an asserted signal depends on whether the signal is active-HIGH or
active-LOW. Asserted means HIGH for active-HIGH signals and LOW for active-LOW
signals:
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Prefix n Denotes active-LOW signals except in the case of AHB or Advanced
Peripheral Bus APB reset signals. These are named HRESETn and
PRESETn respectively.
Prefix DH Denotes data side AHB signals.
Prefix IH Denotes instruction side AHB signals.
Prefix DR Denotes data side TCM interface signals.
Prefix IR Denotes instruction side TCM interface signals.
Prefix ETM Denotes ETM interface signals.
Prefix DBG Denotes debug/JTAG signals.
Prefix CP Denotes coprocessor interface signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Preface
xx Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Numbering
<size in bits>’<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
•‘h7B4 is an unsized hexadecimal value.
•‘o7654 is an unsized octal value.
•8’d9 is an eight-bit wide decimal value of 9.
•8’h3F is an eight-bit wide hexadecimal value of
0x3 . This is
equivalent to b00111111.
•8’b1111 is an eight-bit wide binary value of b00001111.
Further reading
This section lists publications by ARM Limited, and by third parties.
ARM Limited periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and the ARM Limited
Frequently Asked Questions list.
ARM publications
This manual contains information that is specific to the ARM926EJ-S processor. Refer
to the following documents for other relevant information:
•ARM Architecture Reference Manual (ARM DDI 0100)
•ARM AMBA Specification (Rev 2.0) (ARM IHI 0001)
•ARM926EJ-S Implementation Guide (ARM DII 0015)
•ARM926EJ-S Test Chip Implementation Guide (ARM DXI 0131)
•ARM9EJ-S Technical Reference Manual (ARM DDI 0222)
•Multi-layer AHB Overview (ARM DVI 0045)
•ETM9 Technical Reference Manual (ARM DDI 0157).