ARM ARM7TDMI Product manual

Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C
ARM7TDMI
Revision: r4p1
Technical Reference Manual

ii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
ARM7TDMI
Technical Reference Manual
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks owned by ARM Limited. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Figure B-2 on page B-5 reprinted with permission IEEE Std 1149.1-1990. IEEE Standard Test Access Port
and Boundary-Scan Architecture Copyright 2001, by IEEE. The IEEE disclaims any responsibility or liability
resulting from the placement and use in the described manner.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Change
17 April 2001 A First release for ARM7TDMI Rev 4.
19 September 2001 B Maintenance update to correct minor documentation errors.
26 November 2004 C Maintenance update to correct minor documentation errors.

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. iii
Contents
ARM7TDMI Technical Reference Manual
Preface
About this manual ........................................................................................ xvi
Feedback ...................................................................................................... xx
Chapter 1 Introduction
1.1 About the ARM7TDMI core ......................................................................... 1-2
1.2 Architecture ................................................................................................. 1-5
1.3 Block, core, and functional diagrams .......................................................... 1-7
1.4 Instruction set summary ............................................................................ 1-11
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Processor operating states ......................................................................... 2-3
2.3 Memory formats .......................................................................................... 2-4
2.4 Data types ................................................................................................... 2-6
2.5 Operating modes ........................................................................................ 2-7
2.6 Registers ..................................................................................................... 2-8
2.7 The program status registers .................................................................... 2-13
2.8 Exceptions ................................................................................................ 2-16
2.9 Interrupt latencies ..................................................................................... 2-23
2.10 Reset ......................................................................................................... 2-24

Contents
iv Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Chapter 3 Memory Interface
3.1 About the memory interface ....................................................................... 3-2
3.2 Bus interface signals .................................................................................. 3-3
3.3 Bus cycle types .......................................................................................... 3-4
3.4 Addressing signals ................................................................................... 3-11
3.5 Address timing .......................................................................................... 3-14
3.6 Data timed signals .................................................................................... 3-17
3.7 Stretching access times ............................................................................ 3-29
3.8 Privileged mode access ............................................................................ 3-31
3.9 Reset sequence after power up ................................................................ 3-32
Chapter 4 Coprocessor Interface
4.1 About coprocessors .................................................................................... 4-2
4.2 Coprocessor interface signals .................................................................... 4-4
4.3 Pipeline following signals ............................................................................ 4-5
4.4 Coprocessor interface handshaking ........................................................... 4-6
4.5 Connecting coprocessors ......................................................................... 4-12
4.6 If you are not using an external coprocessor ............................................ 4-15
4.7 Undefined instructions .............................................................................. 4-16
4.8 Privileged instructions ............................................................................... 4-17
Chapter 5 Debug Interface
5.1 About the debug interface .......................................................................... 5-2
5.2 Debug systems ........................................................................................... 5-4
5.3 Debug interface signals .............................................................................. 5-7
5.4 ARM7TDMI core clock domains ............................................................... 5-11
5.5 Determining the core and system state .................................................... 5-13
5.6 About EmbeddedICE-RT logic ................................................................. 5-14
5.7 Disabling EmbeddedICE-RT .................................................................... 5-16
5.8 Debug Communications Channel ............................................................. 5-17
5.9 Monitor mode ............................................................................................ 5-21
Chapter 6 Instruction Cycle Timings
6.1 About the instruction cycle timing tables .................................................... 6-3
6.2 Branch and branch with link ....................................................................... 6-4
6.3 Thumb branch with link ............................................................................... 6-5
6.4 Branch and Exchange ................................................................................ 6-6
6.5 Data operations .......................................................................................... 6-7
6.6 Multiply and multiply accumulate ................................................................ 6-9
6.7 Load register ............................................................................................. 6-12
6.8 Store register ............................................................................................ 6-14
6.9 Load multiple registers ............................................................................. 6-15
6.10 Store multiple registers ............................................................................. 6-17
6.11 Data swap ................................................................................................. 6-18
6.12 Software interrupt and exception entry ..................................................... 6-19
6.13 Coprocessor data operation ..................................................................... 6-20

Contents
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. v
6.14 Coprocessor data transfer from memory to coprocessor .......................... 6-21
6.15 Coprocessor data transfer from coprocessor to memory .......................... 6-23
6.16 Coprocessor register transfer, load from coprocessor .............................. 6-25
6.17 Coprocessor register transfer, store to coprocessor ................................. 6-26
6.18 Undefined instructions and coprocessor absent ....................................... 6-27
6.19 Unexecuted instructions ............................................................................ 6-28
6.20 Instruction speed summary ....................................................................... 6-29
Chapter 7 AC and DC Parameters
7.1 Timing diagrams ......................................................................................... 7-2
7.2 Notes on AC parameters .......................................................................... 7-20
7.3 DC parameters .......................................................................................... 7-26
Appendix A Signal and Transistor Descriptions
A.1 Transistor dimensions ................................................................................. A-2
A.2 Signal types ................................................................................................ A-3
A.3 Signal descriptions ...................................................................................... A-4
Appendix B Debug in Depth
B.1 Scan chains and the JTAG interface .......................................................... B-3
B.2 Resetting the TAP controller ....................................................................... B-6
B.3 Pullup resistors ........................................................................................... B-7
B.4 Instruction register ...................................................................................... B-8
B.5 Public instructions ....................................................................................... B-9
B.6 Test data registers .................................................................................... B-14
B.7 The ARM7TDMI core clocks ..................................................................... B-22
B.8 Determining the core and system state in debug state ............................. B-24
B.9 Behavior of the program counter in debug state ....................................... B-30
B.10 Priorities and exceptions ........................................................................... B-33
B.11 Scan chain cell data .................................................................................. B-35
B.12 The watchpoint registers ........................................................................... B-42
B.13 Programming breakpoints ......................................................................... B-47
B.14 Programming watchpoints ......................................................................... B-50
B.15 The debug control register ........................................................................ B-51
B.16 The debug status register ......................................................................... B-54
B.17 The abort status register ........................................................................... B-56
B.18 Coupling breakpoints and watchpoints ..................................................... B-57
B.19 EmbeddedICE-RT timing .......................................................................... B-59
B.20 Programming restriction ............................................................................ B-60
Appendix C Differences Between Rev 3a and Rev 4
C.1 Summary of differences between Rev 3a and Rev 4 ................................. C-2
C.2 Detailed descriptions of differences between Rev 3a and Rev 4 ............... C-3
Glossary

Contents
vi Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. vii
List of Tables
ARM7TDMI Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Key to tables ........................................................................................................... 1-11
Table 1-2 ARM instruction summary ....................................................................................... 1-13
Table 1-3 Addressing modes .................................................................................................. 1-16
Table 1-4 Operand 2 ............................................................................................................... 1-18
Table 1-5 Fields ....................................................................................................................... 1-19
Table 1-6 Condition fields ........................................................................................................ 1-19
Table 1-7 Thumb instruction set summary .............................................................................. 1-22
Table 2-1 Register mode identifiers .......................................................................................... 2-7
Table 2-2 PSR mode bit values ............................................................................................... 2-15
Table 2-3 Exception entry and exit .......................................................................................... 2-16
Table 2-4 Exception vectors .................................................................................................... 2-21
Table 2-5 Exception priority order ........................................................................................... 2-22
Table 3-1 Bus cycle types ......................................................................................................... 3-5
Table 3-2 Burst types ................................................................................................................ 3-7
Table 3-3 Significant address bits ........................................................................................... 3-12
Table 3-4 nOPC ...................................................................................................................... 3-12
Table 3-5 nTRANS encoding .................................................................................................. 3-13
Table 3-6 Tristate control of processor outputs ....................................................................... 3-21
Table 3-7 Read accesses ........................................................................................................ 3-27
Table 3-8 Use of nM[4:0] to indicate current processor mode ................................................ 3-31
Table 4-1 Coprocessor availability ............................................................................................ 4-3
Table 4-2 Handshaking signals ................................................................................................. 4-6

List of Tables
viii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Table 4-3 Summary of coprocessor signaling ........................................................................... 4-7
Table 4-4 Mode identifier signal meanings, nTRANS ............................................................. 4-17
Table 5-1 DCC register access instructions ............................................................................ 5-18
Table 6-1 Branch instruction cycle operations .......................................................................... 6-4
Table 6-2 Thumb long branch with link ..................................................................................... 6-5
Table 6-3 Branch and exchange instruction cycle operations .................................................. 6-6
Table 6-4 Data operation instruction cycles .............................................................................. 6-8
Table 6-5 Multiply instruction cycle operations ......................................................................... 6-9
Table 6-6 Multiply accumulate instruction cycle operations ...................................................... 6-9
Table 6-7 Multiply long instruction cycle operations ............................................................... 6-10
Table 6-8 Multiply accumulate long instruction cycle operations ............................................ 6-10
Table 6-9 Load register instruction cycle operations .............................................................. 6-12
Table 6-10 MAS[1:0] signal encoding ....................................................................................... 6-13
Table 6-11 Store register instruction cycle operations .............................................................. 6-14
Table 6-12 Load multiple registers instruction cycle operations ............................................... 6-15
Table 6-13 Store multiple registers instruction cycle operations ............................................... 6-17
Table 6-14 Data swap instruction cycle operations .................................................................. 6-18
Table 6-15 Software Interrupt instruction cycle operations ....................................................... 6-19
Table 6-16 Coprocessor data operation instruction cycle operations ....................................... 6-20
Table 6-17 Coprocessor data transfer instruction cycle operations .......................................... 6-21
Table 6-18 coprocessor data transfer instruction cycle operations ........................................... 6-23
Table 6-19 Coprocessor register transfer, load from coprocessor ............................................ 6-25
Table 6-20 Coprocessor register transfer, store to coprocessor ............................................... 6-26
Table 6-21 Undefined instruction cycle operations ................................................................... 6-27
Table 6-22 Unexecuted instruction cycle operations ................................................................ 6-28
Table 6-23 ARM instruction speed summary ............................................................................ 6-29
Table 7-1 General timing parameters ....................................................................................... 7-4
Table 7-2 ABE address control timing parameters ................................................................... 7-5
Table 7-3 Bidirectional data write cycle timing parameters ....................................................... 7-6
Table 7-4 Bidirectional data read cycle timing parameters ....................................................... 7-6
Table 7-5 Data bus control timing parameters .......................................................................... 7-7
Table 7-6 Output 3-state time timing parameters ..................................................................... 7-8
Table 7-7 Unidirectional data write cycle timing parameters .................................................... 7-8
Table 7-8 Unidirectional data read cycle timing parameters ..................................................... 7-9
Table 7-9 Configuration pin timing parameters ....................................................................... 7-10
Table 7-10 Coprocessor timing parameters .............................................................................. 7-10
Table 7-11 Exception timing parameters .................................................................................. 7-11
Table 7-12 Synchronous interrupt timing parameters ............................................................... 7-12
Table 7-13 Debug timing parameters ....................................................................................... 7-13
Table 7-14 DCC output timing parameters ............................................................................... 7-13
Table 7-15 Breakpoint timing parameters ................................................................................. 7-14
Table 7-16 TCK and ECLK timing parameters ......................................................................... 7-15
Table 7-17 MCLK timing parameters ........................................................................................ 7-15
Table 7-18 Scan general timing parameters ............................................................................. 7-16
Table 7-19 Reset period timing parameters .............................................................................. 7-17
Table 7-20 Output enable and disable timing parameters ........................................................ 7-18
Table 7-21 ALE address control timing parameters .................................................................. 7-19

List of Tables
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. ix
Table 7-22 APE address control timing parameters .................................................................. 7-19
Table 7-23 AC timing parameters used in this chapter ............................................................. 7-20
Table A-1 Transistor gate dimensions of the output driver for a 0.18µm process ..................... A-2
Table A-2 Signal types ............................................................................................................... A-3
Table A-3 Signal descriptions .................................................................................................... A-4
Table B-1 Public instructions ..................................................................................................... B-9
Table B-2 Scan chain number allocation ................................................................................. B-16
Table B-3 Scan chain 0 cells ................................................................................................... B-35
Table B-4 Scan chain 1 cells ................................................................................................... B-40
Table B-5 Function and mapping of EmbeddedICE-RT registers ........................................... B-42
Table B-6 MAS[1:0] signal encoding ....................................................................................... B-45
Table B-7 Debug control register bit assignments ................................................................... B-51
Table B-8 Interrupt signal control ............................................................................................. B-52
Table B-9 Debug status register bit assignments .................................................................... B-54

List of Tables
xCopyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xi
List of Figures
ARM7TDMI Technical Reference Manual
Key to timing diagram conventions .......................................................................... xviii
Figure 1-1 Instruction pipeline .................................................................................................... 1-2
Figure 1-2 ARM7TDMI processor block diagram ....................................................................... 1-8
Figure 1-3 ARM7TDMI main processor logic ............................................................................. 1-9
Figure 1-4 ARM7TDMI processor functional diagram .............................................................. 1-10
Figure 1-5 ARM instruction set formats .................................................................................... 1-12
Figure 1-6 Thumb instruction set formats ................................................................................. 1-21
Figure 2-1 LIttle-endian addresses of bytes and halfwords within words ................................... 2-4
Figure 2-2 Big-endian addresses of bytes and halfwords within words ...................................... 2-5
Figure 2-3 Register organization in ARM state ........................................................................... 2-9
Figure 2-4 Register organization in Thumb state ..................................................................... 2-10
Figure 2-5 Mapping of Thumb-state registers onto ARM-state registers .................................. 2-11
Figure 2-6 Program status register format ................................................................................ 2-13
Figure 3-1 Simple memory cycle ................................................................................................ 3-4
Figure 3-2 Nonsequential memory cycle .................................................................................... 3-6
Figure 3-3 Sequential access cycles .......................................................................................... 3-7
Figure 3-4 Internal cycles ........................................................................................................... 3-8
Figure 3-5 Merged IS cycle ........................................................................................................ 3-9
Figure 3-6 Coprocessor register transfer cycles ....................................................................... 3-10
Figure 3-7 Memory cycle timing ............................................................................................... 3-10
Figure 3-8 Pipelined addresses ................................................................................................ 3-14
Figure 3-9 Depipelined addresses ............................................................................................ 3-15
Figure 3-10 SRAM compatible address timing ........................................................................... 3-16

List of Figures
xii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Figure 3-11 External bus arrangement ...................................................................................... 3-17
Figure 3-12 Bidirectional bus timing ........................................................................................... 3-18
Figure 3-13 Unidirectional bus timing ......................................................................................... 3-18
Figure 3-14 External connection of unidirectional buses ........................................................... 3-19
Figure 3-15 Data write bus cycle ................................................................................................ 3-20
Figure 3-16 Data bus control circuit ........................................................................................... 3-20
Figure 3-17 Test chip data bus circuit ........................................................................................ 3-23
Figure 3-18 Memory access ....................................................................................................... 3-25
Figure 3-19 Two-cycle memory access ..................................................................................... 3-26
Figure 3-20 Data replication ....................................................................................................... 3-28
Figure 3-21 Typical system timing ............................................................................................. 3-30
Figure 3-22 Reset sequence ...................................................................................................... 3-32
Figure 4-1 Coprocessor busy-wait sequence ............................................................................. 4-8
Figure 4-2 Coprocessor register transfer sequence ................................................................... 4-9
Figure 4-3 Coprocessor data operation sequence ................................................................... 4-10
Figure 4-4 Coprocessor load sequence ................................................................................... 4-11
Figure 4-5 Coprocessor connections with bidirectional bus ..................................................... 4-12
Figure 4-6 Coprocessor connections with unidirectional bus ................................................... 4-13
Figure 4-7 Connecting multiple coprocessors .......................................................................... 4-14
Figure 5-1 Typical debug system ............................................................................................... 5-4
Figure 5-2 ARM7TDMI block diagram ........................................................................................ 5-5
Figure 5-3 Debug state entry ..................................................................................................... 5-8
Figure 5-4 Clock switching on entry to debug state ................................................................. 5-11
Figure 5-5 ARM7 CPU main processor logic, TAP controller, and EmbeddedICE-RT logic .... 5-14
Figure 5-6 DCC control register format .................................................................................... 5-17
Figure 7-1 General timings ......................................................................................................... 7-3
Figure 7-2 ABE address control ................................................................................................. 7-5
Figure 7-3 Bidirectional data write cycle .................................................................................... 7-5
Figure 7-4 Bidirectional data read cycle ..................................................................................... 7-6
Figure 7-5 Data bus control ........................................................................................................ 7-7
Figure 7-6 Output 3-state time ................................................................................................... 7-8
Figure 7-7 Unidirectional data write cycle .................................................................................. 7-8
Figure 7-8 Unidirectional data read cycle ................................................................................... 7-9
Figure 7-9 Configuration pin timing ............................................................................................ 7-9
Figure 7-10 Coprocessor timing ................................................................................................. 7-10
Figure 7-11 Exception timing ..................................................................................................... 7-11
Figure 7-12 Synchronous interrupt timing .................................................................................. 7-12
Figure 7-13 Debug timing ........................................................................................................... 7-12
Figure 7-14 DCC output timing .................................................................................................. 7-13
Figure 7-15 Breakpoint timing .................................................................................................... 7-14
Figure 7-16 TCK and ECLK relationship .................................................................................... 7-14
Figure 7-17 MCLK timing ........................................................................................................... 7-15
Figure 7-18 Scan general timing ................................................................................................ 7-16
Figure 7-19 Reset period timing ................................................................................................. 7-17
Figure 7-20 Output enable and disable times due to HIGHZ TAP instruction ............................ 7-17
Figure 7-21 Output enable and disable times due to data scanning .......................................... 7-18
Figure 7-22 ALE address control ............................................................................................... 7-18

List of Figures
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xiii
Figure 7-23 APE address control ............................................................................................... 7-19
Figure B-1 ARM7TDMI core scan chain arrangements .............................................................. B-4
Figure B-2 Test access port controller state transitions .............................................................. B-5
Figure B-3 ID code register format ............................................................................................ B-14
Figure B-4 Output scan cell ...................................................................................................... B-17
Figure B-5 Clock switching on entry to debug state .................................................................. B-22
Figure B-6 Debug exit sequence .............................................................................................. B-28
Figure B-7 EmbeddedICE-RT block diagram ........................................................................... B-43
Figure B-8 Watchpoint control value and mask format ............................................................. B-45
Figure B-9 Debug control register format .................................................................................. B-51
Figure B-10 Debug status register format ................................................................................... B-54
Figure B-11 Debug control and status register structure ............................................................ B-55
Figure B-12 Debug abort status register ..................................................................................... B-56

List of Figures
xiv Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C

ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xv
Preface
This preface introduces the ARM7TDMI r4p1 Technical Reference Manual. It contains
the following sections:
•About this manual on page xvi
•Feedback on page xx.

Preface
xvi Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
About this manual
This is the ARM for the ARM7TDMI r4p1 processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this ARM,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This manual has been written for experienced hardware and software engineers who are
working with the ARM7TDMI processor.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the architecture.
Chapter 2 Programmer’s Model
Read this chapter for a description of the 32-bit ARM and 16-bit Thumb
instruction sets.
Chapter 3 Memory Interface
Read this chapter for a description of nonsequential, sequential, internal,
and coprocessor register transfer memory cycles.
Chapter 4 Coprocessor Interface
Read this chapter for details of theimplementation of the specialized
additional instructions for use with coprocessors and a description of the
interface.
Chapter 5 Debug Interface
Read this chapter for a description of the ARM7TDMI core hardware
extensions for advanced debugging to make it simpler to develop
application software, operating systems, and hardware.
Chapter 6 Instruction Cycle Timings
Read this chapter for a description of the instruction cycle timings.

Preface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xvii
Chapter 7 AC and DC Parameters
Read this chapter for a description of the AC and DC parameters, timing
diagrams, definitions, and operating data.
Appendix A Signal and Transistor Descriptions
Read this chapter for a description of the ARM7TDMI core signals.
Appendix B Debug in Depth
Read this chapter for further information on the debug interface and
EmbeddedICE-RT macrocell.
Appendix C Differences Between Rev 3a and Rev 4
Read this chapter for a description of the differences and enhancements
between Rev 3a and Rev 4 of the processor.
Glossary Read the glossary for a list of terms used in this manual.
Conventions
Conventions that this Thumb can use are described in:
•Typographical
•Timing diagrams on page xviii
•Signals on page xviii
•Numbering on page xix.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
signal names. Also used for terms in descriptive lists, where
appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.

Preface
xviii Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
< and > Angle brackets enclose replaceable terms for assembler syntax
where they appear in code or code fragments. They appear in
normal font in running text. For example:
•
MRC p15, 0 <Rd>, <CRn>, <CRm>, <Opcode_2>
• The Opcode_2 value selects which register is accessed.
Timing diagrams
The figure named Key to timing diagram conventions explains the components used in
timing diagrams. Variations, when they occur, have clear labels. You must not assume
any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value
within the shaded area at that time. The actual level is unimportant and does not affect
normal operation.
Key to timing diagram conventions
Signals
The signal conventions are:
Signal level The level of an asserted signal depends on whether the signal is
active-HIGH or active-LOW. Asserted means HIGH for
active-HIGH signals and LOW for active-LOW signals.
Prefix H Denotes Advanced High-performance Bus (AHB) signals.
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus

Preface
ARM DDI 0210C Copyright © 2001, 2004 ARM Limited. All rights reserved. xix
Prefix n Denotes active-LOW signals except in the case of AHB or
Advanced Peripheral Bus (APB) reset signals.
Prefix P Denotes APB signals.
Suffix n AHB HRESETn and APB PRESETDBGn reset signals.
Numbering
The numbering convention is:
<size in bits>'<base><number>
This is a Verilog method of abbreviating constant numbers. For example:
• 'h7B4 is an unsized hexadecimal value.
• 'o7654 is an unsized octal value.
• 8'd9 is an eight-bit wide decimal value of 9.
• 8'h3F is an eight-bit wide hexadecimal value of
0x3F . This is
equivalent to b00111111.
• 8'b1111 is an eight-bit wide binary value of b00001111.
Further reading
This section lists publications by ARM Limited, and by third parties.
ARM Limited periodically provides updates and corrections to its documentation. See
http://www.arm.com for current errata sheets, addenda, and the ARM Limited
Frequently Asked Questions list.
ARM publications
This document contains information that is specific to the ARM7TDMI core. See the
following documents for other relevant information:
•ARM Architecture Reference Manual (ARM DDI 0100).
Other publications
This section lists relevant documents published by third parties:
•IEEE Std. 1149.1-1990 Standard Test Access Port and Boundary-Scan
Architecture.

Preface
xx Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C
Feedback
ARM Limited welcomes feedback both on the ARM7TDMI r4p1 processor, and its
documentation.
Feedback on this product
If you have any comments or suggestions about this product, please contact your
supplier giving:
• the product name
• a concise explanation of your comments.
Feedback on this manual
If you have any comments about this manual, send email to
[email protected] giving:
• the title
• the number
• the relevant page number(s) to which your comments refer
• a concise explanation of your comments.
ARM Limited also welcomes general suggestions for additions and improvements.