ARM Cortex-M0 Product manual

Copyright © 2009 ARM Limited. All rights reserved.
ARM DDI 0432C (ID112415)
Cortex™-M0
Revision: r0p0
Technical Reference Manual

ii Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
Cortex-M0
Technical Reference Manual
Copyright © 2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM®Limited in the EU and
other countries, except as otherwise stated below in this proprietary notice. Other brands and names
mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Change history
Date Issue Confidentiality Change
19 March 2009 A Non-Confidential, Restricted Access First release for r0p0
27 July 2009 B Non-Confidential, Restricted Access Second release for r0p0
30 November 2009 C Non-Confidential Third release for r0p0

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Web Address
http://www.arm.com

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Contents
Cortex-M0 Technical Reference Manual
Preface
About this book ............................................................................................. xii
Feedback ...................................................................................................... xv
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Features ...................................................................................................... 1-3
1.3 Interfaces .................................................................................................... 1-4
1.4 Configurable options ................................................................................... 1-5
1.5 Product documentation, design flow and architecture ................................ 1-6
1.6 Product revisions ........................................................................................ 1-9
Chapter 2 Functional Description
2.1 About the functions ..................................................................................... 2-2
2.2 Interfaces .................................................................................................... 2-4
Chapter 3 Programmers Model
3.1 About the programmers model .................................................................... 3-2
3.2 Modes of operation and execution .............................................................. 3-3
3.3 Instruction set summary .............................................................................. 3-4
3.4 Memory model ............................................................................................ 3-9
3.5 Processor core registers summary ........................................................... 3-11

Contents
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3.6 Exceptions ................................................................................................ 3-12
Chapter 4 System Control
4.1 About system control .................................................................................. 4-2
4.2 System control register summary ............................................................... 4-3
Chapter 5 Nested Vectored Interrupt Controller
5.1 About the NVIC ........................................................................................... 5-2
5.2 NVIC register summary .............................................................................. 5-3
Chapter 6 Debug
6.1 About debug ............................................................................................... 6-2
6.2 Debug register summary ............................................................................ 6-9
Appendix A Revisions
Glossary

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List of Tables
Cortex-M0 Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Processor configurable options ................................................................................. 1-5
Table 3-1 Cortex-M0 instruction summary ................................................................................ 3-4
Table 3-2 Memory map usage .................................................................................................. 3-9
Table 3-3 Processor core register set summary ..................................................................... 3-11
Table 4-1 System control registers ............................................................................................ 4-3
Table 4-2 CPUID bit register assignments ................................................................................ 4-4
Table 5-1 NVIC registers ........................................................................................................... 5-3
Table 6-1 Cortex-M0 ROM table identification values ............................................................... 6-4
Table 6-2 Cortex-M0 ROM table components ........................................................................... 6-4
Table 6-3 SCS identification values .......................................................................................... 6-5
Table 6-4 DWT identification values .......................................................................................... 6-6
Table 6-5 BPU identification registers ....................................................................................... 6-7
Table 6-6 Debug registers summary ......................................................................................... 6-9
Table 6-7 BPU register summary .............................................................................................. 6-9
Table 6-8 DWT register summary ............................................................................................. 6-9
Table A-1 Issue A ...................................................................................................................... A-1
Table A-2 Differences between issue A and issue B ................................................................. A-1
Table A-3 Differences between issue B and issue C ................................................................. A-2

List of Tables
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List of Figures
Cortex-M0 Technical Reference Manual
Figure 2-1 Functional block diagram .......................................................................................... 2-2
Figure 4-1 CPUID bit register assignments ................................................................................ 4-4
Figure 6-1 CoreSight discovery .................................................................................................. 6-3

List of Figures
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Preface
This preface introduces the Cortex-M0 Technical Reference Manual. It contains the
following sections:
•About this book on page xii
•Feedback on page xv.

Preface
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About this book
This book is for the Cortex-M0 processor.
Product revision status
The rnpnidentifier indicates the revision status of the product described in this manual,
where:
rnIdentifies the major revision of the product.
pnIdentifies the minor revision or modification status of the product.
Intended audience
This book is written to help:
• system designers, system integrators, and verification engineers
• software developers who want to use the processor.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the processor and its features.
Chapter 2 Functional Description
Read this chapter for a functional overview of the processor and its
components.
Chapter 3 Programmers Model
Read this chapter for an overview of the processor register set, modes of
operation, and other information for programming the processor.
Chapter 4 System Control
Read this chapter for a summary of the system control registers and
programmers model.
Chapter 5 Nested Vectored Interrupt Controller
Read this chapter for a summary of the Nested Vectored Interrupt
Controller (NVIC) registers and programmers model.
Chapter 6 Debug
Read this chapter for a summary of the debug registers and programmers
model.

Preface
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Appendix A Revisions
Read this for a description of the technical changes between released
issues of this book.
Glossary Read this for definitions of terms used in this book.
Conventions
Conventions that this manual can use are described in:
•Typographical.
Typographical
The typographical conventions are:
italic Highlights important notes, introduces special terminology,
denotes internal cross-references, and citations.
bold Highlights interface elements, such as menu names. Denotes
signal names. Also used for terms in descriptive lists, where
appropriate.
monospace Denotes text that you can enter at the keyboard, such as
commands, file and program names, and source code.
monospace Denotes a permitted abbreviation for a command or option. You
can enter the underlined text instead of the full command or option
name.
monospace italic Denotes arguments to monospace text where the argument is to be
replaced by a specific value.
monospace bold Denotes language keywords when used outside example code.
Additional reading
This section lists publications by ARM and by third parties.
See
http://infocenter.arm.com for access to ARM documentation.
ARM publications
This book contains information that is specific to the processor. See the following
documents for other relevant information:
•ARMv6-M Architecture Reference Manual (ARM DDI 0419)

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•ARMv6-M Instruction Set Quick Reference Guide (ARM QRC 0011)
•ARM AMBA® 3 AHB-Lite Protocol Specification (ARM IHI 0033)
•ARM CoreSight™Components Technical Reference Manual (ARM DDI 0314)
•ARM Debug Interface v5, Architecture Specification (ARM IHI 0031)
Note
A Cortex-M0 implementation can include a Debug Access Port (DAP). This DAP
is defined in v5.1 of the ARM Debug interface specification, or in the errata
document to Issue A of the ARM Debug Interface v5 Architecture Specification.
•Application Binary Interface for the ARM Architecture (The Base Standard)
(IHI0036)
•Cortex-M0 Integration and Implementation Manual (ARM DII 0238)
•Cortex-M0 User Guide Reference Material (ARM DUI 0467A).
Other publications
This section lists relevant documents published by third parties:
• IEEE Standard, Test Access Port and Boundary-Scan Architecture specification
1149.1-1990 (JTAG).

Preface
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Feedback
ARM welcomes feedback on the processor and its documentation.
Feedback on the processor
If you have any comments or suggestions about this product, contact your supplier
giving:
• The product name.
• The product revision or version.
• An explanation with as much information as you can provide. Include symptoms
if appropriate.
Feedback on this manual
If you have any comments on this manual, send an email to
[email protected]. Give:
• the title
• the number, ARM DDI 0432C
• the page numbers to which your comments apply
• a concise explanation of your comments.
ARM also welcomes general suggestions for additions and improvements.

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Chapter 1
Introduction
This chapter introduces the Cortex-M0 processor and its features. It contains the
following sections:
•About the processor on page 1-2
•Features on page 1-3
•Interfaces on page 1-4
•Configurable options on page 1-5
•Product documentation, design flow and architecture on page 1-6
•Product revisions on page 1-9.

Introduction
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1.1 About the processor
The Cortex-M0 processor is a very low gate count, highly energy efficient processor
that is intended for microcontroller and deeply embedded applications that require an
area optimized processor.

Introduction
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1.2 Features
The processor features and benefits are:
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware multiplier
• deterministic, high-performance interrupt handling for time-critical applications
• Serial Wire Debug reduces the number of pins required for debugging.
For information about Cortex-M0 architectural compliance, see the Architecture and
protocol information on page 1-8.

Introduction
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1.3 Interfaces
The interfaces included in the processor for external access include:
• external AHB-Lite interface
•Debug Access Port (DAP).