ARM Cortex-M0 Product manual

Copyright © 2009 ARM Limited. All rights reserved.
ARM DDI 0432C (ID112415)
Cortex™-M0
Revision: r0p0
Technical Reference Manual

ii Copyright © 2009 ARM Limited. All rights reserved. ARM DDI 0432C
Non-Confidential ID112415
Cortex-M0
Technical Reference Manual
Copyright © 2009 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with ®or ™are registered trademarks or trademarks of ARM®Limited in the EU and
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mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to
license restrictions in accordance with the terms of the agreement entered into by ARM and the party that
ARM delivered this document to.
Unrestricted Access is an ARM internal classification.
Product Status
The information in this document is final, that is for a developed product.
Change history
Date Issue Confidentiality Change
19 March 2009 A Non-Confidential, Restricted Access First release for r0p0
27 July 2009 B Non-Confidential, Restricted Access Second release for r0p0
30 November 2009 C Non-Confidential Third release for r0p0

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Contents
Cortex-M0 Technical Reference Manual
Preface
About this book ............................................................................................. xii
Feedback ...................................................................................................... xv
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Features ...................................................................................................... 1-3
1.3 Interfaces .................................................................................................... 1-4
1.4 Configurable options ................................................................................... 1-5
1.5 Product documentation, design flow and architecture ................................ 1-6
1.6 Product revisions ........................................................................................ 1-9
Chapter 2 Functional Description
2.1 About the functions ..................................................................................... 2-2
2.2 Interfaces .................................................................................................... 2-4
Chapter 3 Programmers Model
3.1 About the programmers model .................................................................... 3-2
3.2 Modes of operation and execution .............................................................. 3-3
3.3 Instruction set summary .............................................................................. 3-4
3.4 Memory model ............................................................................................ 3-9
3.5 Processor core registers summary ........................................................... 3-11

Contents
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3.6 Exceptions ................................................................................................ 3-12
Chapter 4 System Control
4.1 About system control .................................................................................. 4-2
4.2 System control register summary ............................................................... 4-3
Chapter 5 Nested Vectored Interrupt Controller
5.1 About the NVIC ........................................................................................... 5-2
5.2 NVIC register summary .............................................................................. 5-3
Chapter 6 Debug
6.1 About debug ............................................................................................... 6-2
6.2 Debug register summary ............................................................................ 6-9
Appendix A Revisions
Glossary

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List of Tables
Cortex-M0 Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1 Processor configurable options ................................................................................. 1-5
Table 3-1 Cortex-M0 instruction summary ................................................................................ 3-4
Table 3-2 Memory map usage .................................................................................................. 3-9
Table 3-3 Processor core register set summary ..................................................................... 3-11
Table 4-1 System control registers ............................................................................................ 4-3
Table 4-2 CPUID bit register assignments ................................................................................ 4-4
Table 5-1 NVIC registers ........................................................................................................... 5-3
Table 6-1 Cortex-M0 ROM table identification values ............................................................... 6-4
Table 6-2 Cortex-M0 ROM table components ........................................................................... 6-4
Table 6-3 SCS identification values .......................................................................................... 6-5
Table 6-4 DWT identification values .......................................................................................... 6-6
Table 6-5 BPU identification registers ....................................................................................... 6-7
Table 6-6 Debug registers summary ......................................................................................... 6-9
Table 6-7 BPU register summary .............................................................................................. 6-9
Table 6-8 DWT register summary ............................................................................................. 6-9
Table A-1 Issue A ...................................................................................................................... A-1
Table A-2 Differences between issue A and issue B ................................................................. A-1
Table A-3 Differences between issue B and issue C ................................................................. A-2

List of Tables
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List of Figures
Cortex-M0 Technical Reference Manual
Figure 2-1 Functional block diagram .......................................................................................... 2-2
Figure 4-1 CPUID bit register assignments ................................................................................ 4-4
Figure 6-1 CoreSight discovery .................................................................................................. 6-3

List of Figures
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