ARM ARM9TDMI Product manual

Copyright © 1998, 1999 ARM Limited. All rights reserved.
ARM DDI0145B
ARM9TDMI
Technical Reference Manual

ii Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
ARM9TDMI
Technical Reference Manual
Copyright © 1998, 1999 ARM Limited. All rights reserved.
Release Information
Proprietary Notice
ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited.
The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, ARM7TDMI,
ARM9TDMI, TDMI and STRONG are trademarks of ARM Limited.
All other products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith. However,
all warranties implied or expressed, including but not limited to implied warranties of merchantability, or
fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
Confidentiality Status
This document is Open Access. This document has no restriction on distribution.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Description Issue Change
November 1998 A First release
July 1999 B Include Rev 2 and minor changes

ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. iii
Contents
ARM9TDMI Technical Reference Manual
Preface
About this document .................................................................................... viii
Further reading .............................................................................................. ix
Typographical conventions ............................................................................ x
Feedback ....................................................................................................... xi
Chapter 1 Introduction
1.1 About the ARM9TDMI ................................................................................. 1-2
1.2 Processor block diagram ............................................................................. 1-3
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Pipeline implementation and interlocks ....................................................... 2-4
Chapter 3 ARM9TDMI Processor Core Memory Interface
3.1 About the memory interface ........................................................................ 3-2
3.2 Instruction interface ..................................................................................... 3-4
3.3 Endian effects for instruction fetches .......................................................... 3-6
3.4 Data interface .............................................................................................. 3-7
3.5 Unidirectional/bidirectional mode interface ............................................... 3-10
3.6 Endian effects for data transfers ............................................................... 3-11
3.7 ARM9TDMI reset behavior ........................................................................ 3-12

Contents
iv Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
Chapter 4 ARM9TDMI Coprocessor Interface
4.1 About the coprocessor interface ................................................................. 4-2
4.2 LDC/STC .................................................................................................... 4-3
4.3 MCR/MRC .................................................................................................. 4-9
4.4 Interlocked MCR ....................................................................................... 4-11
4.5 CDP .......................................................................................................... 4-13
4.6 Privileged instructions ............................................................................... 4-15
4.7 Busy-waiting and interrupts ...................................................................... 4-16
4.8 Coprocessor 15 MCRs ............................................................................. 4-17
Chapter 5 Debug Support
5.1 About debug ............................................................................................... 5-2
5.2 Debug systems ........................................................................................... 5-3
5.3 Debug interface signals .............................................................................. 5-5
5.4 Scan chains and JTAG interface .............................................................. 5-11
5.5 The JTAG state machine .......................................................................... 5-12
5.6 Test data registers .................................................................................... 5-19
5.7 ARM9TDMI core clocks ............................................................................ 5-26
5.8 Clock switching during debug ................................................................... 5-27
5.9 Clock switching during test ....................................................................... 5-28
5.10 Determining the core state and system state ........................................... 5-29
5.11 Exit from debug state ................................................................................ 5-32
5.12 The behavior of the program counter during debug ................................. 5-35
5.13 EmbeddedICE macrocell .......................................................................... 5-38
5.14 Vector catching ......................................................................................... 5-46
5.15 Single stepping ......................................................................................... 5-47
5.16 Debug communications channel .............................................................. 5-48
Chapter 6 Test Issues
6.1 About testing ............................................................................................... 6-2
6.2 Scan chain 0 bit order ................................................................................. 6-3
Chapter 7 Instruction Cycle Summary and Interlocks
7.1 Instruction cycle times ................................................................................ 7-2
7.2 Interlocks .................................................................................................... 7-5
Chapter 8 ARM9TDMI AC Characteristics
8.1 ARM9TDMI timing diagrams ...................................................................... 8-2
8.2 ARM9TDMI timing parameters ................................................................. 8-14
Appendix A ARM9TDMI Signal Descriptions
A.1 Instruction memory interface signals .......................................................... A-2
A.2 Data memory interface signals ................................................................... A-3
A.3 Coprocessor interface signals .................................................................... A-5
A.4 JTAG and TAP controller signals ............................................................... A-6
A.5 Debug signals ............................................................................................. A-8

Contents
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. v
A.6 Miscellaneous signals ............................................................................... A-10

Contents
vi Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B

ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. vii
Preface
This preface introduces the ARM9TDMI (Revision 1 and subsequent revisions), which
is a member of the ARM family of general-purpose microprocessors. It contains the
following sections:
•About this document on page viii.
•Further reading on page ix.
•Typographical conventions on page x.
•Feedback on page xi.

Preface
viii Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
About this document
This document is a reference manual for the ARM9TDMI microprocessor. The
ARM9TDMI includes the following features:
• The option, selectable using the UNIEN signal, of using two unidirectional buses
DD[31:0] and DDIN[31:0], instead of a single bidirectional data bus. This is
described in Unidirectional/bidirectional mode interface on page 3-10.
• The value returned by the JTAG TAP controller IDCODE instruction is the value
present on the new TAPID[31:0] input bus. This allows the ID code to be easily
changed for each chip design.
Intended audience
This document has been written for experienced hardware and software engineers who
may or may not have experience of ARM products.

Preface
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. ix
Further reading
This section lists publications by ARM Limited, and by third parties.
ARM publications
ARM Architecture Reference Manual (ARM DDI 0100).
ARM7TDMI Data Sheet (ARM DDI 0029).
Other reading
IEEE Std. 1149.1 - 1990, Standard Test Access Port and Boundary-Scan Architecture.

Preface
xCopyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
Typographical conventions
The following typographical conventions are used in this document:
bold Highlights ARM processor signal names within text, and interface
elements such as menu names. May also be used for emphasis in
descriptive lists where appropriate.
italic Highlights special terminology, cross-references and citations.
typewriter Denotes text that may be entered at the keyboard, such as
commands, file names and program names, and source code.
typewriter Denotes a permitted abbreviation for a command or option. The
underlined text may be entered instead of the full command or
option name.
typewriter italic Denotes arguments to commands or functions where the argument
is to be replaced by a specific value.
typewriter bold Denotes language keywords when used outside example code.

Preface
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. xi
Feedback
ARM Limited welcomes feedback both on the ARM9TDMI, and on the
documentation.
Feedback on this manual
If you have any comments on this document, please send an email to
[email protected]
giving:
• the document title
• the document number
• the page number(s) to which your comments refer
• a concise explanation of your comments.
General suggestions for additions and improvements are also welcome.
Feedback on the ARM9TDMI
If you have any comments or suggestions about the ARM9TDMI, please contact your
supplier giving:
• the product name
• a concise explanation of your comments.

Preface
xii Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B

ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 1-1
Chapter 1
Introduction
This chapter introduces the ARM9TDMI (Revision 1 and subsequent revisions) and
shows its processor block diagram under the headings:
•About the ARM9TDMI on page 1-2.
•Processor block diagram on page 1-3.

Introduction
1-2 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
1.1 About the ARM9TDMI
The ARM9TDMI is a member of the ARM family of general-purpose microprocessors.
The ARM9TDMI is targeted at embedded control applications where high
performance, low die size and low power are all important. The ARM9TDMI supports
both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off
between high performance and high code density. The ARM9TDMI supports the ARM
debug architecture and includes logic to assist in both hardware and software debug.
The ARM9TDMI supports both bidirectional and unidirectional connection to external
memory systems. The ARM9TDMI also includes support for coprocessors.
The ARM9TDMI processor core is implemented using a five-stage pipeline consisting
of fetch, decode, execute, memory and write stages. The device has a Harvard
architecture, and the simple bus interface eases connection to either a cached or
SRAM-based memory system. A simple handshake protocol is provided for
coprocessor support.

Introduction
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 1-3
1.2 Processor block diagram
Figure 1-1 shows the ARM9TDMI processor block diagram.
Figure 1-1 ARM9TDMI processor block diagram
Instruction Decode and Datapath control logic
Instruction
Pipeline
Vectors
IAreg
PSR
B[..]
A[..]
Imm
PSRRD[..]
DINFWD[..]DIN[..]
RESULT[..]
+PC
REGBANK
MUL
BData[..]
AData[..]
IINC
DAreg
Shift
Cmux
IA[..]
IAScan
ID[..]
DAScan
SHIFTER
Amux
Bmux
C[..]
ALU
nALUOut[..]
Byte Rot
/ Sign Ex.
IDScan
Byte/
Word
Repl
DINC
DA[..]
DDIN[]
DDScan
DD[..]

Introduction
1-4 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B

ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 2-1
Chapter 2
Programmer’s Model
This chapter describes the programmer’s model for the ARM9TDMI under the
headings:
•About the programmer’s model on page 2-2.
•Pipeline implementation and interlocks on page 2-4.

Programmer’s Model
2-2 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
2.1 About the programmer’s model
The ARM9TDMI processor core implements ARM Architecture v4T, and so executes
the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The
programmer’s model is fully described in the ARM Architecture Reference Manual.
The ARM v4T architecture specifies a small number of implementation options. The
options selected in the ARM9TDMI implementation are listed in the table below. For
comparison, the options selected for the ARM7TDMI implementation are also shown:
The ARM9TDMI is code compatible with the ARM7TDMI, with two exceptions:
• The ARM9TDMI implements the Base Restored Data Abort model, which
significantly simplifies the software data abort handler.
• The ARM9TDMI fully implements the instruction set extension spaces added to
the ARM (32-bit) instruction set in Architecture v4 and v4T.
These differences are explained in more detail below.
2.1.1 Data abort model
The ARM9TDMI implements the Base Restored Data Abort Model, which differs from
the Base updated data abort model implemented by ARM7TDMI.
The difference in the Data Abort Model affects only a very small section of operating
system code, the data abort handler. It does not affect user code. With the Base Restored
Data Abort Model, when a data abort exception occurs during the execution of a
memory access instruction, the base register is always restored by the processor
hardware to the value the register contained before the instruction was executed. This
removes the need for the data abort handler to ‘unwind’ any base register update which
may have been specified by the aborted instruction.
The Base Restored Data Abort Model significantly simplifies the software data abort
handler.
Table 2-1 ARM9TDMI implementation option
Processor
core
ARM
architecture Data abort model Value stored by direct
STR, STRT, STM of PC
ARM7TDMI v4T Base updated Address of Inst + 12
ARM9TDMI v4T Base restored Address of Inst + 12

Programmer’s Model
ARM DDI0145B Copyright © 1998, 1999 ARM Limited. All rights reserved. 2-3
2.1.2 Instruction set extension spaces
All ARM processors implement the undefined instruction space as one of the entry
mechanisms for the Undefined Instruction Exception. That is, ARM instructions with
opcode[27:25] = 0b011 and opcode[4] = 1 are UNDEFINED on all ARM processors
including the ARM9TDMI and ARM7TDMI.
ARM Architecture v4 and v4T also introduced a number of instruction set extension
spaces to the ARM instruction set. These are:
• arithmetic instruction extension space
• control instruction extension space
• coprocessor instruction extension space
• load/store instruction extension space.
Instructions in these spaces are UNDEFINED (they cause an Undefined Instruction
Exception). The ARM9TDMI fully implements all the instruction set extension spaces
defined in ARM Architecture v4T as UNDEFINED instructions, allowing emulation of
future instruction set additions.

Programmer’s Model
2-4 Copyright © 1998, 1999 ARM Limited. All rights reserved. ARM DDI0145B
2.2 Pipeline implementation and interlocks
The ARM9TDMI implementation uses a five-stage pipeline design. These five stages
are:
• instruction fetch (F)
• instruction decode (D)
• execute (E)
• data memory access (M)
• register write (W).
ARM implementations are fully interlocked, so that software will function identically
across different implementations without concern for pipeline effects. Interlocks do
affect instruction execution times. For example, the following sequence suffers a single
cycle penalty due to a load-use interlock on register R0:
LDR R0, [R7]
ADD R5, R0, R1
For more details, see Chapter 7 Instruction Cycle Summary and Interlocks. Figure 2-1
on page 2-5 shows the timing of the pipeline, and the principal activity in each stage.