ARM ARM966E-S Use and care manual

Copyright © 2000 ARM Limited. All rights reserved.
ARM DDI 0186A
ARM966E-S
(Rev 1)
Technical Reference Manual

ii Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A
ARM966E-S
Technical Reference Manual
Copyright © 2000 ARM Limited. All rights reserved.
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Change history
Date Issue Change
31st July 2000 A First Release

ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. iii
Contents
ARM966E-S Technical Reference Manual
Preface
About this document ..................................................................................... xii
Further reading ............................................................................................. xv
Feedback ..................................................................................................... xvi
Chapter 1 Introduction
1.1 About the ARM966E-S ................................................................................ 1-2
1.2 Microprocessor block diagram .................................................................... 1-3
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 About the ARM9E-S programmer’s model .................................................. 2-3
2.3 ARM966E-S CP15 registers ....................................................................... 2-4
Chapter 3 Memory Map
3.1 About the ARM966E-S memory map .......................................................... 3-2
3.2 Tightly-coupled SRAM address space ........................................................ 3-3
3.3 Bufferable write address space ................................................................... 3-4
Chapter 4 Tightly-coupled SRAM
4.1 ARM966E-S SRAM requirements ............................................................... 4-2
4.2 SRAM stall cycles ....................................................................................... 4-3

Contents
iv Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A
4.3 Enabling the SRAM .................................................................................... 4-4
4.4 ARM966E-S SRAM wrapper ...................................................................... 4-7
Chapter 5 Direct Memory Access (DMA)
5.1 About the DMA interface ............................................................................ 5-2
5.2 Timing interface .......................................................................................... 5-5
5.3 DMAENABLE setup and hold cycles ........................................................ 5-11
5.4 Summary of signal behavior ..................................................................... 5-12
Chapter 6 Bus Interface Unit
6.1 About the BIU and write buffer ................................................................... 6-2
6.2 Write buffer operation ................................................................................. 6-3
6.3 AHB bus master interface ........................................................................... 6-7
6.4 AHB clocking ............................................................................................ 6-17
Chapter 7 Coprocessor Interface
7.1 About the coprocessor interface ................................................................. 7-2
7.2 LDC/STC .................................................................................................... 7-4
7.3 MCR/MRC .................................................................................................. 7-8
7.4 Interlocked MCR ......................................................................................... 7-9
7.5 CDP .......................................................................................................... 7-10
7.6 Privileged instructions ............................................................................... 7-11
7.7 Busy-waiting and interrupts ...................................................................... 7-12
Chapter 8 Debug Support
8.1 About the debug interface .......................................................................... 8-2
8.2 Debug systems ........................................................................................... 8-4
8.3 ARM966E-S scan chain 15 ........................................................................ 8-7
8.4 Debug interface signals .............................................................................. 8-9
8.5 ARM9E-S core clock domains .................................................................. 8-14
8.6 Determining the core and system state .................................................... 8-15
8.7 About the EmbeddedICE-RT .................................................................... 8-16
8.8 Disabling EmbeddedICE-RT .................................................................... 8-18
8.9 The debug communications channel ........................................................ 8-19
8.10 Monitor mode debug ................................................................................. 8-23
8.11 Debug additional reading .......................................................................... 8-25
Chapter 9 Embedded Trace Macrocell Interface
9.1 About the ETM interface ............................................................................. 9-2
9.2 Enabling the ETM interface ........................................................................ 9-3
9.3 ARM966E-S trace support features ............................................................ 9-4
Chapter 10 Test Support
10.1 About the ARM966E-S test methodology ................................................. 10-2
10.2 Scan insertion and ATPG ......................................................................... 10-3
10.3 BIST of tightly-coupled SRAM .................................................................. 10-4

Contents
ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. v
Chapter 11 Instruction cycle timings
11.1 Introduction to instruction cycle timings .................................................... 11-2
11.2 When stall cycles do not occur .................................................................. 11-3
11.3 Tightly-coupled SRAM cycles ................................................................... 11-4
11.4 AHB memory access cycles ...................................................................... 11-6
11.5 Interrupt latency calculation .................................................................... 11-10
Appendix A Signal Descriptions
A.1 Signal properties and requirements ............................................................ A-2
A.2 Clock interface signals ................................................................................ A-3
A.3 AHB signals ................................................................................................ A-4
A.4 Coprocessor interface signals ..................................................................... A-6
A.5 Debug signals ............................................................................................. A-8
A.6 Miscellaneous signals ............................................................................... A-11
A.7 ETM interface signals ............................................................................... A-12
A.8 INTEST wrapper signals ........................................................................... A-14
A.9 DMA Signals ............................................................................................. A-15
Appendix B AC Parameters
B.1 Timing diagrams ......................................................................................... B-2
B.2 AC timing parameter definitions ................................................................ B-12
Appendix C SRAM Stall Cycles
C.1 About SRAM stall cycles ............................................................................ C-2

Contents
vi Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A

ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. vii
List of Tables
ARM966E-S Technical Reference Manual
Change history .............................................................................................................. ii
Table 2-1 CP15 register map .................................................................................................... 2-4
Table 2-2 Register 0, ID code ................................................................................................... 2-5
Table 2-3 Register 1, Control register ....................................................................................... 2-5
Table 2-4 Register 13, Trace process identifier ........................................................................ 2-9
Table 2-5 Register 15, Test register map .................................................................................. 2-9
Table 2-6 Trace control register .............................................................................................. 2-10
Table 2-7 BIST control register ............................................................................................... 2-10
Table 2-8 BIST size encoding examples ................................................................................. 2-11
Table 4-1 I-SRAM stall cycles ................................................................................................... 4-3
Table 5-1 Simultaneous access behavior ................................................................................. 5-3
Table 5-2 DMAENABLE setup and hold cycles with respect to DMAnREQ ............................ 5-11
Table 5-3 DMA signal behavior ............................................................................................... 5-12
Table 7-1 Handshake encoding ................................................................................................ 7-6
Table 8-1 Scan chain 15 addressing mode bit order ................................................................. 8-7
Table 8-2 Mapping of scan chain 15 address field to CP15 registers ....................................... 8-7
Table 8-3 Coprocessor 14 register map .................................................................................. 8-19
Table 10-1 Instruction BIST address and general registers ...................................................... 10-5
Table 10-2 Data BIST address and general registers ............................................................... 10-6
Table 11-1 I-SRAM access ....................................................................................................... 11-4
Table 11-2 D-SRAM access ...................................................................................................... 11-5
Table 11-3 Key to tables ........................................................................................................... 11-7
Table 11-4 AHB read and unbuffered write transfer cycles ....................................................... 11-7

List of Tables
viii Copyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A
Table 11-5 AHB buffered writes cycles ..................................................................................... 11-9
Table 11-6 Interrupt latency cycle summary ........................................................................... 11-10
Table 11-7 Interrupt latency calculated examples .................................................................. 11-11
Table A-1 Clock interface signals .............................................................................................. A-3
Table A-2 AHB signals .............................................................................................................. A-4
Table A-3 Coprocessor interface signals .................................................................................. A-6
Table A-4 Debug signals ........................................................................................................... A-8
Table A-5 Miscellaneous signals ............................................................................................. A-11
Table A-6 ETM interface signals ............................................................................................. A-12
Table A-7 INTEST wrapper signals ......................................................................................... A-14
Table A-8 DMA signals ............................................................................................................ A-15
Table B-1 AC parameters ........................................................................................................ B-12

ARM DDI 0186A Copyright © 2000 ARM Limited. All rights reserved. ix
List of Figures
ARM966E-S Technical Reference Manual
Key to timing diagram conventions ............................................................................ xiv
Figure 1-1 ARM966E-S block diagram ....................................................................................... 1-3
Figure 3-1 ARM966E-S memory map ........................................................................................ 3-2
Figure 3-2 I-SRAM aliasing example .......................................................................................... 3-3
Figure 4-1 SRAM read cycle ...................................................................................................... 4-2
Figure 4-2 ARM966E-S SRAM hierarchy ................................................................................... 4-7
Figure 4-3 ONESEGX32 interface .............................................................................................. 4-8
Figure 4-4 FOURSEGX32 interface ........................................................................................... 4-9
Figure 4-5 FOURSEGX8 interface ........................................................................................... 4-11
Figure 5-1 Single-port RAM DMA interface ................................................................................ 5-3
Figure 5-2 Dual-port RAM DMA interface ................................................................................... 5-4
Figure 5-3 Single-port RAM DMA reads ..................................................................................... 5-5
Figure 5-4 Single-port RAM DMA writes .................................................................................... 5-7
Figure 5-5 Dual-port DMA reads ................................................................................................ 5-8
Figure 5-6 Dual-port RAM DMA writes ....................................................................................... 5-9
Figure 5-7 Mixed DMA read and write ...................................................................................... 5-10
Figure 6-1 Write buffer FIFO content example ........................................................................... 6-4
Figure 6-2 Sequential instruction fetches, after being granted the bus ...................................... 6-8
Figure 6-3 Sequential instruction fetches, no AHB data access required .................................. 6-9
Figure 6-4 Back-to-back LDR, no external instruction access .................................................... 6-9
Figure 6-5 Simultaneous instruction and data requests ........................................................... 6-10
Figure 6-6 Single STM, no instruction fetch ............................................................................. 6-11
Figure 6-7 Single LDM, no instruction access .......................................................................... 6-12

List of Figures
xCopyright © 2000 ARM Limited. All rights reserved. ARM DDI 0186A
Figure 6-8 Single STM, followed by sequential instruction fetch .............................................. 6-13
Figure 6-9 Single LDM followed by sequential instruction fetch ............................................... 6-14
Figure 6-10 Single STM, crossing a 1KB boundary ................................................................... 6-15
Figure 6-11 Single LDM, crossing a 1KB boundary ................................................................... 6-15
Figure 6-12 SWP instruction ...................................................................................................... 6-16
Figure 6-13 AHB 3:1 clocking example ...................................................................................... 6-17
Figure 6-14 ARM966E-S CLK to AHB HCLK sampling ............................................................. 6-19
Figure 7-1 LDC/STC cycle timing ............................................................................................... 7-4
Figure 7-2 MCR/MRC transfer timing with busy-wait ................................................................. 7-8
Figure 7-3 Interlocked MCR/MRC timing with busy-wait ............................................................ 7-9
Figure 7-4 Late cancelled CDP ................................................................................................ 7-10
Figure 7-5 Privileged instructions ............................................................................................. 7-11
Figure 7-6 Busy-waiting and interrupts .................................................................................... 7-12
Figure 8-1 Clock synchronization ............................................................................................... 8-3
Figure 8-2 Typical debug system ............................................................................................... 8-4
Figure 8-3 ARM9E-S block diagram .......................................................................................... 8-5
Figure 8-4 Breakpoint timing .................................................................................................... 8-10
Figure 8-5 Watchpoint entry with data processing instruction .................................................. 8-11
Figure 8-6 Watchpoint entry with branch ................................................................................. 8-12
Figure 8-7 The ARM9E-S, TAP controller and EmbeddedICE-RT .......................................... 8-16
Figure 8-8 Debug communications channel status register ..................................................... 8-20
Figure 8-9 Coprocessor 14 debug status register format ......................................................... 8-21
Figure 9-1 ARM966E-S ETM interface ...................................................................................... 9-2
Figure B-1 Clock, reset and AHB enable timing ......................................................................... B-2
Figure B-2 AHB bus request and grant related timing ................................................................ B-3
Figure B-3 AHB bus master timing ............................................................................................. B-4
Figure B-4 Coprocessor interface timing .................................................................................... B-5
Figure B-5 Debug interface timing .............................................................................................. B-6
Figure B-6 JTAG interface timing ............................................................................................... B-7
Figure B-7 DBGSDOUT to DBGTDO timing .............................................................................. B-8
Figure B-8 Exception and configuration timing ........................................................................... B-8
Figure B-9 INTEST wrapper timing ............................................................................................ B-9
Figure B-10 ETM interface timing ............................................................................................... B-10
Figure B-11 DMA interface timing .............................................................................................. B-11
Figure C-1 SRAM write cycle ...................................................................................................... C-2
Figure C-2 Read follows write ..................................................................................................... C-3
Figure C-3 Simultaneous instruction fetch, data read ................................................................. C-4
Figure C-4 Data read from I-SRAM ............................................................................................ C-5
Figure C-5 Data read followed by instruction fetch ..................................................................... C-6
Figure C-6 Simultaneous instruction fetch, data write ................................................................ C-7
Figure C-7 I-SRAM data write followed by instruction fetch ....................................................... C-8
Figure C-8 I-SRAM write followed by instruction fetch, data write .............................................. C-9
Figure C-9 I-SRAM write followed by instruction fetch, data read ............................................ C-10