ARM Cortex-A76 Core Product manual

Arm® Cortex®-A76 Core
Revision: r3p0
Technical Reference Manual
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.
100798_0300_00_en

Arm® Cortex®-A76 Core
Technical Reference Manual
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.
Release Information
Document History
Issue Date Confidentiality Change
0000-00 9 December 2016 Confidential First draft for r0p0
0000-01 26 May 2017 Confidential First release for r0p0
0100-00 20 October 2017 Confidential First release for r1p0
0200-00 13 April 2018 Confidential First release for r2p0
0300-00 27 July 2018 Non-Confidential First release for r3p0
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Arm® Cortex®-A76 Core
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Arm® Cortex®-A76 Core
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Contents
Arm® Cortex®-A76 Core Technical Reference Manual
Preface
About this book ..................................................... ..................................................... 16
Feedback .................................................................................................................... 21
Part A Functional description
Chapter A1 Introduction
A1.1 About the core ................................................... ................................................... A1-26
A1.2 Features ................................................................................................................ A1-27
A1.3 Implementation options ............................................ ............................................ A1-28
A1.4 Supported standards and specifications ............................... ............................... A1-29
A1.5 Test features .......................................................................................................... A1-30
A1.6 Design tasks .......................................................................................................... A1-31
A1.7 Product revisions ................................................. ................................................. A1-32
Chapter A2 Technical overview
A2.1 Components .......................................................................................................... A2-34
A2.2 Interfaces .............................................................................................................. A2-38
A2.3 About system control .............................................. .............................................. A2-39
A2.4 About the Generic Timer ........................................... ........................................... A2-40
Chapter A3 Clocks, resets, and input synchronization
A3.1 About clocks, resets, and input synchronization ......................... ......................... A3-42
A3.2 Asynchronous interface ............................................ ............................................ A3-43
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Chapter A4 Power management
A4.1 About power management .................................................................................... A4-46
A4.2 Voltage domains .................................................................................................... A4-47
A4.3 Power domains .................................................. .................................................. A4-48
A4.4 Architectural clock gating modes ..................................... ..................................... A4-50
A4.5 Power control ........................................................................................................ A4-52
A4.6 Core power modes ................................................................................................ A4-53
A4.7 Encoding for power modes ......................................... ......................................... A4-56
A4.8 Power domain states for power modes ................................ ................................ A4-57
A4.9 Power up and down sequences ............................................................................ A4-58
A4.10 Debug over powerdown ........................................................................................ A4-59
Chapter A5 Memory Management Unit
A5.1 About the MMU .................................................. .................................................. A5-62
A5.2 TLB organization ................................................. ................................................. A5-64
A5.3 TLB match process ............................................... ............................................... A5-65
A5.4 Translation table walks .......................................................................................... A5-66
A5.5 MMU memory accesses ........................................................................................ A5-67
A5.6 Specific behaviors on aborts and memory attributes ............................................ A5-68
Chapter A6 Level 1 memory system
A6.1 About the L1 memory system ....................................... ....................................... A6-72
A6.2 Cache behavior .................................................. .................................................. A6-73
A6.3 L1 instruction memory system ....................................... ....................................... A6-75
A6.4 L1 data memory system ........................................................................................ A6-77
A6.5 Data prefetching .................................................................................................... A6-79
A6.6 Direct access to internal memory .......................................................................... A6-80
Chapter A7 Level 2 memory system
A7.1 About the L2 memory system ....................................... ....................................... A7-98
A7.2 About the L2 cache ............................................... ............................................... A7-99
A7.3 Support for memory types ......................................... ......................................... A7-100
Chapter A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity ........................................................................................ A8-102
A8.2 Cache protection behavior ........................................ ........................................ A8-103
A8.3 Uncorrected errors and data poisoning ............................... ............................... A8-105
A8.4 RAS error types ................................................. ................................................. A8-106
A8.5 Error Synchronization Barrier ...................................... ...................................... A8-107
A8.6 Error recording .................................................................................................... A8-108
A8.7 Error injection ...................................................................................................... A8-109
Chapter A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface .................... .................... A9-112
A9.2 Bypassing the CPU interface ....................................... ....................................... A9-113
Chapter A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support ................... ................... A10-116
A10.2 Accessing the feature identification registers .................................................... A10-117
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Part B Register descriptions
Chapter B1 AArch32 system registers
B1.1 AArch32 architectural system register summary ........................ ........................ B1-122
Chapter B2 AArch64 system registers
B2.1 AArch64 registers ................................................................................................ B2-126
B2.2 AArch64 architectural system register summary ........................ ........................ B2-127
B2.3 AArch64 implementation defined register summary ..................... ..................... B2-134
B2.4 AArch64 registers by functional group ................................................................ B2-136
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 .......................... .......................... B2-144
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 .......................... .......................... B2-145
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 .......................... .......................... B2-147
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 ..................... ..................... B2-149
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 ..................... ..................... B2-150
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 ..................... ..................... B2-151
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 ..................... ..................... B2-152
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 ..................... ..................... B2-153
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 ..................... ..................... B2-154
B2.14 AIDR_EL1, Auxiliary ID Register, EL1 ................................................................ B2-155
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 .................... B2-156
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 .................... B2-157
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 .................... B2-158
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 ...................................................... B2-159
B2.19 CLIDR_EL1, Cache Level ID Register, EL1 ........................... ........................... B2-161
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 .................... B2-163
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 ........................................ B2-164
B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 ........................................ B2-165
B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 .................. .................. B2-166
B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1 ................................ B2-168
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 .............................................. B2-170
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 ................. ................. B2-172
B2.27 CPUPCR_EL3, CPU Private Control Register, EL3 ............................................ B2-180
B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3 .............................................. B2-182
B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3 ................... ................... B2-184
B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3 .................................... B2-186
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 ..................... ..................... B2-188
B2.32 CSSELR_EL1, Cache Size Selection Register, EL1 ..................... ..................... B2-190
B2.33 CTR_EL0, Cache Type Register, EL0 ................................ ................................ B2-191
B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0 ................................................ B2-193
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 ..................... ..................... B2-194
B2.36 ERRIDR_EL1, Error ID Register, EL1 ................................ ................................ B2-196
B2.37 ERRSELR_EL1, Error Record Select Register, EL1 .......................................... B2-197
B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 ........................ B2-198
B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 .......................... B2-199
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 .............................. B2-200
B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 .......... B2-201
B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 .......... B2-202
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register,
EL1 ...................................................................................................................... B2-203
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B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1 ...
............................................................................................................................. B2-204
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 . . B2-206
B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 .......... B2-207
B2.47 ESR_EL1, Exception Syndrome Register, EL1 ......................... ......................... B2-208
B2.48 ESR_EL2, Exception Syndrome Register, EL2 ......................... ......................... B2-209
B2.49 ESR_EL3, Exception Syndrome Register, EL3 ......................... ......................... B2-210
B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 ...................................... B2-211
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 ............................................ B2-212
B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 ............... ............... B2-214
B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 ............... ............... B2-215
B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1 ............ ............ B2-216
B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1 ............ ............ B2-218
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1 ..... ..... B2-219
B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1 ..... ..... B2-221
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 .... .... B2-222
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 .... .... B2-224
B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1 .... .... B2-226
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 .................... B2-227
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 .................... B2-229
B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1 ............... ............... B2-230
B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1 .................................. B2-231
B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 .................... B2-233
B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 .................... B2-235
B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 .................... B2-237
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 .................... B2-239
B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 .................... B2-241
B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 .................... B2-243
B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 .................... B2-245
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 .................. B2-246
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 .................. B2-248
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 .................. B2-250
B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 .................. B2-252
B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 .................. B2-254
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 .............. .............. B2-256
B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1 .............. .............. B2-258
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1 .............. .............. B2-260
B2.80 LORC_EL1, LORegion Control Register, EL1 .................................................... B2-261
B2.81 LORID_EL1, LORegion ID Register, EL1 ............................. ............................. B2-262
B2.82 LORN_EL1, LORegion Number Register, EL1 ......................... ......................... B2-263
B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3 ................. ................. B2-264
B2.84 MIDR_EL1, Main ID Register, EL1 ...................................................................... B2-266
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1 ...................... ...................... B2-267
B2.86 PAR_EL1, Physical Address Register, EL1 ............................ ............................ B2-269
B2.87 REVIDR_EL1, Revision ID Register, EL1 ............................. ............................. B2-270
B2.88 RMR_EL3, Reset Management Register ............................................................ B2-271
B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3 ................. ................. B2-272
B2.90 SCTLR_EL1, System Control Register, EL1 ........................... ........................... B2-273
B2.91 SCTLR_EL2, System Control Register, EL2 ........................... ........................... B2-275
B2.92 SCTLR_EL3, System Control Register, EL3 ........................... ........................... B2-276
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B2.93 TCR_EL1, Translation Control Register, EL1 ...................................................... B2-278
B2.94 TCR_EL2, Translation Control Register, EL2 ...................................................... B2-279
B2.95 TCR_EL3, Translation Control Register, EL3 ...................................................... B2-280
B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1 ........................................ B2-281
B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2 ........................................ B2-282
B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3 ................... ................... B2-283
B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 ........................................ B2-284
B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2 ........................................ B2-285
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 .............. .............. B2-286
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register ............... ............... B2-287
B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 .............................. B2-288
B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 .......... .......... B2-289
Chapter B3 Error system registers
B3.1 Error system register summary ..................................... ..................................... B3-292
B3.2 ERR0ADDR, Error Record Address Register .......................... .......................... B3-293
B3.3 ERR0CTLR, Error Record Control Register ........................................................ B3-294
B3.4 ERR0FR, Error Record Feature Register ............................. ............................. B3-296
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0 ........................................ B3-298
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 ........................................ B3-301
B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register ..... ..... B3-302
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register .................... B3-303
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register ........................ B3-305
B3.10 ERR0STATUS, Error Record Primary Status Register ................... ................... B3-307
Chapter B4 GIC registers
B4.1 CPU interface registers ........................................... ........................................... B4-313
B4.2 AArch64 physical GIC CPU interface system register summary ............ ............ B4-314
B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1 ....
............................................................................................................................. B4-315
B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1 B4-316
B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1 .................... B4-317
B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1 .................... B4-318
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1 ............... ............... B4-319
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3 ............... ............... B4-321
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1 ...... B4-323
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2 ... ... B4-324
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3 ... ... B4-326
B4.12 AArch64 virtual GIC CPU interface register summary ........................................ B4-328
B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0,
EL1 ...................................................................................................................... B4-329
B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0,
EL1 ...................................................................................................................... B4-330
B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1 .... .... B4-331
B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1 .... .... B4-332
B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 .................... B4-333
B4.18 AArch64 virtual interface control system register summary ................................ B4-335
B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2 ....
............................................................................................................................. B4-336
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B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2 ....
............................................................................................................................. B4-337
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2 ............ ............ B4-338
B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2 .... B4-341
B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2 ............. ............. B4-343
Chapter B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary .................................................................................. B5-346
B5.2 FPCR, Floating-point Control Register ................................................................ B5-347
B5.3 FPSR, Floating-point Status Register ................................ ................................ B5-349
B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1 ...................................... B5-351
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1 ...................................... B5-353
B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1 ...................................... B5-355
B5.7 AArch32 register summary .................................................................................. B5-357
B5.8 FPSCR, Floating-Point Status and Control Register ..................... ..................... B5-358
Part C Debug descriptions
Chapter C1 Debug
C1.1 About debug methods ............................................ ............................................ C1-366
C1.2 Debug register interfaces .................................................................................... C1-367
C1.3 Debug events ...................................................................................................... C1-369
C1.4 External debug interface .......................................... .......................................... C1-370
Chapter C2 Performance Monitor Unit
C2.1 About the PMU .................................................................................................... C2-372
C2.2 PMU functional description ........................................ ........................................ C2-373
C2.3 PMU events ........................................................................................................ C2-374
C2.4 PMU interrupts .................................................................................................... C2-383
C2.5 Exporting PMU events ........................................................................................ C2-384
Chapter C3 Activity Monitor Unit
C3.1 About the AMU .................................................................................................... C3-386
C3.2 Accessing the activity monitors ..................................... ..................................... C3-387
C3.3 AMU counters .................................................. .................................................. C3-388
C3.4 AMU events ........................................................................................................ C3-389
Chapter C4 Embedded Trace Macrocell
C4.1 About the ETM .................................................................................................... C4-392
C4.2 ETM trace unit generation options and resources .............................................. C4-393
C4.3 ETM trace unit functional description .................................................................. C4-395
C4.4 Resetting the ETM .............................................................................................. C4-396
C4.5 Programming and reading ETM trace unit registers ..................... ..................... C4-397
C4.6 ETM trace unit register interfaces ................................... ................................... C4-398
C4.7 Interaction with the PMU and Debug .................................................................. C4-399
Part D Debug registers
Chapter D1 AArch32 debug registers
D1.1 AArch32 debug register summary ................................... ................................... D1-404
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Chapter D2 AArch64 debug registers
D2.1 AArch64 debug register summary ................................... ................................... D2-406
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1 .............................. D2-408
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1 ............... ............... D2-411
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1 ............................ D2-412
Chapter D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary ............................ ............................ D3-416
D3.2 EDCIDR0, External Debug Component Identification Register 0 ........... ........... D3-420
D3.3 EDCIDR1, External Debug Component Identification Register 1 ........... ........... D3-421
D3.4 EDCIDR2, External Debug Component Identification Register 2 ........... ........... D3-422
D3.5 EDCIDR3, External Debug Component Identification Register 3 ........... ........... D3-423
D3.6 EDDEVID, External Debug Device ID Register 0 ....................... ....................... D3-424
D3.7 EDDEVID1, External Debug Device ID Register 1 ...................... ...................... D3-425
D3.8 EDPIDR0, External Debug Peripheral Identification Register 0 .......................... D3-426
D3.9 EDPIDR1, External Debug Peripheral Identification Register 1 .......................... D3-427
D3.10 EDPIDR2, External Debug Peripheral Identification Register 2 .......................... D3-428
D3.11 EDPIDR3, External Debug Peripheral Identification Register 3 .......................... D3-429
D3.12 EDPIDR4, External Debug Peripheral Identification Register 4 .......................... D3-430
D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7 .......... .......... D3-431
D3.14 EDRCR, External Debug Reserve Control Register ..................... ..................... D3-432
Chapter D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary .................................... .................................... D4-434
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0 ...... D4-436
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1 ...... D4-439
D4.4 PMCR, Performance Monitors Control Register ........................ ........................ D4-441
Chapter D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary .................................... .................................... D5-446
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0 ..
............................................................................................................................. D5-448
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0 ..
............................................................................................................................. D5-451
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0 ................ ................ D5-453
Chapter D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary ............................. ............................. D6-456
D6.2 PMCFGR, Performance Monitors Configuration Register .................................. D6-460
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0 ............ D6-461
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1 ............ D6-462
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2 ............ D6-463
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3 ............ D6-464
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0 ....... ....... D6-465
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1 ....... ....... D6-466
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2 ....... ....... D6-467
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3 ....... ....... D6-468
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4 ....... ....... D6-469
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 ..... ..... D6-470
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Chapter D7 PMU snapshot registers
D7.1 PMU snapshot register summary ........................................................................ D7-472
D7.2 PMPCSSR, Snapshot Program Counter Sample Register ................ ................ D7-473
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register ............. ............. D7-474
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register ............ ............ D7-475
D7.5 PMSSSR, PMU Snapshot Status Register ............................ ............................ D7-476
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register ................... ................... D7-477
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register ................... ................... D7-478
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 ............. ............. D7-479
D7.9 PMSSCR, PMU Snapshot Capture Register ...................................................... D7-480
Chapter D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary .................................... .................................... D8-482
D8.2 AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0 .. .. D8-483
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0 ..... ..... D8-484
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0 ............. ............. D8-485
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0 .......................... D8-487
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0 .......... .......... D8-489
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0 ........... ........... D8-490
Chapter D9 ETM registers
D9.1 ETM register summary ........................................................................................ D9-495
D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7 ........................ D9-499
D9.3 TRCACVRn, Address Comparator Value Registers 0-7 .................. .................. D9-501
D9.4 TRCAUTHSTATUS, Authentication Status Register ..................... ..................... D9-502
D9.5 TRCAUXCTLR, Auxiliary Control Register ............................ ............................ D9-503
D9.6 TRCBBCTLR, Branch Broadcast Control Register ...................... ...................... D9-505
D9.7 TRCCCCTLR, Cycle Count Control Register .......................... .......................... D9-506
D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0 ............. ............. D9-507
D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0 ................. ................. D9-508
D9.10 TRCCIDR0, ETM Component Identification Register 0 ...................................... D9-509
D9.11 TRCCIDR1, ETM Component Identification Register 1 ...................................... D9-510
D9.12 TRCCIDR2, ETM Component Identification Register 2 ...................................... D9-511
D9.13 TRCCIDR3, ETM Component Identification Register 3 ...................................... D9-512
D9.14 TRCCLAIMCLR, Claim Tag Clear Register ........................................................ D9-513
D9.15 TRCCLAIMSET, Claim Tag Set Register ............................................................ D9-514
D9.16 TRCCNTCTLR0, Counter Control Register 0 .......................... .......................... D9-515
D9.17 TRCCNTCTLR1, Counter Control Register 1 .......................... .......................... D9-517
D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1 ................. ................. D9-519
D9.19 TRCCNTVRn, Counter Value Registers 0-1 ........................... ........................... D9-520
D9.20 TRCCONFIGR, Trace Configuration Register .................................................... D9-521
D9.21 TRCDEVAFF0, Device Affinity Register 0 ............................. ............................. D9-524
D9.22 TRCDEVAFF1, Device Affinity Register 1 ............................. ............................. D9-526
D9.23 TRCDEVARCH, Device Architecture Register .................................................... D9-527
D9.24 TRCDEVID, Device ID Register .......................................................................... D9-528
D9.25 TRCDEVTYPE, Device Type Register ................................................................ D9-529
D9.26 TRCEVENTCTL0R, Event Control 0 Register .................................................... D9-530
D9.27 TRCEVENTCTL1R, Event Control 1 Register .................................................... D9-532
D9.28 TRCEXTINSELR, External Input Select Register ....................... ....................... D9-533
D9.29 TRCIDR0, ID Register 0 .......................................... .......................................... D9-534
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D9.30 TRCIDR1, ID Register 1 .......................................... .......................................... D9-536
D9.31 TRCIDR2, ID Register 2 .......................................... .......................................... D9-537
D9.32 TRCIDR3, ID Register 3 .......................................... .......................................... D9-539
D9.33 TRCIDR4, ID Register 4 .......................................... .......................................... D9-541
D9.34 TRCIDR5, ID Register 5 .......................................... .......................................... D9-543
D9.35 TRCIDR8, ID Register 8 .......................................... .......................................... D9-545
D9.36 TRCIDR9, ID Register 9 .......................................... .......................................... D9-546
D9.37 TRCIDR10, ID Register 10 ........................................ ........................................ D9-547
D9.38 TRCIDR11, ID Register 11 .................................................................................. D9-548
D9.39 TRCIDR12, ID Register 12 ........................................ ........................................ D9-549
D9.40 TRCIDR13, ID Register 13 ........................................ ........................................ D9-550
D9.41 TRCIMSPEC0, Implementation Specific Register 0 ..................... ..................... D9-551
D9.42 TRCITATBIDR, Integration ATB Identification Register ................... ................... D9-552
D9.43 TRCITCTRL, Integration Mode Control Register ................................................ D9-553
D9.44 TRCITIATBINR, Integration Instruction ATB In Register .................. .................. D9-554
D9.45 TRCITIATBOUTR, Integration Instruction ATB Out Register .............................. D9-555
D9.46 TRCITIDATAR, Integration Instruction ATB Data Register ................ ................ D9-556
D9.47 TRCLAR, Software Lock Access Register .......................................................... D9-557
D9.48 TRCLSR, Software Lock Status Register ............................. ............................. D9-558
D9.49 TRCCNTVRn, Counter Value Registers 0-1 ........................... ........................... D9-559
D9.50 TRCOSLAR, OS Lock Access Register .............................................................. D9-560
D9.51 TRCOSLSR, OS Lock Status Register ............................... ............................... D9-561
D9.52 TRCPDCR, Power Down Control Register ............................ ............................ D9-562
D9.53 TRCPDSR, Power Down Status Register ............................. ............................. D9-563
D9.54 TRCPIDR0, ETM Peripheral Identification Register 0 .................... .................... D9-564
D9.55 TRCPIDR1, ETM Peripheral Identification Register 1 .................... .................... D9-565
D9.56 TRCPIDR2, ETM Peripheral Identification Register 2 .................... .................... D9-566
D9.57 TRCPIDR3, ETM Peripheral Identification Register 3 .................... .................... D9-567
D9.58 TRCPIDR4, ETM Peripheral Identification Register 4 .................... .................... D9-568
D9.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7 ................. ................. D9-569
D9.60 TRCPRGCTLR, Programming Control Register ........................ ........................ D9-570
D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16 .............................. D9-571
D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2 ......... ......... D9-572
D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register ...................................... D9-574
D9.64 TRCSEQSTR, Sequencer State Register ............................. ............................. D9-575
D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0 ............... ............... D9-576
D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0 ................ ................ D9-577
D9.67 TRCSTALLCTLR, Stall Control Register .............................. .............................. D9-578
D9.68 TRCSTATR, Status Register ....................................... ....................................... D9-579
D9.69 TRCSYNCPR, Synchronization Period Register ................................................ D9-580
D9.70 TRCTRACEIDR, Trace ID Register .................................................................... D9-581
D9.71 TRCTSCTLR, Global Timestamp Control Register ...................... ...................... D9-582
D9.72 TRCVICTLR, ViewInst Main Control Register .................................................... D9-583
D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register ............... ............... D9-585
D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register ................... ................... D9-586
D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0 ........................................ D9-587
D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0 . . D9-588
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Part E Appendices
Appendix A Cortex®-A76 Core AArch32 unpredictable behaviors
A.1 Use of R15 by Instruction ............................................................................ Appx-A-592
A.2 Load/Store accesses crossing page boundaries .................... .................... Appx-A-593
A.3 Armv8 Debug UNPREDICTABLE behaviors ....................... ....................... Appx-A-594
A.4 Other UNPREDICTABLE behaviors ............................................................ Appx-A-597
Appendix B Revisions
B.1 Revisions .................................................. .................................................. Appx-B-600
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Preface
This preface introduces the Arm® Cortex®-A76 Core Technical Reference Manual.
It contains the following:
•About this book on page 16.
•Feedback on page 21.
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About this book
This Technical Reference Manual is for the Cortex®-A76 core. It provides reference documentation and
contains programming details for registers. It also describes the memory system, the caches, the
interrupts, and the debug features.
Product revision status
The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2,
where:
rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.
Intended audience
This manual is for system designers, system integrators, and programmers who are designing or
programming a System-on-Chip (SoC) that uses an Arm core.
Using this book
This book is organized into the following chapters:
Part A Functional description
This part describes the main functionality of the Cortex-A76 core.
Chapter A1 Introduction
This chapter provides an overview of the Cortex-A76 core and its features.
Chapter A2 Technical overview
This chapter describes the structure of the Cortex-A76 core.
Chapter A3 Clocks, resets, and input synchronization
This chapter describes the clocks, resets, and input synchronization of the Cortex-A76 core.
Chapter A4 Power management
This chapter describes the power domains and the power modes in the Cortex-A76 core.
Chapter A5 Memory Management Unit
This chapter describes the Memory Management Unit (MMU) of the Cortex-A76 core.
Chapter A6 Level 1 memory system
This chapter describes the L1 instruction cache and data cache that make up the L1 memory
system.
Chapter A7 Level 2 memory system
This chapter describes the L2 memory system.
Chapter A8 Reliability, Availability, and Serviceability (RAS)
This chapter describes the RAS features implemented in the Cortex-A76 core.
Chapter A9 Generic Interrupt Controller CPU interface
This chapter describes the Cortex-A76 core implementation of the Arm Generic Interrupt
Controller (GIC) CPU interface.
Chapter A10 Advanced SIMD and floating-point support
This chapter describes the Advanced SIMD and floating-point features and registers in the
Cortex-A76 core. The unit in charge of handling the Advanced SIMD and floating-point features
is also referred to as data engine in this manual.
Part B Register descriptions
This part describes the non-debug registers of the Cortex-A76 core.
Preface
Product revision status
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Chapter B1 AArch32 system registers
This chapter describes the system registers in the AArch32 state.
Chapter B2 AArch64 system registers
This chapter describes the system registers in the AArch64 state.
Chapter B3 Error system registers
This chapter describes the error registers accessed by the AArch64 error registers.
Chapter B4 GIC registers
This chapter describes the GIC registers.
Chapter B5 Advanced SIMD and floating-point registers
This chapter describes the Advanced SIMD and floating-point registers.
Part C Debug descriptions
This part describes the debug functionality of the Cortex-A76 core.
Chapter C1 Debug
This chapter describes the Cortex-A76 core debug registers and shows examples of how to use
them.
Chapter C2 Performance Monitor Unit
This chapter describes the Performance Monitor Unit (PMU) and the registers that it uses.
Chapter C3 Activity Monitor Unit
This chapter describes the Activity Monitor Unit (AMU).
Chapter C4 Embedded Trace Macrocell
This chapter describes the ETM for the Cortex-A76 core.
Part D Debug registers
This part describes the debug registers of the Cortex-A76 core.
Chapter D1 AArch32 debug registers
This chapter describes the debug registers in the AArch32 Execution state and shows examples of
how to use them.
Chapter D2 AArch64 debug registers
This chapter describes the debug registers in the AArch64 Execution state and shows examples of
how to use them.
Chapter D3 Memory-mapped debug registers
This chapter describes the memory-mapped debug registers and shows examples of how to use
them.
Chapter D4 AArch32 PMU registers
This chapter describes the AArch32 PMU registers and shows examples of how to use them.
Chapter D5 AArch64 PMU registers
This chapter describes the AArch64 PMU registers and shows examples of how to use them.
Chapter D6 Memory-mapped PMU registers
This chapter describes the memory-mapped PMU registers and shows examples of how to use
them.
Chapter D7 PMU snapshot registers
PMU snapshot registers are an IMPLEMENTATION DEFINED extension to an Armv8-A compliant PMU
to support an external core monitor that connects to a system profiler.
Chapter D8 AArch64 AMU registers
This chapter describes the AArch64 AMU registers and shows examples of how to use them.
Chapter D9 ETM registers
This chapter describes the ETM registers.
Preface
Using this book
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Part E Appendices
This part describes the appendices of the Cortex-A76 core.
Appendix A Cortex®-A76 Core AArch32 unpredictable behaviors
This appendix describes the cases in which the Cortex-A76 core implementation diverges from
the preferred behavior described in Armv8 AArch32 UNPREDICTABLE behaviors.
Appendix B Revisions
This appendix describes the technical changes between released issues of this book.
Glossary
The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those
terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning
differs from the generally accepted meaning.
See the Arm® Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Preface
Using this book
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Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
Figure 1 Key to timing diagram conventions
Signals
The signal conventions are:
Signal level
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
Lowercase n
At the start or end of a signal name denotes an active-LOW signal.
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Arm publications
•Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile (DDI 0487).
•Arm® Cortex®-A76 Core Cryptographic Extension Technical Reference Manual (100801).
•Arm® Cortex®-A76 Core Configuration and Sign-off Guide (100799).
•Arm® Cortex®-A76 Core Integration Manual (100800).
•Arm® DynamIQ™ Shared Unit Integration Manual (100455).
•Arm® DynamIQ™ Shared Unit Technical Reference Manual (100453).
•Arm® DynamIQ™ Shared Unit Configuration and Sign-off Guide (100454).
•Arm® CoreSight™ ELA-500 Embedded Logic Analyzer Technical Reference Manual
(100127).
•AMBA® AXI™ and ACE™ Protocol Specification AXI3™, AXI4™, and AXI4-Lite™, ACE and
ACE-Lite™ (IHI 0022).
•AMBA® APB Protocol Version 2.0 Specification (IHI 0024).
•Arm® AMBA® 5 CHI Architecture Specification (IHI 0050).
•Arm® CoreSight™ Architecture Specification v3.0 (IHI 0029).
•Arm® Debug Interface Architecture Specification, ADIv5.0 to ADIv5.2 (IHI 0031).
•AMBA® 4 ATB Protocol Specification (IHI 0032).
•Arm® Generic Interrupt Controller Architecture Specification (IHI 0069).
•Arm® Embedded Trace Macrocell Architecture Specification ETMv4 (IHI 0064).
•AMBA® Low Power Interface Specification Arm® Q-Channel and P-Channel Interfaces (IHI
0068).
•Arm® Reliability, Availability, and Serviceability (RAS) Specification, Armv8, for the Armv8-
A architecture profile (DDI 0587A).
Preface
Additional reading
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Other publications
•ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic.
Note
Arm floating-point terminology is largely based on the earlier ANSI/IEEE Std 754-1985
issue of the standard. See the Arm® Architecture Reference Manual Armv8, for Armv8-A
architecture profile for more information.
Preface
Additional reading
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