
DAC1 USB
Instruction Manual Revision D Page 18
UltraLock™ Clock System
Accurate 24-bit audio conversion requires a
very low-jitter conversion clock. Jitter can
very easily turn a 24-bit converter into a 16-
bit converter (or worse). There is no point in
buying a 24-bit converter if clock jitter has
not been adequately addressed.
Jitter is present on every digital audio
interface. This type of jitter is known as
‘interface jitter’ and it is present even in the
most carefully designed audio systems.
Interface jitter accumulates as digital signals
travel down a cable and from one digital
device to the next. If we measure interface
jitter in a typical system we will find that it is
10 to 10,000 times higher than the maximum
allowable level for accurate 24-bit conversion.
Fortunately, interface jitter has absolutely no
effect on the audio unless it influences the
conversion clock in an analog-to-digital
converter (A/D) or in a digital-to-analog
converter (D/A).
Many converters use a single-stage Phase
Lock Loop (PLL) circuit to derive their
conversion clocks from AES/EBU, Wordclock,
or Superclock reference signals. Single-stage
PLL circuits provide some jitter attenuation
above 5 kHz but none below 5 kHz.
Unfortunately, digital audio signals often have
their strongest jitter components at 2 kHz.
Consequently, these converters can achieve
their rated performance only when driven
from very low jitter sources and through very
short cables. It is highly unlikely that any
converter with a single-stage PLL can achieve
better than 16 bits of performance in a typical
installation. Specified performance may be
severely degraded in most installations.
Better converters usually use a two-stage PLL
circuit to filter out more of the interface jitter.
In theory, a two-stage PLL can remove
enough of the jitter to achieve accurate 24-bit
conversion (and some do). However, not all
two-stage PLL circuits are created equal.
Many two-stage PLL’s do not remove enough
of the low-frequency jitter. In addition, two-
stage PLL circuits often require several
seconds to lock to an incoming signal.
Finally, a two-stage PLL may fail to lock when
jitter is too high, or when the reference
sample frequency has drifted.
UltraLock™ converters exceed the jitter
performance of two-stage PLL converters, and
are free from the slow-lock and no-lock
problems that can plague two-stage PLL
designs. UltraLock™ converters have
extremely high immunity to interface jitter
under all operating conditions. No jitter-
induced artifacts can be detected using an
Audio Precision System 2 Cascade test set.
Measurement limits include detection of
artifacts as low as –140 dBFS, application of
jitter amplitudes as high as 12.75 UI, and
application of jitter over a frequency range of
2 Hz to 200 kHz. Any AES/EBU signal that
can be decoded by the AES/EBU receiver will
be reproduced without the addition of any
measurable jitter artifacts.
The DAC1 USB, DAC1, DAC-104, ADC1 and
the ADC-104 employ Benchmark’s
UltraLock™ technology to eliminate jitter-
induced performance problems. UltraLock™
technology isolates the conversion clock from
the digital audio interface clock. Jitter on a
D/A digital audio input, or an A/D reference
input can never have any measurable effect
on the conversion clock of an UltraLock™
converter. In an UltraLock™ converter, the
conversion clock is never phase-locked to a
reference clock. Instead the converter
oversampling-ratio is varied with extremely
high precision to achieve the proper phase
relationship to the reference clock. The clock
isolation of the UltraLock™ system insures
that interface jitter can never degrade the
quality of the audio conversion. Specified
performance is consistent and repeatable in
any installation with cables of any quality
level!
How does conversion clock jitter
degrade converter performance?
Problem #1: Jitter phase modulates the
audio signal. This modulation creates
sidebands (unwanted tones) above and below
every tone in the audio signal. Worse yet,
these sidebands are often widely separated
from the tones in the original signal.