Cypress CY3650 User manual

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CY3650
USB Development System
User’s Guide
Version 2.4
June 30, 1999

DOCUMENT HISTORY PAGE
Document Title: USB Development System User’ s Guide
Document Number:
REV ECN NO. ISSUE
DATE
ORIG.
OF
CHANGE
DESCRIPTION OF CHANGE
0.9 –Preliminary Release
1.0 –9/27/96 TIW Update switches, I/O, misc., 24pin pkg
1.1 –11/20/96 JDW Update switches, pin list, suspend
1.2 –
2.0 –6/17/97 TEN Modified to incorporate CY7C6341x and
CY7C6351x
2.1 –7/30/97 TEN Changed J1 odd pins to even and even to odd.
Expanded explanation of serial buffer size
2.2 –12/16/97 TEN Fixed Table 7, J2 Pin 30 changed from
“ MR_” (duplicate) to “ MW_”
2.3 –2/27/98 TEN Added TOC plus a number of changes and
corrections
2.4 -6/30/99 TEN Changed Cypress Logo to be part of file

Ver 2.4 – i –
CY3650 USB Development System User’ s Guide
1. Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Hardware Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.1. Power Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2. Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3. Ribbon Cable connectors J1 and J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.4. PC Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.5. Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.1. Differences between the chip and the development board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2. Firmware ROM vs. RAM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.3. PC debug interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.4. I/O Port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5.5. Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.6. Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.7. USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1. Target Chip and Connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2. J2 - Microcontroller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.3. J3 - RS232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

– ii – Ver 2.4
CY3650 USB Development System User’ s Guide

Ver 2.4 – 1–
CY3650 USB Development System User’ s Guide
1. Overview
The Cypress USB Development System is a powerful tool to assist development of user hardware and firmware
with emulated Cypress USB ICs. In the full development system environment (Figure 1), a PC-based interface
facilitates debugging through break-traps, single stepping, and display/modification of registers and data RAM. In
this mode, firmware can be implemented in on-board EPROM, or downloaded to program RAM. The RAM option
provides a quick and easy method for testing firmware revisions.
Stand-alone mode (Figure 2) allows portable system operation. In this case, user firmware is loaded in EPROM,
and only power need be applied to produce a fully operating emulated USB chip.
Figure 3 shows a block diagram of the development board, illustrating the major system components and the user
interfaces. The board supports a family of Cypress USB ICs, with varying amounts of on-chip EPROM, RAM, I/O,
PC
Development
Board
Logic Analyzer
Target System
Wall Bug
USB
RS-232
J1J2
Figure 1. Typical USB Development Environment
Development
Board
Target System
Wall Bug
Figure 2. Stand-alone Environment
J2 J1

– 2– Ver 2.4
CY3650 USB Development System User’ s Guide
etc. Consult the individual device specification for details on the IC being emulated.
2. Kit Contents
The USB Development System contains the following items:
• USB development board
• Wall transformer power supply (“ Wall bug”)
• USB cable
• RS-232 9-pin to 9-pin cable
• 9-pin to 25-pin adapter for RS-232 cable
• Quick Start User’ s Guide (yellow)
• This user’ s guide
• USB Development System Software Guide
• CYASM Assembler User’s Guide
• PC interface software
• CYASM Assembler software
• Registration Card
3. Hardware Installation
This section describes the hardware installation steps necessary for operating the development board. These
include supplying power to the board, connecting to a PC, and configuring on-board switches. Refer to Figure 4 for
locations of components mentioned in this document; Figure 1 shows typical connections for the system develop-
ment environment.
To/From
PC
Serial
Interface
Engine
CS
CS
USB
D+
D−
J6
J13
Power
In
+5V
Reset
Switch
Options
Program RAM
8k x 8
Program ROM
8k x 8
Data RAM
256 x 8
UART
USB
Transceiver
Microcontroller
S2
Voltage
Regulators +3.3V
Port
Transceivers
Port0
Port1
Port2
Port3
Figure 3. Development Board Functional Block Diagram

Ver 2.4 – 3–
CY3650 USB Development System User’ s Guide
3.1. Power Connection
The development board is designed to be powered by the enclosed wall transformer. Connect the transformer to a
110V AC source, and to power jack J13 on the board. +5V and +3.3V are generated by regulators on the board.
The green LED will light when power is applied.
3.2. Jumpers
Jumper JP1, at the right side of Figure 4, applies VDD (+5V) to pin 57 of connector J1. Without JP1, no connection
to VDD occurs on J1. The board is shipped with the jumper installed.
3.3. Ribbon Cable connectors J1 and J2
The diagram above correctly depicts the location of pin 1 for both J1 and J2. However the printed wiring board
shows J1 pin 1 incorrectly. Please refer to figure 4 when locating pin numbers.
3.4. PC Communication
For communicating with a PC, plug the enclosed RS-232 cable into the 9-pin connector J6 on the board. The other
end of the cable should be connected to the appropriate COM port on the PC, typically COM1 or COM2, depend-
ing on the PC’ s configuration. A 9-pin to 25-pin adapter is provided in case the PC port uses a 25-pin connector.
Cypress Semiconductor
1/12/97
Rev B
P/N MPU-80-EMU
JP1
JP2
RS3
RS11
RS9
RS7RS5
RS8RS6
RS4 RS10
J1
C51
U7
J12
U11
R1
D3
D4
D5
D6
D7
D8
D9
D10
J8
R5
D2
D1
R4
C25
C45
U12
S2
U10
J10
RP1
U3
RS1
J7
U2
U15
U14
U13
U8
U5
J2
U1
J13
C52
C53
J9
U6
J6
U9
S3
RS2
U4
J11
Figure 4. Development Board Layout
(User EPROM)
D11
S1
USB Conn.

– 4– Ver 2.4
CY3650 USB Development System User’ s Guide
The required communication settings for the PC are:
It is also recommended that the UART FIFO size settings be set tothe minimum values. In Windows 95 the follow-
ing steps will change the FIFO settings:
•On the desk-top, double click on the “ My Computer” Icon and then double click on the “ Control Panel” Icon. Alter-
nately, use the “start” menu and choose “ Settings” and then “ Control Panel”.
•In the “ Control Panel” window, double click on the “ System” Icon.
•In the “ System” window click on the “ Device Manager” tab. Then scroll down through the list of devices to the serial
port used for the USB Development Board, this is usually COM1 or COM2. Select the appropriate device by double
clicking.
•This brings up a serial device window, inside you will see tabs, select the “ Advanced” tab. This sub-widow contain the
settings for the serial transmit and receive FIFOs. Set the receive FIFO to 1 and set the transmit FIFO to 3 if this is a
valid setting, otherwise set the FIFO size to 1.
3.5. Switch Settings
Two 8-position DIP switches provide configuration options for the two on-board FPGAs. Table 1 and Table 2 list
options for switches S1 and S3 respectively. Further information on these options is given in Section 5. Unused
switches should be left in the default setting, as these may support internal test modes.
Baud Rate 19200
Data Bits 8
Parity None
Stop Bits 1
Flow Control None used
Table 1: Switch S1 Configuration
Position Open (1) Closed (0) Function
1Enable Disable USB Bus Reset
2Enable Disable Watch Dog Reset
3Enable Disable Cext (wake up)
4Enable Disable IO Port Input Only Mode
5Enable Disable Suspend on Power On Reset
6Default –Required
7Default –Required
8Default –Required

Ver 2.4 – 5–
CY3650 USB Development System User’ s Guide
4. Software Installation
For information on operation of the interactive PC debug environment, refer to the USB Development System
Software Guide.
For information on the CYASM assembly language programming and the assembler, refer to the CYASM Assem-
bler User’ s Guide.
5. Operation
5.1. Differences between the chip and the development board
The development board is lacking some of the features that are present on the integrated circuit. Three important
differences are:
1. No programmable pull-up resistors on GPIO pins
2. No programmable DAC currents on GPIO pins
3. The development board is not bus powered and therefore it is not initialized when the USB connector is
first attached.
5.2. Firmware ROM vs. RAM operation
The user’s program code will be executed from either a ROM (U5) or program RAM, depending on the setting of
switch S3-1 (see Table 2). The U5 ROM is a Cypress CY7C261-45, an 8k x 8 UV-erasable EPROM. Only 4k of
the EPROM is currently addressable. The program RAM supports the same memory size as the EPROM.
To program or erase the EPROM, refer to the data sheets for the Cypress CY7C261-45. The part can be repeatedly
reprogrammed as user firmware is updated. Follow appropriate ESD precautions when handling the part. When
installing U5 in the development board, note the IC orientation guide, shown on the board and in Figure 4.
The following examples illustrate typical procedures for operating from either ROM or RAM.
Example 1: Program ROM Operation
1. Develop assembly code; program this into the U5 Cypress CY7C261-45 EPROM.
2. Remove power from the development board.
3. Install U5 into the development board.
4. Set switch S3-1 for program ROM operation (see Table 2)
5. Apply power to the board.
Table 2: Switch S3 Configuration
Position Open (1) Closed (0) Function
1Program RAM Program ROM (U5) User-code Source
2Run on Reset Halt on Reset Operation at Reset
3–Default Unused
4–Default Unused
5–Default Unused
6–Default Unused
7–Default Unused
8–Default Unused