Epson S1C33L26 User manual

Rev.1.1
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C33L26
Technical Manual

©
SEIKO EPSON CORPORATION 2010, All rights reserved.
NOTICE
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Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as medical prod-
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Devices
S1 C 33209 F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 33000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Yx : Writer software
Corresponding model number
33L01: for S1C33L01
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number

CONTENTS
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation i
– Contents –
1 Overview........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
1.2 Block Diagram..................................................................................................................1-8
1.3 Pin Descriptions ...............................................................................................................1-9
1.3.1 Pin Arrangement................................................................................................1-9
1.3.2 Pin Functions ....................................................................................................1-12
1.3.3 Package ............................................................................................................1-20
1.3.4 Thermal Resistance of the Package .................................................................1-23
2 CPU................................................................................................................................2-1
2.1 Features of the C33 PE Core...........................................................................................2-1
2.2 CPU Registers .................................................................................................................2-2
2.3 Instruction Set ..................................................................................................................2-2
2.4 Debug Mode.....................................................................................................................2-5
2.5 Chip ID .............................................................................................................................2-6
3 Memory Map..................................................................................................................3-1
3.1 Boot Address....................................................................................................................3-2
3.2 Area 0 (IRAM, Cache Memory)........................................................................................3-3
3.2.1 IRAM..................................................................................................................3-3
3.2.2 Cache Memory ..................................................................................................3-3
3.3 Areas 1 and 2 (Reserved for System)..............................................................................3-3
3.4 Area 3 (IVRAM, DSTRAM)...............................................................................................3-3
3.4.1 IVRAM ...............................................................................................................3-3
3.4.2 DSTRAM............................................................................................................3-3
3.5 Area 6 (I/O Area)..............................................................................................................3-4
3.6 External Memory Area .....................................................................................................3-4
3.7 Bus Masters and Accessible Memories ..........................................................................3-4
3.8 Memory Access Rate.......................................................................................................3-4
4 Power Supply ................................................................................................................4-1
4.1 Power Supply Pins ...........................................................................................................4-1
4.2 Operating Voltage (LVDD)..................................................................................................4-2
4.3 Power Supply for PLL (PLLVDD, PLLVSS)..........................................................................4-2
4.4 Power Supply for RTC (RTCVDD) .....................................................................................4-2
4.5 I/O Interface Voltage (HVDD).............................................................................................4-2
4.6 Power Supply for Analog Circuits (AVDD) .........................................................................4-2
4.7 Precautions on Power Supply ..........................................................................................4-3
5 Reset and NMI...............................................................................................................5-1
5.1 Initial Reset ......................................................................................................................5-1
5.1.1 #RESET Pin.......................................................................................................5-1
5.1.2 Resetting by the Watchdog Timer ......................................................................5-1
5.1.3 Initial Reset Sequence.......................................................................................5-2
5.1.4 Initial Reset Status ............................................................................................5-2
5.1.5 Precautions to be Taken during Initial Reset......................................................5-3
5.2 NMI Input .........................................................................................................................5-3
5.2.1 #NMI Pin ............................................................................................................5-4
5.2.2 NMI by the Watchdog Timer...............................................................................5-4

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ii Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
6 Clock Management Unit (CMU) ...................................................................................6-1
6.1 CMU Module Overview ....................................................................................................6-1
6.2 CMU Pins .........................................................................................................................6-2
6.3 Oscillators ........................................................................................................................6-2
6.3.1 OSC3 Oscillator Circuit......................................................................................6-2
6.3.2 OSC1 Oscillator Circuit......................................................................................6-3
6.4 PLL...................................................................................................................................6-4
6.4.1 PLL On/Off Control ............................................................................................6-4
6.4.2 Selecting the PLL Input Clock ...........................................................................6-5
6.4.3 Setting the Frequency Multiplication Rate .........................................................6-5
6.4.4 Other PLL Settings ............................................................................................6-6
6.4.5 Power Supply for PLL ........................................................................................6-7
6.5 SSCG ...............................................................................................................................6-7
6.5.1 SSCG On/Off Control ........................................................................................6-7
6.5.2 SS Modulation Parameter Settings....................................................................6-8
6.6 System Clock Settings .....................................................................................................6-9
6.6.1 System Clock Source Selection.........................................................................6-9
6.6.2 System Clock Frequency Setting......................................................................6-10
6.6.3 Main System Clock (MCLK) Setting..................................................................6-10
6.7 Clock Supply Control.......................................................................................................6-11
6.7.1 Core Clock (CCLK) ...........................................................................................6-11
6.7.2 Bus Clock (BCLK).............................................................................................6-11
6.7.3 Peripheral Module Clocks (PCLK1, PCLK2).....................................................6-12
6.7.4 GE Module Clock (GCLK).................................................................................6-12
6.7.5 LCDC Module Clock (LCLK).............................................................................6-13
6.7.6 SRAMC and SDRAMC Clock (SDCLK)............................................................6-13
6.7.7 USB Clocks (USBCLK, USBREGCLK).............................................................6-14
6.8 Clock External Output (CMU_CLK).................................................................................6-14
6.9 Standby Modes ...............................................................................................................6-15
6.9.1 HALT Mode .......................................................................................................6-15
6.9.2 SLEEP Mode ....................................................................................................6-15
6.10 Control Register Details ................................................................................................6-16
Clock Source Select Register (CMU_OSCSEL)....................................................................... 6-16
Oscillation Control Register (CMU_OSCCTL).......................................................................... 6-17
LCDC Clock Division Ratio Select Register (CMU_LCLKDIV)................................................. 6-18
Clock Control Register (CMU_CLKCTL) .................................................................................. 6-19
System Clock Division Ratio Select Register (CMU_SYSCLKDIV) ......................................... 6-21
CMU_CLK Select Register (CMU_CMUCLK) .......................................................................... 6-22
PLL Input Clock Division Ratio Select Register (CMU_PLLINDIV) .......................................... 6-23
PLL Control Register 0 (CMU_PLLCTL0) ................................................................................ 6-24
PLL Control Register 1 (CMU_PLLCTL1) ................................................................................ 6-25
PLL Control Register 2 (CMU_PLLCTL2) ................................................................................ 6-26
SSCG Macro Control Register 0 (CMU_SSCG0)..................................................................... 6-26
SSCG Macro Control Register 1 (CMU_SSCG1)..................................................................... 6-26
CMU Write Protect Register (CMU_PROTECT)....................................................................... 6-27
7 Prescaler (PSC).............................................................................................................7-1
7.1 PSC Module Overview .....................................................................................................7-1
7.2 Control Register Details ...................................................................................................7-1
PSC Control Register (PSC_CTL)............................................................................................. 7-1
8 Real-Time Clock (RTC).................................................................................................8-1
8.1 RTC Module Overview .....................................................................................................8-1
8.2 RTC Counters ..................................................................................................................8-2

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation iii
8.3 RTC Control .....................................................................................................................8-4
8.3.1 Operating Clock Control.....................................................................................8-4
8.3.2 RTC Initial Sequence .........................................................................................8-4
8.3.3 12/24-hour Mode and Counter Settings.............................................................8-5
8.3.4 Start/Stop and Software Reset ..........................................................................8-5
8.3.5 Counter Hold and Busy Flag..............................................................................8-6
8.3.6 30-second Correction ........................................................................................8-7
8.3.7 Counter Read ....................................................................................................8-7
8.4 RTC Interrupts..................................................................................................................8-8
8.5 WAKEUP and #STBY Pins...............................................................................................8-9
8.6 Details of Control Registers ............................................................................................8-11
RTC Interrupt Status Register (RTC_INTSTAT) ....................................................................... 8-11
RTC Interrupt Mode Register (RTC_INTMODE) ...................................................................... 8-12
RTC Control 0 Register (RTC_CNTL0) .................................................................................... 8-13
RTC Control 1 Register (RTC_CNTL1) .................................................................................... 8-14
RTC Second Register (RTC_SEC)........................................................................................... 8-15
RTC Minute Register (RTC_MIN)............................................................................................. 8-15
RTC Hour Register (RTC_HOUR)............................................................................................ 8-16
RTC Day Register (RTC_DAY)................................................................................................. 8-16
RTC Month Register (RTC_MONTH) ....................................................................................... 8-17
RTC Year Register (RTC_YEAR).............................................................................................. 8-17
RTC Days of Week Register (RTC_WEEK).............................................................................. 8-18
RTC Wakeup Configuration Register (RTC_WAKEUP)............................................................ 8-18
9 SRAM Controller (SRAMC) ..........................................................................................9-1
9.1 SRAMC Module Overview ...............................................................................................9-1
9.2 SRAMC Pins ....................................................................................................................9-1
9.3 SRAMC Operating Clock..................................................................................................9-2
9.4 External Memory Areas ...................................................................................................9-2
9.4.1 Chip Enable Signals...........................................................................................9-3
9.4.2 Area Condition Settings .....................................................................................9-3
9.5 Connection of External Devices and Bus Operation ........................................................9-5
9.5.1 Connecting External Devices.............................................................................9-5
9.5.2 Data Configuration in Memory ...........................................................................9-5
9.5.3 External Bus Operation......................................................................................9-6
9.6 Bus Access Timing Charts ...............................................................................................9-7
9.6.1 SRAM Read/Write Timing with No External #WAIT...........................................9-7
9.6.2 SRAM Read/Write Timings with External #WAIT...............................................9-9
9.7 Control Register Details ..................................................................................................9-10
#CE[7:4] Access Timing Configuration Register (SRAMC_TMG47) ........................................ 9-10
#CE[10:8]Access Timing Configuration Register (SRAMC_TMG810) ..................................... 9-11
#CE[10:4] Device Configuration Register (SRAMC_TYPE) ..................................................... 9-13
10 SDRAM Controller (SDRAMC)..................................................................................10-1
10.1 SDRAMC Module Overview..........................................................................................10-1
10.2 SDRAMC Pins...............................................................................................................10-1
10.3 SDRAM Clock and Double Frequency Mode ................................................................10-2
10.4 Configuration of SDRAM...............................................................................................10-2
10.4.1 SDRAM Area ..................................................................................................10-2
10.4.2 SDRAM Size and Access Condition Settings .................................................10-2
10.5 Control and Operation of SDRAM Interface..................................................................10-7
10.5.1 Initializing SDRAM ..........................................................................................10-7
10.5.2 SDRAM Commands........................................................................................10-9
10.5.3 SDRAM Bus Operations .................................................................................10-9

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iv Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
10.5.4 Read/Write Cycles .........................................................................................10-10
10.5.5 SDRAM Refresh ............................................................................................10-12
10.5.6 Power-Down Mode.........................................................................................10-14
10.6 Data Queue Buffer (DQB) ............................................................................................10-14
10.7 Control Register Details ...............................................................................................10-15
SDRAM Initialization Register (SDRAMC_INIT)...................................................................... 10-15
SDRAM Configuration Register (SDRAMC_CFG) .................................................................. 10-17
SDRAM Refresh Register (SDRAMC_REF) ........................................................................... 10-18
SDRAM Application Configuration Register (SDRAMC_APP)................................................ 10-20
10.8 Precautions ..................................................................................................................10-20
11 Cache Controller (CCU) ............................................................................................11-1
11.1 CCU Module Overview..................................................................................................11-1
11.2 Cache Configuration .....................................................................................................11-2
11.3 Cache Settings and Operations ....................................................................................11-3
11.3.1 Cache Enable .................................................................................................11-3
11.3.2 Selecting Area to Be Cached..........................................................................11-3
11.3.3 Comparing Addresses and Cache Hit/Mishit ..................................................11-3
11.3.4 Reading Operation..........................................................................................11-4
11.3.5 Writing Operation ............................................................................................11-5
11.3.6 Flush ...............................................................................................................11-5
11.4 Cache Lock with Interrupt Level Specified ....................................................................11-5
11.5 Caching Operation during Debugging...........................................................................11-6
11.6 Cache Data Integrity .....................................................................................................11-6
11.7 Control Register Details ................................................................................................11-6
Cache Configuration Register (CCU_CFG).............................................................................. 11-6
Cacheable Area Select Register (CCU_AREA) ....................................................................... 11-7
Cache Lock Register (CCU_LK)............................................................................................... 11-8
Cache Status Register (CCU_STAT) ....................................................................................... 11-8
Cache Write Buffer Status Register (CCU_WB_STAT) ............................................................ 11-9
CCLK Division Ratio Select Register (CCU_CCLKDV) ........................................................... 11-10
12 Interrupt Controller (ITC) ..........................................................................................12-1
12.1 ITC Module Overview....................................................................................................12-1
12.2 Vector Table...................................................................................................................12-2
12.3 Control of Maskable Interrupts ......................................................................................12-3
12.3.1 Interrupt Control Bits in Peripheral Modules ...................................................12-3
12.3.2 ITC Interrupt Request Processing ..................................................................12-3
12.3.3 Interrupt Processing by the C33 PE Core.......................................................12-4
12.4 NMI................................................................................................................................12-5
12.5 Software Exception .......................................................................................................12-5
12.6 HALT and SLEEP Mode Cancellation ...........................................................................12-5
12.7 Control Register Details ................................................................................................12-6
Interrupt Level Registers (ITC_xxx_LV).................................................................................... 12-6
13 DMA Controller (DMAC) ............................................................................................13-1
13.1 DMAC Module Overview...............................................................................................13-1
13.2 DMAC Operating Clock .................................................................................................13-1
13.3 Programming Control Information .................................................................................13-2
13.3.1 Setting the Base Address ...............................................................................13-2
13.3.2 Control Information .........................................................................................13-2
13.3.3 Auto-Reload Data ...........................................................................................13-6
13.4 DMAC Invocation ..........................................................................................................13-6
13.5 Operation of DMAC.......................................................................................................13-8

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation v
13.5.1 Single Transfer Mode ......................................................................................13-8
13.5.2 Successive Transfer Mode ..............................................................................13-9
13.6 DMAC Interrupt ............................................................................................................13-10
13.7 Control Register Details ...............................................................................................13-11
DMAC Channel Enable Register (DMAC_CH_EN)................................................................. 13-11
DMAC Control Table Base Address Register (DMAC_TBL_BASE) ........................................ 13-11
DMAC Interrupt Enable Register (DMAC_IE).......................................................................... 13-12
DMAC Trigger Select Register (DMAC_TRG_SEL)................................................................. 13-13
DMAC Trigger Flag Register (DMAC_TRG_FLG) ................................................................... 13-14
DMAC End-of-Transfer Flag Register (DMAC_END_FLG)...................................................... 13-15
DMAC Running Status Register (DMAC_RUN_STAT) ............................................................ 13-15
DMAC Pause Status Register (DMAC_PAUSE_STAT)............................................................ 13-16
14 8-bit Timers (T8).........................................................................................................14-1
14.1 T8 Module Overview .....................................................................................................14-1
14.2 Count Clock...................................................................................................................14-2
14.3 Count Mode...................................................................................................................14-2
14.4 Reload Data Register and Underflow Cycle..................................................................14-2
14.5 Timer Reset...................................................................................................................14-3
14.6 RUN/STOP Control .......................................................................................................14-3
14.7 T8 Output Signals..........................................................................................................14-4
14.8 Fine Mode (Ch.0 to Ch.3)..............................................................................................14-4
14.9 T8 Interrupts ..................................................................................................................14-5
14.10 Control Register Details ..............................................................................................14-6
T8 Ch.xInput Clock Select Registers (T8_CLKx) .................................................................... 14-7
T8 Ch.xReload Data Registers (T8_TRx)................................................................................ 14-7
T8 Ch.xCounter Data Registers (T8_TCx) .............................................................................. 14-8
T8 Ch.xControl Registers (T8_CTLx)...................................................................................... 14-8
T8 Ch.xInterrupt Control Registers (T8_INTx) ........................................................................ 14-9
15 16-bit PWM Timer (T16A5).........................................................................................15-1
15.1 T16A5 Module Overview ...............................................................................................15-1
15.2 T16A5 Input/Output Pins ...............................................................................................15-2
15.3 Count Clock...................................................................................................................15-2
15.4 T16A5 Operating Modes ...............................................................................................15-3
15.4.1 Comparator Mode and Capture Mode ............................................................15-3
15.4.2 Repeat Mode and One-Shot Mode.................................................................15-4
15.5 Counter Control ............................................................................................................15-4
15.5.1 Counter Reset.................................................................................................15-4
15.5.2 Counter RUN/STOP Control ...........................................................................15-5
15.5.3 Reading Counter Values .................................................................................15-5
15.5.4 Timing Charts..................................................................................................15-5
15.6 Timer Output Control.....................................................................................................15-6
15.7 T16A5 Interrupts and DMA............................................................................................15-7
15.7.1 Interrupts.........................................................................................................15-7
15.7.2 DMA Transfer ..................................................................................................15-9
15.8 Control Register Details ................................................................................................15-9
T16A5 Ch.xCounter Control Registers (T16A_CTLx) ............................................................ 15-10
T16A5 Ch.xCounter Data Registers (T16A_TCx) .................................................................. 15-12
T16A5 Ch.xComparator/Capture Control Registers (T16A_CCCTLx) ................................... 15-13
T16A5 Ch.xComparator/Capture A Data Registers (T16A_CCAx) ........................................ 15-15
T16A5 Ch.xComparator/Capture B Data Registers (T16A_CCBx) ........................................ 15-15
T16A5 Ch.xComparator/Capture Interrupt Enable Registers (T16A_IENx) ........................... 15-16
T16A5 Ch.xComparator/Capture Interrupt Flag Registers (T16A_IFLGx) ............................. 15-16

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vi Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
16 16-bit Audio PWM Timer (T16P)................................................................................16-1
16.1 T16P Module Overview .................................................................................................16-1
16.2 T16P Input/Output Pins .................................................................................................16-2
16.3 Setting T16P Operating Conditions...............................................................................16-2
16.3.1 Count Clock ....................................................................................................16-2
16.3.2 PCM Data Configuration.................................................................................16-3
16.3.3 Operating Mode Selection ..............................................................................16-3
16.3.4 PWM Output Condition Settings .....................................................................16-4
16.4 Control and T16P Operations........................................................................................16-5
16.4.1 Resetting T16P ...............................................................................................16-5
16.4.2 Run/Stop Control ............................................................................................16-5
16.4.3 Setting Compare Data ....................................................................................16-5
16.4.4 Volume Control................................................................................................16-6
16.4.5 Counter Value .................................................................................................16-7
16.4.6 Timing Charts..................................................................................................16-7
16.5 T16P Interrupts and DMA..............................................................................................16-9
16.5.1 Interrupts.........................................................................................................16-9
16.5.2 DMA Transfer .................................................................................................16-10
16.6 Control Register Details ...............................................................................................16-10
T16P Compare A Buffer Register (T16P_A) ........................................................................... 16-10
T16P Compare B Buffer Register (T16P_B) ........................................................................... 16-11
T16P Counter Data Register (T16P_CNT_DATA) ................................................................... 16-11
T16P Volume Control Register (T16P_VOL_CTL) .................................................................. 16-11
T16P Control Register (T16P_CTL) ........................................................................................ 16-12
T16P Running Control Register (T16P_RUN)......................................................................... 16-14
T16P Internal Clock Control Register (T16P_CLK)................................................................. 16-15
T16P Interrupt Control Register (T16P_INT)........................................................................... 16-15
17 Watchdog Timer (WDT)..............................................................................................17-1
17.1 WDT Module Overview .................................................................................................17-1
17.2 WDT Input/Output Pins .................................................................................................17-1
17.3 WDT Operating Clock ..................................................................................................17-2
17.4 Control of the Watchdog Timer......................................................................................17-2
17.4.1 Setting Up the Watchdog Timer ......................................................................17-2
17.4.2 Starting/Stopping the Watchdog Timer ..........................................................17-3
17.4.3 Resetting the Watchdog Timer .......................................................................17-3
17.4.4 Operation in Standby Mode ............................................................................17-3
17.4.5 Clock Output of the Watchdog Timer .............................................................17-3
17.4.6 External NMI Output .......................................................................................17-4
17.5 Control Register Details ................................................................................................17-4
WDT Write Protect Register (WD_PROTECT)......................................................................... 17-4
WDT Enable and Setup Register (WD_EN)............................................................................. 17-5
WDT Comparison Data L/H Registers (WD_CMP_L, WD_CMP_H)........................................ 17-6
WDT Count Data L/H Registers (WD_CNT_L, WD_CNT_H)................................................... 17-6
WDT Control Register (WD_CTL) ............................................................................................ 17-6
18 Universal Serial Interface (USI) ................................................................................18-1
18.1 USI Module Overview ..................................................................................................18-1
18.2 USI Pins ........................................................................................................................18-2
18.3 USI Clock Sources ........................................................................................................18-2
18.4 USI Module Settings ....................................................................................................18-4
18.4.1 USI Module Software Reset............................................................................18-4
18.4.2 Interface Mode ................................................................................................18-4
18.4.3 General Settings for All Interface Modes ........................................................18-4

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation vii
18.4.4 Settings for UART Mode ................................................................................18-5
18.4.5 Settings for SPI Mode ....................................................................................18-5
18.4.6 Settings for I2C Mode .....................................................................................18-6
18.5 Data Transfer Control ....................................................................................................18-7
18.5.1 Data Transfer in UART Mode ..........................................................................18-7
18.5.2 Data Transfer in SPI Mode ..............................................................................18-8
18.5.3 Data Transfer in I2C Mode..............................................................................18-10
18.6 Receive Errors..............................................................................................................18-19
18.7 USI Interrupts and DMA ...............................................................................................18-20
18.7.1 Interrupts in UART Mode ...............................................................................18-20
18.7.2 Interrupts in SPI Mode ...................................................................................18-21
18.7.3 Interrupts in I2C Master Mode........................................................................18-22
18.7.4 Interrupts in I2C Slave Mode ..........................................................................18-22
18.7.5 DMA Transfer .................................................................................................18-23
18.8 Control Register Details ...............................................................................................18-23
USI Global Configuration Register (USI_GCFG)..................................................................... 18-24
USI Transmit Data Buffer Register (USI_TD) .......................................................................... 18-24
USI Receive Data Buffer Register (USI_RD)........................................................................... 18-25
USI UART Mode Configuration Register (USI_UCFG)............................................................ 18-25
USI UART Mode Interrupt Enable Register (USI_UIE)............................................................ 18-26
USI UART Mode Interrupt Flag Register (USI_UIF)................................................................ 18-26
USI SPI Master/Slave Mode Configuration Register (USI_SCFG).......................................... 18-28
USI SPI Master/Slave Mode Interrupt Enable Register (USI_SIE).......................................... 18-29
USI SPI Master/Slave Mode Interrupt Flag Register (USI_SIF) .............................................. 18-30
USI I2C Master Mode Trigger Register (USI_IMTG)................................................................ 18-31
USI I2C Master Mode Interrupt Enable Register (USI_IMIE)................................................... 18-32
USI I2C Master Mode Interrupt Flag Register (USI_IMIF) ....................................................... 18-32
USI I2C Slave Mode Trigger Register (USI_ISTG)................................................................... 18-33
USI I2C Slave Mode Interrupt Enable Register (USI_ISIE)...................................................... 18-34
USI I2C Slave Mode Interrupt Flag Register (USI_ISIF).......................................................... 18-35
18.9 Precautions ..................................................................................................................18-36
19 Universal Serial Interface with LCD Interface (USIL) .............................................19-1
19.1 USIL Module Overview ................................................................................................19-1
19.2 USIL Pins ......................................................................................................................19-2
19.3 USIL Clock Sources ......................................................................................................19-3
19.4 USIL Module Settings ..................................................................................................19-5
19.4.1 USIL Module Software Reset..........................................................................19-5
19.4.2 Interface Mode ................................................................................................19-5
19.4.3 General Settings for All Interface Modes ........................................................19-5
19.4.4 Settings for UART Mode ................................................................................19-5
19.4.5 Settings for SPI Mode ....................................................................................19-6
19.4.6 Settings for I2C Mode .....................................................................................19-7
19.4.7 Settings for LCD SPI Mode ............................................................................19-7
19.4.8 Settings for LCD Parallel Mode ......................................................................19-9
19.5 Data Transfer Control ...................................................................................................19-10
19.5.1 Data Transfer in UART Mode .........................................................................19-10
19.5.2 Data Transfer in SPI Mode .............................................................................19-11
19.5.3 Data Transfer in I2C Mode..............................................................................19-13
19.5.4 Data Transmission in LCD SPI Mode.............................................................19-23
19.5.5 Data Transfer in LCD Parallel Mode...............................................................19-24
19.6 Receive Errors..............................................................................................................19-27
19.7 USIL Interrupts and DMA .............................................................................................19-28
19.7.1 Interrupts in UART Mode ...............................................................................19-28