Epson S1C33L26 User manual

Rev.1.1
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C33L26
Technical Manual

©
SEIKO EPSON CORPORATION 2010, All rights reserved.
NOTICE
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Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
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further, there is no representation that this material is applicable to products requiring high level reliability, such as medical prod-
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Devices
S1 C 33209 F 00E1
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G: TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q: TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 33000 H2 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Dx : Evaluation board
Ex : ROM emulation board
Mx: Emulation memory for external ROM
Tx : A socket for mounting
Cx : Compiler package
Sx : Middleware package
Yx : Writer software
Corresponding model number
33L01: for S1C33L01
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number

CONTENTS
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation i
– Contents –
1 Overview........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
1.2 Block Diagram..................................................................................................................1-8
1.3 Pin Descriptions ...............................................................................................................1-9
1.3.1 Pin Arrangement................................................................................................1-9
1.3.2 Pin Functions ....................................................................................................1-12
1.3.3 Package ............................................................................................................1-20
1.3.4 Thermal Resistance of the Package .................................................................1-23
2 CPU................................................................................................................................2-1
2.1 Features of the C33 PE Core...........................................................................................2-1
2.2 CPU Registers .................................................................................................................2-2
2.3 Instruction Set ..................................................................................................................2-2
2.4 Debug Mode.....................................................................................................................2-5
2.5 Chip ID .............................................................................................................................2-6
3 Memory Map..................................................................................................................3-1
3.1 Boot Address....................................................................................................................3-2
3.2 Area 0 (IRAM, Cache Memory)........................................................................................3-3
3.2.1 IRAM..................................................................................................................3-3
3.2.2 Cache Memory ..................................................................................................3-3
3.3 Areas 1 and 2 (Reserved for System)..............................................................................3-3
3.4 Area 3 (IVRAM, DSTRAM)...............................................................................................3-3
3.4.1 IVRAM ...............................................................................................................3-3
3.4.2 DSTRAM............................................................................................................3-3
3.5 Area 6 (I/O Area)..............................................................................................................3-4
3.6 External Memory Area .....................................................................................................3-4
3.7 Bus Masters and Accessible Memories ..........................................................................3-4
3.8 Memory Access Rate.......................................................................................................3-4
4 Power Supply ................................................................................................................4-1
4.1 Power Supply Pins ...........................................................................................................4-1
4.2 Operating Voltage (LVDD)..................................................................................................4-2
4.3 Power Supply for PLL (PLLVDD, PLLVSS)..........................................................................4-2
4.4 Power Supply for RTC (RTCVDD) .....................................................................................4-2
4.5 I/O Interface Voltage (HVDD).............................................................................................4-2
4.6 Power Supply for Analog Circuits (AVDD) .........................................................................4-2
4.7 Precautions on Power Supply ..........................................................................................4-3
5 Reset and NMI...............................................................................................................5-1
5.1 Initial Reset ......................................................................................................................5-1
5.1.1 #RESET Pin.......................................................................................................5-1
5.1.2 Resetting by the Watchdog Timer ......................................................................5-1
5.1.3 Initial Reset Sequence.......................................................................................5-2
5.1.4 Initial Reset Status ............................................................................................5-2
5.1.5 Precautions to be Taken during Initial Reset......................................................5-3
5.2 NMI Input .........................................................................................................................5-3
5.2.1 #NMI Pin ............................................................................................................5-4
5.2.2 NMI by the Watchdog Timer...............................................................................5-4

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ii Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
6 Clock Management Unit (CMU) ...................................................................................6-1
6.1 CMU Module Overview ....................................................................................................6-1
6.2 CMU Pins .........................................................................................................................6-2
6.3 Oscillators ........................................................................................................................6-2
6.3.1 OSC3 Oscillator Circuit......................................................................................6-2
6.3.2 OSC1 Oscillator Circuit......................................................................................6-3
6.4 PLL...................................................................................................................................6-4
6.4.1 PLL On/Off Control ............................................................................................6-4
6.4.2 Selecting the PLL Input Clock ...........................................................................6-5
6.4.3 Setting the Frequency Multiplication Rate .........................................................6-5
6.4.4 Other PLL Settings ............................................................................................6-6
6.4.5 Power Supply for PLL ........................................................................................6-7
6.5 SSCG ...............................................................................................................................6-7
6.5.1 SSCG On/Off Control ........................................................................................6-7
6.5.2 SS Modulation Parameter Settings....................................................................6-8
6.6 System Clock Settings .....................................................................................................6-9
6.6.1 System Clock Source Selection.........................................................................6-9
6.6.2 System Clock Frequency Setting......................................................................6-10
6.6.3 Main System Clock (MCLK) Setting..................................................................6-10
6.7 Clock Supply Control.......................................................................................................6-11
6.7.1 Core Clock (CCLK) ...........................................................................................6-11
6.7.2 Bus Clock (BCLK).............................................................................................6-11
6.7.3 Peripheral Module Clocks (PCLK1, PCLK2).....................................................6-12
6.7.4 GE Module Clock (GCLK).................................................................................6-12
6.7.5 LCDC Module Clock (LCLK).............................................................................6-13
6.7.6 SRAMC and SDRAMC Clock (SDCLK)............................................................6-13
6.7.7 USB Clocks (USBCLK, USBREGCLK).............................................................6-14
6.8 Clock External Output (CMU_CLK).................................................................................6-14
6.9 Standby Modes ...............................................................................................................6-15
6.9.1 HALT Mode .......................................................................................................6-15
6.9.2 SLEEP Mode ....................................................................................................6-15
6.10 Control Register Details ................................................................................................6-16
Clock Source Select Register (CMU_OSCSEL)....................................................................... 6-16
Oscillation Control Register (CMU_OSCCTL).......................................................................... 6-17
LCDC Clock Division Ratio Select Register (CMU_LCLKDIV)................................................. 6-18
Clock Control Register (CMU_CLKCTL) .................................................................................. 6-19
System Clock Division Ratio Select Register (CMU_SYSCLKDIV) ......................................... 6-21
CMU_CLK Select Register (CMU_CMUCLK) .......................................................................... 6-22
PLL Input Clock Division Ratio Select Register (CMU_PLLINDIV) .......................................... 6-23
PLL Control Register 0 (CMU_PLLCTL0) ................................................................................ 6-24
PLL Control Register 1 (CMU_PLLCTL1) ................................................................................ 6-25
PLL Control Register 2 (CMU_PLLCTL2) ................................................................................ 6-26
SSCG Macro Control Register 0 (CMU_SSCG0)..................................................................... 6-26
SSCG Macro Control Register 1 (CMU_SSCG1)..................................................................... 6-26
CMU Write Protect Register (CMU_PROTECT)....................................................................... 6-27
7 Prescaler (PSC).............................................................................................................7-1
7.1 PSC Module Overview .....................................................................................................7-1
7.2 Control Register Details ...................................................................................................7-1
PSC Control Register (PSC_CTL)............................................................................................. 7-1
8 Real-Time Clock (RTC).................................................................................................8-1
8.1 RTC Module Overview .....................................................................................................8-1
8.2 RTC Counters ..................................................................................................................8-2

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation iii
8.3 RTC Control .....................................................................................................................8-4
8.3.1 Operating Clock Control.....................................................................................8-4
8.3.2 RTC Initial Sequence .........................................................................................8-4
8.3.3 12/24-hour Mode and Counter Settings.............................................................8-5
8.3.4 Start/Stop and Software Reset ..........................................................................8-5
8.3.5 Counter Hold and Busy Flag..............................................................................8-6
8.3.6 30-second Correction ........................................................................................8-7
8.3.7 Counter Read ....................................................................................................8-7
8.4 RTC Interrupts..................................................................................................................8-8
8.5 WAKEUP and #STBY Pins...............................................................................................8-9
8.6 Details of Control Registers ............................................................................................8-11
RTC Interrupt Status Register (RTC_INTSTAT) ....................................................................... 8-11
RTC Interrupt Mode Register (RTC_INTMODE) ...................................................................... 8-12
RTC Control 0 Register (RTC_CNTL0) .................................................................................... 8-13
RTC Control 1 Register (RTC_CNTL1) .................................................................................... 8-14
RTC Second Register (RTC_SEC)........................................................................................... 8-15
RTC Minute Register (RTC_MIN)............................................................................................. 8-15
RTC Hour Register (RTC_HOUR)............................................................................................ 8-16
RTC Day Register (RTC_DAY)................................................................................................. 8-16
RTC Month Register (RTC_MONTH) ....................................................................................... 8-17
RTC Year Register (RTC_YEAR).............................................................................................. 8-17
RTC Days of Week Register (RTC_WEEK).............................................................................. 8-18
RTC Wakeup Configuration Register (RTC_WAKEUP)............................................................ 8-18
9 SRAM Controller (SRAMC) ..........................................................................................9-1
9.1 SRAMC Module Overview ...............................................................................................9-1
9.2 SRAMC Pins ....................................................................................................................9-1
9.3 SRAMC Operating Clock..................................................................................................9-2
9.4 External Memory Areas ...................................................................................................9-2
9.4.1 Chip Enable Signals...........................................................................................9-3
9.4.2 Area Condition Settings .....................................................................................9-3
9.5 Connection of External Devices and Bus Operation ........................................................9-5
9.5.1 Connecting External Devices.............................................................................9-5
9.5.2 Data Configuration in Memory ...........................................................................9-5
9.5.3 External Bus Operation......................................................................................9-6
9.6 Bus Access Timing Charts ...............................................................................................9-7
9.6.1 SRAM Read/Write Timing with No External #WAIT...........................................9-7
9.6.2 SRAM Read/Write Timings with External #WAIT...............................................9-9
9.7 Control Register Details ..................................................................................................9-10
#CE[7:4] Access Timing Configuration Register (SRAMC_TMG47) ........................................ 9-10
#CE[10:8]Access Timing Configuration Register (SRAMC_TMG810) ..................................... 9-11
#CE[10:4] Device Configuration Register (SRAMC_TYPE) ..................................................... 9-13
10 SDRAM Controller (SDRAMC)..................................................................................10-1
10.1 SDRAMC Module Overview..........................................................................................10-1
10.2 SDRAMC Pins...............................................................................................................10-1
10.3 SDRAM Clock and Double Frequency Mode ................................................................10-2
10.4 Configuration of SDRAM...............................................................................................10-2
10.4.1 SDRAM Area ..................................................................................................10-2
10.4.2 SDRAM Size and Access Condition Settings .................................................10-2
10.5 Control and Operation of SDRAM Interface..................................................................10-7
10.5.1 Initializing SDRAM ..........................................................................................10-7
10.5.2 SDRAM Commands........................................................................................10-9
10.5.3 SDRAM Bus Operations .................................................................................10-9

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iv Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
10.5.4 Read/Write Cycles .........................................................................................10-10
10.5.5 SDRAM Refresh ............................................................................................10-12
10.5.6 Power-Down Mode.........................................................................................10-14
10.6 Data Queue Buffer (DQB) ............................................................................................10-14
10.7 Control Register Details ...............................................................................................10-15
SDRAM Initialization Register (SDRAMC_INIT)...................................................................... 10-15
SDRAM Configuration Register (SDRAMC_CFG) .................................................................. 10-17
SDRAM Refresh Register (SDRAMC_REF) ........................................................................... 10-18
SDRAM Application Configuration Register (SDRAMC_APP)................................................ 10-20
10.8 Precautions ..................................................................................................................10-20
11 Cache Controller (CCU) ............................................................................................11-1
11.1 CCU Module Overview..................................................................................................11-1
11.2 Cache Configuration .....................................................................................................11-2
11.3 Cache Settings and Operations ....................................................................................11-3
11.3.1 Cache Enable .................................................................................................11-3
11.3.2 Selecting Area to Be Cached..........................................................................11-3
11.3.3 Comparing Addresses and Cache Hit/Mishit ..................................................11-3
11.3.4 Reading Operation..........................................................................................11-4
11.3.5 Writing Operation ............................................................................................11-5
11.3.6 Flush ...............................................................................................................11-5
11.4 Cache Lock with Interrupt Level Specified ....................................................................11-5
11.5 Caching Operation during Debugging...........................................................................11-6
11.6 Cache Data Integrity .....................................................................................................11-6
11.7 Control Register Details ................................................................................................11-6
Cache Configuration Register (CCU_CFG).............................................................................. 11-6
Cacheable Area Select Register (CCU_AREA) ....................................................................... 11-7
Cache Lock Register (CCU_LK)............................................................................................... 11-8
Cache Status Register (CCU_STAT) ....................................................................................... 11-8
Cache Write Buffer Status Register (CCU_WB_STAT) ............................................................ 11-9
CCLK Division Ratio Select Register (CCU_CCLKDV) ........................................................... 11-10
12 Interrupt Controller (ITC) ..........................................................................................12-1
12.1 ITC Module Overview....................................................................................................12-1
12.2 Vector Table...................................................................................................................12-2
12.3 Control of Maskable Interrupts ......................................................................................12-3
12.3.1 Interrupt Control Bits in Peripheral Modules ...................................................12-3
12.3.2 ITC Interrupt Request Processing ..................................................................12-3
12.3.3 Interrupt Processing by the C33 PE Core.......................................................12-4
12.4 NMI................................................................................................................................12-5
12.5 Software Exception .......................................................................................................12-5
12.6 HALT and SLEEP Mode Cancellation ...........................................................................12-5
12.7 Control Register Details ................................................................................................12-6
Interrupt Level Registers (ITC_xxx_LV).................................................................................... 12-6
13 DMA Controller (DMAC) ............................................................................................13-1
13.1 DMAC Module Overview...............................................................................................13-1
13.2 DMAC Operating Clock .................................................................................................13-1
13.3 Programming Control Information .................................................................................13-2
13.3.1 Setting the Base Address ...............................................................................13-2
13.3.2 Control Information .........................................................................................13-2
13.3.3 Auto-Reload Data ...........................................................................................13-6
13.4 DMAC Invocation ..........................................................................................................13-6
13.5 Operation of DMAC.......................................................................................................13-8

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation v
13.5.1 Single Transfer Mode ......................................................................................13-8
13.5.2 Successive Transfer Mode ..............................................................................13-9
13.6 DMAC Interrupt ............................................................................................................13-10
13.7 Control Register Details ...............................................................................................13-11
DMAC Channel Enable Register (DMAC_CH_EN)................................................................. 13-11
DMAC Control Table Base Address Register (DMAC_TBL_BASE) ........................................ 13-11
DMAC Interrupt Enable Register (DMAC_IE).......................................................................... 13-12
DMAC Trigger Select Register (DMAC_TRG_SEL)................................................................. 13-13
DMAC Trigger Flag Register (DMAC_TRG_FLG) ................................................................... 13-14
DMAC End-of-Transfer Flag Register (DMAC_END_FLG)...................................................... 13-15
DMAC Running Status Register (DMAC_RUN_STAT) ............................................................ 13-15
DMAC Pause Status Register (DMAC_PAUSE_STAT)............................................................ 13-16
14 8-bit Timers (T8).........................................................................................................14-1
14.1 T8 Module Overview .....................................................................................................14-1
14.2 Count Clock...................................................................................................................14-2
14.3 Count Mode...................................................................................................................14-2
14.4 Reload Data Register and Underflow Cycle..................................................................14-2
14.5 Timer Reset...................................................................................................................14-3
14.6 RUN/STOP Control .......................................................................................................14-3
14.7 T8 Output Signals..........................................................................................................14-4
14.8 Fine Mode (Ch.0 to Ch.3)..............................................................................................14-4
14.9 T8 Interrupts ..................................................................................................................14-5
14.10 Control Register Details ..............................................................................................14-6
T8 Ch.xInput Clock Select Registers (T8_CLKx) .................................................................... 14-7
T8 Ch.xReload Data Registers (T8_TRx)................................................................................ 14-7
T8 Ch.xCounter Data Registers (T8_TCx) .............................................................................. 14-8
T8 Ch.xControl Registers (T8_CTLx)...................................................................................... 14-8
T8 Ch.xInterrupt Control Registers (T8_INTx) ........................................................................ 14-9
15 16-bit PWM Timer (T16A5).........................................................................................15-1
15.1 T16A5 Module Overview ...............................................................................................15-1
15.2 T16A5 Input/Output Pins ...............................................................................................15-2
15.3 Count Clock...................................................................................................................15-2
15.4 T16A5 Operating Modes ...............................................................................................15-3
15.4.1 Comparator Mode and Capture Mode ............................................................15-3
15.4.2 Repeat Mode and One-Shot Mode.................................................................15-4
15.5 Counter Control ............................................................................................................15-4
15.5.1 Counter Reset.................................................................................................15-4
15.5.2 Counter RUN/STOP Control ...........................................................................15-5
15.5.3 Reading Counter Values .................................................................................15-5
15.5.4 Timing Charts..................................................................................................15-5
15.6 Timer Output Control.....................................................................................................15-6
15.7 T16A5 Interrupts and DMA............................................................................................15-7
15.7.1 Interrupts.........................................................................................................15-7
15.7.2 DMA Transfer ..................................................................................................15-9
15.8 Control Register Details ................................................................................................15-9
T16A5 Ch.xCounter Control Registers (T16A_CTLx) ............................................................ 15-10
T16A5 Ch.xCounter Data Registers (T16A_TCx) .................................................................. 15-12
T16A5 Ch.xComparator/Capture Control Registers (T16A_CCCTLx) ................................... 15-13
T16A5 Ch.xComparator/Capture A Data Registers (T16A_CCAx) ........................................ 15-15
T16A5 Ch.xComparator/Capture B Data Registers (T16A_CCBx) ........................................ 15-15
T16A5 Ch.xComparator/Capture Interrupt Enable Registers (T16A_IENx) ........................... 15-16
T16A5 Ch.xComparator/Capture Interrupt Flag Registers (T16A_IFLGx) ............................. 15-16

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vi Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
16 16-bit Audio PWM Timer (T16P)................................................................................16-1
16.1 T16P Module Overview .................................................................................................16-1
16.2 T16P Input/Output Pins .................................................................................................16-2
16.3 Setting T16P Operating Conditions...............................................................................16-2
16.3.1 Count Clock ....................................................................................................16-2
16.3.2 PCM Data Configuration.................................................................................16-3
16.3.3 Operating Mode Selection ..............................................................................16-3
16.3.4 PWM Output Condition Settings .....................................................................16-4
16.4 Control and T16P Operations........................................................................................16-5
16.4.1 Resetting T16P ...............................................................................................16-5
16.4.2 Run/Stop Control ............................................................................................16-5
16.4.3 Setting Compare Data ....................................................................................16-5
16.4.4 Volume Control................................................................................................16-6
16.4.5 Counter Value .................................................................................................16-7
16.4.6 Timing Charts..................................................................................................16-7
16.5 T16P Interrupts and DMA..............................................................................................16-9
16.5.1 Interrupts.........................................................................................................16-9
16.5.2 DMA Transfer .................................................................................................16-10
16.6 Control Register Details ...............................................................................................16-10
T16P Compare A Buffer Register (T16P_A) ........................................................................... 16-10
T16P Compare B Buffer Register (T16P_B) ........................................................................... 16-11
T16P Counter Data Register (T16P_CNT_DATA) ................................................................... 16-11
T16P Volume Control Register (T16P_VOL_CTL) .................................................................. 16-11
T16P Control Register (T16P_CTL) ........................................................................................ 16-12
T16P Running Control Register (T16P_RUN)......................................................................... 16-14
T16P Internal Clock Control Register (T16P_CLK)................................................................. 16-15
T16P Interrupt Control Register (T16P_INT)........................................................................... 16-15
17 Watchdog Timer (WDT)..............................................................................................17-1
17.1 WDT Module Overview .................................................................................................17-1
17.2 WDT Input/Output Pins .................................................................................................17-1
17.3 WDT Operating Clock ..................................................................................................17-2
17.4 Control of the Watchdog Timer......................................................................................17-2
17.4.1 Setting Up the Watchdog Timer ......................................................................17-2
17.4.2 Starting/Stopping the Watchdog Timer ..........................................................17-3
17.4.3 Resetting the Watchdog Timer .......................................................................17-3
17.4.4 Operation in Standby Mode ............................................................................17-3
17.4.5 Clock Output of the Watchdog Timer .............................................................17-3
17.4.6 External NMI Output .......................................................................................17-4
17.5 Control Register Details ................................................................................................17-4
WDT Write Protect Register (WD_PROTECT)......................................................................... 17-4
WDT Enable and Setup Register (WD_EN)............................................................................. 17-5
WDT Comparison Data L/H Registers (WD_CMP_L, WD_CMP_H)........................................ 17-6
WDT Count Data L/H Registers (WD_CNT_L, WD_CNT_H)................................................... 17-6
WDT Control Register (WD_CTL) ............................................................................................ 17-6
18 Universal Serial Interface (USI) ................................................................................18-1
18.1 USI Module Overview ..................................................................................................18-1
18.2 USI Pins ........................................................................................................................18-2
18.3 USI Clock Sources ........................................................................................................18-2
18.4 USI Module Settings ....................................................................................................18-4
18.4.1 USI Module Software Reset............................................................................18-4
18.4.2 Interface Mode ................................................................................................18-4
18.4.3 General Settings for All Interface Modes ........................................................18-4

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation vii
18.4.4 Settings for UART Mode ................................................................................18-5
18.4.5 Settings for SPI Mode ....................................................................................18-5
18.4.6 Settings for I2C Mode .....................................................................................18-6
18.5 Data Transfer Control ....................................................................................................18-7
18.5.1 Data Transfer in UART Mode ..........................................................................18-7
18.5.2 Data Transfer in SPI Mode ..............................................................................18-8
18.5.3 Data Transfer in I2C Mode..............................................................................18-10
18.6 Receive Errors..............................................................................................................18-19
18.7 USI Interrupts and DMA ...............................................................................................18-20
18.7.1 Interrupts in UART Mode ...............................................................................18-20
18.7.2 Interrupts in SPI Mode ...................................................................................18-21
18.7.3 Interrupts in I2C Master Mode........................................................................18-22
18.7.4 Interrupts in I2C Slave Mode ..........................................................................18-22
18.7.5 DMA Transfer .................................................................................................18-23
18.8 Control Register Details ...............................................................................................18-23
USI Global Configuration Register (USI_GCFG)..................................................................... 18-24
USI Transmit Data Buffer Register (USI_TD) .......................................................................... 18-24
USI Receive Data Buffer Register (USI_RD)........................................................................... 18-25
USI UART Mode Configuration Register (USI_UCFG)............................................................ 18-25
USI UART Mode Interrupt Enable Register (USI_UIE)............................................................ 18-26
USI UART Mode Interrupt Flag Register (USI_UIF)................................................................ 18-26
USI SPI Master/Slave Mode Configuration Register (USI_SCFG).......................................... 18-28
USI SPI Master/Slave Mode Interrupt Enable Register (USI_SIE).......................................... 18-29
USI SPI Master/Slave Mode Interrupt Flag Register (USI_SIF) .............................................. 18-30
USI I2C Master Mode Trigger Register (USI_IMTG)................................................................ 18-31
USI I2C Master Mode Interrupt Enable Register (USI_IMIE)................................................... 18-32
USI I2C Master Mode Interrupt Flag Register (USI_IMIF) ....................................................... 18-32
USI I2C Slave Mode Trigger Register (USI_ISTG)................................................................... 18-33
USI I2C Slave Mode Interrupt Enable Register (USI_ISIE)...................................................... 18-34
USI I2C Slave Mode Interrupt Flag Register (USI_ISIF).......................................................... 18-35
18.9 Precautions ..................................................................................................................18-36
19 Universal Serial Interface with LCD Interface (USIL) .............................................19-1
19.1 USIL Module Overview ................................................................................................19-1
19.2 USIL Pins ......................................................................................................................19-2
19.3 USIL Clock Sources ......................................................................................................19-3
19.4 USIL Module Settings ..................................................................................................19-5
19.4.1 USIL Module Software Reset..........................................................................19-5
19.4.2 Interface Mode ................................................................................................19-5
19.4.3 General Settings for All Interface Modes ........................................................19-5
19.4.4 Settings for UART Mode ................................................................................19-5
19.4.5 Settings for SPI Mode ....................................................................................19-6
19.4.6 Settings for I2C Mode .....................................................................................19-7
19.4.7 Settings for LCD SPI Mode ............................................................................19-7
19.4.8 Settings for LCD Parallel Mode ......................................................................19-9
19.5 Data Transfer Control ...................................................................................................19-10
19.5.1 Data Transfer in UART Mode .........................................................................19-10
19.5.2 Data Transfer in SPI Mode .............................................................................19-11
19.5.3 Data Transfer in I2C Mode..............................................................................19-13
19.5.4 Data Transmission in LCD SPI Mode.............................................................19-23
19.5.5 Data Transfer in LCD Parallel Mode...............................................................19-24
19.6 Receive Errors..............................................................................................................19-27
19.7 USIL Interrupts and DMA .............................................................................................19-28
19.7.1 Interrupts in UART Mode ...............................................................................19-28

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19.7.2 Interrupts in SPI Mode ...................................................................................19-28
19.7.3 Interrupts in I2C Master Mode........................................................................19-29
19.7.4 Interrupts in I2C Slave Mode ..........................................................................19-30
19.7.5 Interrupts in LCD SPI Mode...........................................................................19-31
19.7.6 Interrupts in LCD Parallel Mode.....................................................................19-31
19.7.7 DMA Transfer .................................................................................................19-31
19.8 Control Register Details ...............................................................................................19-32
USIL Global Configuration Register (USIL_GCFG)................................................................. 19-32
USIL Transmit Data Buffer Register (USIL_TD) ...................................................................... 19-33
USIL Receive Data Buffer Register (USIL_RD)....................................................................... 19-33
USIL UART Mode Configuration Register (USIL_UCFG)........................................................ 19-33
USIL UART Mode Interrupt Enable Register (USIL_UIE)........................................................ 19-34
USIL UART Mode Interrupt Flag Register (USIL_UIF)............................................................ 19-35
USIL SPI Master/Slave Mode Configuration Register (USIL_SCFG)...................................... 19-36
USIL SPI Master/Slave Mode Interrupt Enable Register (USIL_SIE)...................................... 19-37
USIL SPI Master/Slave Mode Interrupt Flag Register (USIL_SIF) .......................................... 19-38
USIL I2C Master Mode Trigger Register (USIL_IMTG)............................................................ 19-39
USIL I2C Master Mode Interrupt Enable Register (USIL_IMIE)............................................... 19-40
USIL I2C Master Mode Interrupt Flag Register (USIL_IMIF) ................................................... 19-40
USIL I2C Slave Mode Trigger Register (USIL_ISTG)............................................................... 19-41
USIL I2C Slave Mode Interrupt Enable Register (USIL_ISIE).................................................. 19-42
USIL I2C Slave Mode Interrupt Flag Register (USIL_ISIF)...................................................... 19-43
USIL LCD SPI Mode Configuration Register (USIL_LSCFG) ................................................. 19-44
USIL LCD SPI Mode Interrupt Enable Register (USIL_LSIE) ................................................. 19-45
USIL LCD SPI Mode Interrupt Flag Register (USIL_LSIF)...................................................... 19-45
USIL LCD SPI Mode Data Configuration Register (USIL_LSDCFG) ...................................... 19-46
USIL LCD Parallel I/F Mode Configuration Register (USIL_LPCFG) ...................................... 19-47
USIL LCD Parallel I/F Mode Interrupt Enable Register (USIL_LPIE) ...................................... 19-48
USIL LCD Parallel I/F Mode Interrupt Flag Register (USIL_LPIF) .......................................... 19-49
USIL LCD Parallel I/F Mode Access Timing Register (USIL_LPAC) ....................................... 19-49
19.9 Precautions ..................................................................................................................19-51
20 General-Purpose Serial Interface (FSIO).................................................................20-1
20.1 FSIO Module Overview .................................................................................................20-1
20.2 FSIO Pins......................................................................................................................20-2
20.3 FSIO Operating Clock ...................................................................................................20-2
20.4 Mode Settings ...............................................................................................................20-2
20.4.1 Interface Mode and Transfer Mode .................................................................20-2
20.4.2 Standard Mode and Advanced Mode .............................................................20-3
20.5 Baud-Rate Timer (Baud Rate Setting) ..........................................................................20-3
20.6 Clock-Synchronized Interface .......................................................................................20-4
20.6.1 Outline of Clock-Synchronized Interface.........................................................20-4
20.6.2 Setting Clock-Synchronized Interface.............................................................20-5
20.6.3 Control and Operation of Clock-Synchronized Transfer ..................................20-6
20.7 Asynchronous Interface................................................................................................20-12
20.7.1 Outline of Asynchronous Interface.................................................................20-12
20.7.2 Setting Asynchronous Interface .....................................................................20-13
20.7.3 Control and Operation of Asynchronous Transfer ..........................................20-15
20.8 IrDA Interface ...............................................................................................................20-18
20.8.1 Outline of IrDA Interface.................................................................................20-18
20.8.2 Setting IrDA Interface.....................................................................................20-19
20.8.3 Control and Operation of IrDA Interface.........................................................20-20
20.9 FSIO Interrupts and DMA.............................................................................................20-21
20.9.1 Interrupts........................................................................................................20-21
20.9.2 DMA Transfer .................................................................................................20-22

CONTENTS
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation ix
20.10 Control Register Details .............................................................................................20-22
FSIO Ch.xTransmit Data Registers (FSIO_TXDx).................................................................. 20-23
FSIO Ch.xReceive Data Registers (FSIO_RXDx).................................................................. 20-23
FSIO Ch.xStatus Registers (FSIO_STATUSx) ....................................................................... 20-23
FSIO Ch.xControl Registers (FSIO_CTLx)............................................................................. 20-25
FSIO Ch.xIrDA Registers (FSIO_IRDAx) ............................................................................... 20-26
FSIO Ch.xBaud-rate Timer Control Registers (FSIO_BRTRUNx).......................................... 20-28
FSIO Ch.xBaud-rate Timer Reload Data L Registers (FSIO_BRTRDLx)............................... 20-28
FSIO Ch.xBaud-rate Timer Reload Data H Registers (FSIO_BRTRDHx).............................. 20-28
FSIO Ch.xBaud-rate Timer Count Data L Registers (FSIO_BRTCDLx)................................. 20-29
FSIO Ch.xBaud-rate Timer Count Data H Registers (FSIO_BRTCDHx) ............................... 20-29
FSIO Ch.xInterrupt Flag Registers (FSIO_INTFx) ................................................................. 20-29
FSIO Ch.xInterrupt Enable Registers (FSIO_INTEx) ............................................................. 20-30
FSIO Ch.xSTD/ADV Mode Select Registers (FSIO_ADVx) ................................................... 20-30
21 I2S................................................................................................................................21-1
21.1 I2S Module Overview.....................................................................................................21-1
21.2 I2S Output Pins..............................................................................................................21-1
21.3 I2S Module Operating Clock..........................................................................................21-2
21.4 Setting the I2S Module ..................................................................................................21-2
21.5 Data Output Control ......................................................................................................21-6
21.6 I2S Interrupt and DMA ..................................................................................................21-11
21.6.1 Interrupts........................................................................................................21-11
21.6.2 DMA Transfer .................................................................................................21-12
21.7 Control Register Details ...............................................................................................21-12
I2S Control Register (I2S_CTL) ............................................................................................... 21-13
I2S Master Clock Division Ratio Register (I2S_DV_MCLK)..................................................... 21-16
I2S Audio Clock Division Ratio Register (I2S_DV_AUDIO_CLK)............................................. 21-16
I2S Start/Stop Register (I2S_START) ...................................................................................... 21-18
I2S FIFO Status Register (I2S_FIFO_STAT)............................................................................ 21-18
I2S Interrupt Control Register (I2S_INT).................................................................................. 21-19
I2S FIFO Register (I2S_FIFO) ................................................................................................. 21-21
21.8 Setting the I2S Clocks ..................................................................................................21-22
22 Remote Controller (REMC) .......................................................................................22-1
22.1 REMC Module Overview...............................................................................................22-1
22.2 REMC Input/Output Pins...............................................................................................22-1
22.3 Carrier Generation ........................................................................................................22-1
22.4 Data Length Counter Clock Settings.............................................................................22-2
22.5 Data Transfer Control ....................................................................................................22-3
22.6 REMC Interrupts ...........................................................................................................22-5
22.7 Control Register Details ................................................................................................22-6
REMC Configuration Register (REMC_CFG)........................................................................... 22-6
REMC Carrier Length Setup Register (REMC_CAR)............................................................... 22-7
REMC Length Counter Register (REMC_LCNT) ..................................................................... 22-8
REMC Interrupt Control Register (REMC_INT)........................................................................ 22-8
23 Card Interface (CARD)...............................................................................................23-1
23.1 CARD Module Overview ...............................................................................................23-1
23.2 CARD Output Pins ........................................................................................................23-1
23.3 Card Interface Control Signals ......................................................................................23-1
24 I/O Ports (GPIO) .........................................................................................................24-1
24.1 GPIO Module Overview ................................................................................................24-1
24.2 Input/Output Pin Function Selection (Port MUX)...........................................................24-2

CONTENTS
xSeiko Epson Corporation S1C33L26 TECHNICAL MANUAL
24.3 Data Input/Output..........................................................................................................24-3
24.4 Pull-up Control ..............................................................................................................24-4
24.5 Port Input Interrupt and DMA ........................................................................................24-4
24.6 Input Port Noise Filters..................................................................................................24-9
24.7 Bus Drive Control ..........................................................................................................24-9
24.8 Control Register Details ................................................................................................24-9
PxPort Data Registers (GPIO_Px_DAT)................................................................................. 24-11
PxPort I/O Control Registers (GPIO_Px_IOC) ....................................................................... 24-11
Bus Drive Control Register (GPIO_BUS_DRV)....................................................................... 24-12
PxPort Pull-up Control Registers (GPIO_Px_PUP)................................................................ 24-12
FPT0–3 Interrupt Port Select Register (GPIO_FPT03_SEL) .................................................. 24-13
FPT4–7 Interrupt Port Select Register (GPIO_FPT47_SEL) .................................................. 24-13
FPT8–B Interrupt Port Select Register (GPIO_FPT8B_SEL).................................................. 24-14
FPTC–F Interrupt Port Select Register (GPIO_FPTCF_SEL)................................................. 24-15
FPT0–3 Interrupt Polarity Select Register (GPIO_FPT03_POL)............................................. 24-15
FPT4–7 Interrupt Polarity Select Register (GPIO_FPT47_POL)............................................. 24-16
FPT8–B Interrupt Polarity Select Register (GPIO_FPT8B_POL)............................................ 24-16
FPTC–F Interrupt Polarity Select Register (GPIO_FPTCF_POL) ........................................... 24-16
FPT0–3 Interrupt Mode Select Register (GPIO_FPT03_MOD) .............................................. 24-16
FPT4–7 Interrupt Mode Select Register (GPIO_FPT47_MOD) .............................................. 24-17
FPT8–B Interrupt Mode Select Register (GPIO_FPT8B_MOD) ............................................. 24-17
FPTC–F Interrupt Mode Select Register (GPIO_FPTCF_MOD)............................................. 24-17
FPT0–3 Interrupt Mask Register (GPIO_FPT03_MSK) .......................................................... 24-18
FPT4–7 Interrupt Mask Register (GPIO_FPT47_MSK) .......................................................... 24-18
FPT8–B Interrupt Mask Register (GPIO_FPT8B_MSK) ......................................................... 24-18
FPTC–F Interrupt Mask Register (GPIO_FPTCF_MSK)......................................................... 24-18
FPT0–3 Interrupt Flag Register (GPIO_FPT03_FLG)............................................................. 24-19
FPT4–7 Interrupt Flag Register (GPIO_FPT47_FLG)............................................................. 24-19
FPT8–B Interrupt Flag Register (GPIO_FPT8B_FLG)............................................................ 24-19
FPTC–F Interrupt Flag Register (GPIO_FPTCF_FLG) ........................................................... 24-20
FPT0–1 Interrupt Chattering Filter Control Register (GPIO_FPT01_CHAT) ........................... 24-20
FPT2–3 Interrupt Chattering Filter Control Register (GPIO_FPT23_CHAT) ........................... 24-21
FPT4–5 Interrupt Chattering Filter Control Register (GPIO_FPT45_CHAT) ........................... 24-22
FPT6–7 Interrupt Chattering Filter Control Register (GPIO_FPT67_CHAT) ........................... 24-22
FPT8–9 Interrupt Chattering Filter Control Register (GPIO_FPT89_CHAT) ........................... 24-23
FPTA–B Interrupt Chattering Filter Control Register (GPIO_FPTAB_CHAT) .......................... 24-23
FPTC–D Interrupt Chattering Filter Control Register (GPIO_FPTCD_ CHAT).......................... 24-24
FPTE–F Interrupt Chattering Filter Control Register (GPIO_FPTEF_CHAT).......................... 24-24
Port DMA Trigger Source Select Register (GPIO_DMA) ......................................................... 24-25
P0[3:0] Port Function Select Register (PMUX_P0_03) ........................................................... 24-26
P0[7:4] Port Function Select Register (PMUX_P0_47) ........................................................... 24-27
P1[3:0] Port Function Select Register (PMUX_P1_03) ........................................................... 24-28
P1[7:4] Port Function Select Register (PMUX_P1_47) ........................................................... 24-29
P2[1:0] Port Function Select Register (PMUX_P2_01) ........................................................... 24-29
P3[3:0] Port Function Select Register (PMUX_P3_03) ........................................................... 24-30
P3[6:4] Port Function Select Register (PMUX_P3_46) ........................................................... 24-31
P4[2:0] Port Function Select Register (PMUX_P4_02) ........................................................... 24-31
P5[3:0] Port Function Select Register (PMUX_P5_03) ........................................................... 24-32
P5[6:4] Port Function Select Register (PMUX_P5_46) ........................................................... 24-33
P60 Port Function Select Register (PMUX_P6_0) .................................................................. 24-33
P7[3:0] Port Function Select Register (PMUX_P7_03) ........................................................... 24-34
P7[5:4] Port Function Select Register (PMUX_P7_45) ........................................................... 24-34
P8[3:0] Port Function Select Register (PMUX_P8_03) ........................................................... 24-35
P9[3:0] Port Function Select Register (PMUX_P9_03) ........................................................... 24-36
P9[7:4] Port Function Select Register (PMUX_P9_47) ........................................................... 24-37
PA[3:0] Port Function Select Register (PMUX_PA_03) ........................................................... 24-38
PA[6:4] Port Function Select Register (PMUX_PA_46) ........................................................... 24-38
PB[3:0] Port Function Select Register (PMUX_PB_03) .......................................................... 24-39

CONTENTS
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation xi
PB[7:4] Port Function Select Register (PMUX_PB_47) .......................................................... 24-40
PC[3:0] Port Function Select Register (PMUX_PC_03) .......................................................... 24-41
PC[7:4] Port Function Select Register (PMUX_PC_47) .......................................................... 24-42
Port Noise Filter Control Register (GPIO_FILTER) ................................................................. 24-42
GPIO/PMUX Write Protect Register (GPIO_PROTECT)......................................................... 24-43
25 A/D Converter (ADC10) .............................................................................................25-1
25.1 ADC10 Module Overview..............................................................................................25-1
25.2 ADC10 Input Pins..........................................................................................................25-2
25.3 A/D Converter Settings .................................................................................................25-2
25.3.1 A/D Conversion Clock Setting.........................................................................25-2
25.3.2 Selecting A/D Conversion Start and End Channels........................................25-3
25.3.3 A/D Conversion Mode Setting.........................................................................25-4
25.3.4 Trigger Selection ............................................................................................25-4
25.3.5 Sampling Time Setting ...................................................................................25-4
25.3.6 Setting Conversion Result Storing Mode ........................................................25-5
25.4 A/D Conversion Control and Operations.......................................................................25-5
25.4.1 Activating A/D Converter.................................................................................25-5
25.4.2 Starting A/D Conversion .................................................................................25-5
25.4.3 Reading A/D Conversion Results ...................................................................25-5
25.4.4 Terminating A/D Conversion ...........................................................................25-6
25.4.5 Timing Charts..................................................................................................25-6
25.5 A/D Converter Interrupts and DMA ...............................................................................25-8
25.6 Control Register Details ................................................................................................25-8
A/D Conversion Result Register (ADC10_ADD) ..................................................................... 25-9
A/D Trigger/Channel Select Register (ADC10_TRG) .............................................................. 25-9
A/D Control/Status Register (ADC10_CTL) ............................................................................ 25-11
A/D Clock Control Register (ADC10_CLK) ............................................................................. 25-13
26 LCD Controller (LCDC)..............................................................................................26-1
26.1 LCDC Module Overview................................................................................................26-1
26.2 Block Diagram...............................................................................................................26-2
26.3 LCDC Output Pins.........................................................................................................26-3
26.4 System Settings ............................................................................................................26-5
26.4.1 Configuration of Display Data Memory (VRAM) .............................................26-5
26.4.2 Setting the LCDC Clock..................................................................................26-6
26.5 Setting the LCD Panel...................................................................................................26-7
26.5.1 Types of Panels...............................................................................................26-7
26.5.2 STN Panel Timing Parameters........................................................................26-7
26.5.3 HR-TFT Panel Timing Parameters.................................................................26-11
26.5.4 Display Modes ...............................................................................................26-14
26.5.5 VRAM Data Format........................................................................................26-15
26.5.6 LUT Bypass Mode .........................................................................................26-20
26.5.7 Look-up Tables...............................................................................................26-26
26.5.8 Frame Rates ..................................................................................................26-28
26.5.9 Other Settings................................................................................................26-28
26.6 Display Control.............................................................................................................26-29
26.6.1 Controlling LCD Power Up/Down...................................................................26-29
26.6.2 Main Window Display Start Address and Virtual Screen Settings .................26-29
26.6.3 Writing Display Data ......................................................................................26-31
26.6.4 Inverting and Blanking the Display.................................................................26-31
26.6.5 Picture-in-Picture Plus and Sub-Window.......................................................26-31
26.7 LCDC Interrupt .............................................................................................................26-34
26.8 Power Save ..................................................................................................................26-34

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xii Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
26.9 Reload Functions .........................................................................................................26-35
26.10 Control Register Details .............................................................................................26-36
LCDC Interrupt Enable Register (LCDC_INT)......................................................................... 26-37
Status and Power Save Configuration Register (LCDC_PSAVE)............................................ 26-37
Horizontal Display Register (LCDC_HDISP)........................................................................... 26-38
Vertical Display Register (LCDC_VDISP)................................................................................ 26-38
MOD Rate Register (LCDC_MODR)....................................................................................... 26-39
Horizontal Display Start Position Register (LCDC_HDPS)...................................................... 26-39
Vertical Display Start Position Register (LCDC_VDPS) .......................................................... 26-39
FPLINE Pulse Setting Register (LCDC_FPLINE).................................................................... 26-40
FPFRAME Pulse Setting Register (LCDC_FPFR) .................................................................. 26-40
FPFRAME Pulse Offset Register (LCDC_FPFROFS) ............................................................ 26-41
TFT Special Output Register (LCDC_TFTSO)........................................................................ 26-41
TFT_CTL1 Pulse Register (LCDC_TFT_CTL1) ...................................................................... 26-42
TFT_CTL0 Pulse Register (LCDC_TFT_CTL0) ...................................................................... 26-43
TFT_CTL2 Register (LCDC_TFT_CTL2) ................................................................................ 26-43
LCDC Reload Control Register (LCDC_RLDCTL) .................................................................. 26-43
LCDC Reload Table Base Address Register (LCDC_RLDADR) ............................................. 26-44
LCDC Display Mode Register (LCDC_DISPMOD).................................................................. 26-45
Main Window Display Start Address Register (LCDC_MAINADR) ......................................... 26-47
Main Screen Address Offset Register (LCDC_MAINOFS)...................................................... 26-47
Sub-window Display Start Address Register (LCDC_SUBADR)............................................. 26-47
Sub-Screen Address Offset Register (LCDC_SUBOFS) ........................................................ 26-47
Sub-Window Start Position Register (LCDC_SUBSP)............................................................ 26-48
Sub-Window End Position Register (LCDC_SUBEP) ............................................................. 26-48
Monochrome Look-up Table Registers 0 and 1 (LCDC_MLUT0/1) ......................................... 26-49
27 Graphics Engine (GE) ...............................................................................................27-1
27.1 GE Module Overview ....................................................................................................27-1
27.2 Operating Clock.............................................................................................................27-2
27.3 Drawing Functions.........................................................................................................27-2
27.3.1 Drawing Area ..................................................................................................27-2
27.3.2 Drawing Basic Objects....................................................................................27-5
27.3.3 Drawing Characters and Symbols ..................................................................27-9
27.3.4 Decompression/Copy Functions ....................................................................27-10
27.3.5 Drawing Effects..............................................................................................27-14
27.4 Controlling GE..............................................................................................................27-20
27.4.1 Initial Settings ................................................................................................27-20
27.4.2 Command Execution and Termination ...........................................................27-20
27.4.3 Status Check During Execution .....................................................................27-21
27.4.4 Updated Range in Work Area ........................................................................27-22
27.4.5 Errors .............................................................................................................27-22
27.4.6 GE Reset .......................................................................................................27-24
27.4.7 GE Interrupts .................................................................................................27-25
27.5 Command Details.........................................................................................................27-26
27.5.1 Command Format ..........................................................................................27-26
27.5.2 List of Commands..........................................................................................27-27
27.5.3 STOP1–4 Commands (Stop) .........................................................................27-27
27.5.4 GE_CONFIG Command (GE Configuration) .................................................27-28
27.5.5 DOT Command (Dot Drawing).......................................................................27-28
27.5.6 LINE Command (Straight Line Drawing)........................................................27-30
27.5.7 RECT Command (Rectangle Drawing)..........................................................27-31
27.5.8 TRI_FILL Command (Solid Filled Triangle Drawing)......................................27-33
27.5.9 RECT_FILL Command (Solid Filled Rectangle Drawing) ..............................27-35
27.5.10 QUAD_FILL Command (Solid Filled Quadrilateral Drawing) .......................27-37
27.5.11 CIRCLE Command (Circle Drawing) ...........................................................27-39

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S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation xiii
27.5.12 CIRCLE_FILL Command (Solid Filled Circle Drawing)................................27-41
27.5.13 FONT_CFG Command (Font Configuration) ...............................................27-42
27.5.14 CHAR Command (Character Drawing)........................................................27-43
27.5.15 DECOMP Command (Decompression and Drawing) ..................................27-45
27.5.16 COPY Command (Copy) .............................................................................27-47
27.5.17 BLKCOPY Command (Block Transfer).........................................................27-49
27.6 Control Register Details ...............................................................................................27-51
GE Command Address Register (GE_CMD_ADDR) .............................................................. 27-51
GE Control Register (GE_CTL)............................................................................................... 27-52
GE Interrupt Enable Register (GE_IE) .................................................................................... 27-53
GE Interrupt Flag Register 1 (GE_IF1).................................................................................... 27-54
GE Interrupt Flag Register 2 (GE_IF2).................................................................................... 27-55
GE Interrupt Flag Register 3 (GE_IF3).................................................................................... 27-57
VRAM Work Area Width Register (GE_REAL_W) .................................................................. 27-57
VRAM Work Area Start Address Register (GE_WK_ADDR) .................................................. 27-57
VRAM Work Area Size Register (GE_WK_SIZE).................................................................... 27-58
Display Configuration Register (GE_DISP_CFG) ................................................................... 27-58
VRAM Rotation Control Register (GE_ROTATE)..................................................................... 27-60
Clipping Area Start Position Register (GE_CLIP_ST)............................................................. 27-60
Clipping Area End Position Register (GE_CLIP_END) ........................................................... 27-61
Mesh Configuration Register (GE_MESH).............................................................................. 27-61
Transparent Color Register (GE_MAGIC) ............................................................................... 27-62
Updated Area Start Position Register (GE_UPDT_ST)........................................................... 27-62
Updated Area End Position Register (GE_UPDT_END)......................................................... 27-63
Palette 1 (GE_PALETTE1) ...................................................................................................... 27-63
CCT1 4-bit Entries (GE_CCT1_4BIT) ..................................................................................... 27-63
CCT1 2-bit Entries (GE_CCT1_2BIT) ..................................................................................... 27-64
CCT1 1-bit Entries (GE_CCT1_1BIT) ..................................................................................... 27-64
27.7 LCDC Settings .............................................................................................................27-64
28 USB Function Controller (USB)................................................................................28-1
28.1 USB Function Controller Overview ...............................................................................28-1
28.2 Pins for the USB Interface.............................................................................................28-2
28.3 USB Operating Clocks ..................................................................................................28-2
28.4 Settings in Other Modules.............................................................................................28-2
28.5 Functional Description ..................................................................................................28-2
28.5.1 USB Control....................................................................................................28-3
28.5.2 FIFO Management.........................................................................................28-16
28.5.3 Port Interface .................................................................................................28-18
28.5.4 Snooze...........................................................................................................28-22
28.6 Registers ......................................................................................................................28-23
28.6.1 List of Registers .............................................................................................28-23
28.6.2 Detailed Description of Registers ..................................................................28-26
MainIntStat (Main Interrupt Status) ......................................................................................... 28-26
SIE_IntStat (SIE Interrupt Status) ........................................................................................... 28-27
EPrIntStat (EPr Interrupt Status) ............................................................................................. 28-28
DMA_IntStat (DMA Interrupt Status) ....................................................................................... 28-28
FIFO_IntStat (FIFO Interrupt Status)....................................................................................... 28-28
EP0IntStat (EP0 Interrupt Status) ........................................................................................... 28-29
EPaIntStat (EPa Interrupt Status)............................................................................................ 28-30
EPbIntStat (EPb Interrupt Status) ........................................................................................... 28-30
EPcIntStat (EPc Interrupt Status)............................................................................................ 28-31
EPdIntStat (EPd Interrupt Status) ........................................................................................... 28-32
MainIntEnb (Main Interrupt Enable)......................................................................................... 28-32
SIE_IntEnb (SIE Interrupt Enable)........................................................................................... 28-33
EPrIntEnb (EPr Interrupt Enable) ............................................................................................ 28-33

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xiv Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
DMA_IntEnb (DMA Interrupt Enable) ...................................................................................... 28-33
FIFO_IntEnb (FIFO Interrupt Enable)...................................................................................... 28-33
EP0IntEnb (EP0 Interrupt Enable)........................................................................................... 28-33
EPaIntEnb (EPa Interrupt Enable)........................................................................................... 28-34
EPbIntEnb (EPb Interrupt Enable)........................................................................................... 28-34
EPcIntEnb (EPc Interrupt Enable)........................................................................................... 28-34
EPdIntEnb (EPd Interrupt Enable)........................................................................................... 28-34
RevisionNum (Revision Number) ............................................................................................ 28-34
USB_Control (USB Control) .................................................................................................... 28-35
USB_Status (USB Status)....................................................................................................... 28-35
XcvrControl (Xcvr Control)....................................................................................................... 28-36
USB_Test (USB Test) .............................................................................................................. 28-36
EPnControl (Endpoint Control)................................................................................................ 28-37
EPrFIFO_Clr (EPr FIFO Clear)................................................................................................ 28-38
FrameNumber_H (Frame Number HIGH)................................................................................ 28-39
FrameNumber_L (Frame Number LOW)................................................................................. 28-39
EP0Setup_0 (EP0 Setup 0)–EP0Setup_7 (EP0 Setup 7)....................................................... 28-39
USB_Address (USB Address)................................................................................................. 28-40
EP0Control (EP0 Control) ....................................................................................................... 28-40
EP0ControlIN (EP0 Control IN) ............................................................................................... 28-41
EP0ControlOUT (EP0 Control OUT) ....................................................................................... 28-42
EP0MaxSize (EP0 Max Packet Size) ...................................................................................... 28-42
EPaControl (EPa Control)........................................................................................................ 28-43
EPbControl (EPb Control) ....................................................................................................... 28-44
EPcControl (EPc Control)........................................................................................................ 28-44
EPdControl (EPd Control) ....................................................................................................... 28-45
EPaMaxSize_H (EPa Max Packet Size HIGH)........................................................................ 28-46
EPaMaxSize_L (EPa Max Packet Size LOW).......................................................................... 28-46
EPaConfig_0 (EPa Configuration 0)........................................................................................ 28-47
EPaConfig_1 (EPa Configuration 1)........................................................................................ 28-47
EPbMaxSize_H (EPb Max Packet Size HIGH)........................................................................ 28-47
EPbMaxSize_L (EPb Max Packet Size LOW) ......................................................................... 28-47
EPbConfig_0 (EPb Configuration 0)........................................................................................ 28-48
EPbConfig_1 (EPb Configuration 1)........................................................................................ 28-48
EPcMaxSize_H (EPc Max Packet Size HIGH) ........................................................................ 28-49
EPcMaxSize_L (EPc Max Packet Size LOW).......................................................................... 28-49
EPcConfig_0 (EPc Configuration 0) ........................................................................................ 28-49
EPcConfig_1 (EPc Configuration 1) ........................................................................................ 28-49
EPdMaxSize_H (EPd Max Packet Size HIGH)........................................................................ 28-50
EPdMaxSize_L (EPd Max Packet Size LOW) ......................................................................... 28-50
EPdConfig_0 (EPd Configuration 0)........................................................................................ 28-50
EPdConfig_1 (EPd Configuration 1)........................................................................................ 28-50
EPaStartAdrs_H (EPa FIFO Start Address HIGH) .................................................................. 28-51
EPaStartAdrs_L (EPa FIFO Start Address LOW) ................................................................... 28-51
EPbStartAdrs_H (EPb FIFO Start Address HIGH).................................................................. 28-51
EPbStartAdrs_L (EPb FIFO Start Address LOW) ................................................................... 28-51
EPcStartAdrs_H (EPc FIFO Start Address HIGH) .................................................................. 28-52
EPcStartAdrs_L (EPc FIFO Start Address LOW).................................................................... 28-52
EPdStartAdrs_H (EPd FIFO Start Address HIGH).................................................................. 28-52
EPdStartAdrs_L (EPd FIFO Start Address LOW) ................................................................... 28-52
CPU_JoinRd (CPU Join FIFO Read) ...................................................................................... 28-53
CPU_JoinWr (CPU Join FIFO Write)....................................................................................... 28-53
EnEPnFIFO_Access (EPn FIFO Access Enable) ................................................................... 28-54
EPnFIFOforCPU (EPn FIFO for CPU)..................................................................................... 28-54
EPnRdRemain_H (EPn FIFO Read Remain HIGH)................................................................ 28-55
EPnRdRemain_L (EPn FIFO Read Remain LOW) ................................................................. 28-55
EPnWrRemain_H (EPn FIFO Write Remain HIGH) ................................................................ 28-55
EPnWrRemain_L (EPn FIFO Write Remain LOW).................................................................. 28-55
DescAdrs_H (Descriptor Address HIGH) ................................................................................ 28-55

CONTENTS
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation xv
DescAdrs_L (Descriptor Address LOW).................................................................................. 28-55
DescSize_H (Descriptor Size HIGH)....................................................................................... 28-56
DescSize_L (Descriptor Size LOW)......................................................................................... 28-56
DescDoor (Descriptor Door).................................................................................................... 28-56
DMA_FIFO_Control (DMA FIFO Control)................................................................................ 28-57
DMA_Join (DMA Join FIFO).................................................................................................... 28-57
DMA_Control (DMA Control)................................................................................................... 28-57
DMA_Config_0 (DMA Configuration 0) ................................................................................... 28-58
DMA_Config_1 (DMA Configuration 1) ................................................................................... 28-58
DMA_Latency (DMA Latency)................................................................................................. 28-60
DMA_Remain_H (DMA FIFO Remain HIGH).......................................................................... 28-60
DMA_Remain_L (DMA FIFO Remain LOW)........................................................................... 28-60
DMA_Count_HH (DMA Transfer Byte Counter HIGH/HIGH)................................................... 28-60
DMA_Count_HL (DMA Transfer Byte Counter HIGH/LOW) .................................................... 28-60
DMA_Count_LH (DMA Transfer Byte Counter LOW/HIGH) .................................................... 28-60
DMA_Count_LL (DMA Transfer Byte Counter LOW/LOW)...................................................... 28-60
29 Misc Registers (MISC)...............................................................................................29-1
29.1 RTC Wait Control ..........................................................................................................29-1
29.2 Internal RAM Wait Control.............................................................................................29-1
29.3 USB Settings.................................................................................................................29-2
29.3.1 USB Wait Control ............................................................................................29-2
29.3.2 Snooze Control ...............................................................................................29-2
29.3.3 USB Interrupt Enable......................................................................................29-2
29.4 RAM Location................................................................................................................29-2
29.5 Boot Register ................................................................................................................29-2
29.6 Control Register Details ................................................................................................29-3
RTC Wait Control Register (MISC_RTCWT)............................................................................ 29-3
USB Configuration Register (MISC_USB)................................................................................ 29-3
Internal RAM Wait Control Register (MISC_RAMWT).............................................................. 29-4
Boot Register (MISC_BOOT) ................................................................................................... 29-5
RAM Location Select Register (MISC_RAM_LOC).................................................................. 29-5
Misc Protect Register (MISC_PROTECT) ................................................................................ 29-6
30 Divider (DIV)...............................................................................................................30-1
31 Electrical Characteristics..........................................................................................31-1
31.1 Absolute Maximum Rating ............................................................................................31-1
31.2 Recommended Operating Conditions ...........................................................................31-1
31.3 DC Characteristics ........................................................................................................31-2
31.4 Current Consumption ....................................................................................................31-3
31.5 A/D Converter Characteristics.......................................................................................31-5
31.6 Oscillation Characteristics.............................................................................................31-6
31.7 PLL Characteristics .......................................................................................................31-7
31.8 AC Characteristics.........................................................................................................31-7
31.8.1 External Clock Input Characteristics...............................................................31-7
31.8.2 SRAMC AC Characteristics ............................................................................31-7
31.8.3 SDRAMC AC Characteristics..........................................................................31-8
31.8.4 USI/USIL AC Characteristics .........................................................................31-11
31.8.5 LCDC AC Characteristics ..............................................................................31-13
31.8.6 #STBY AC Characteristics.............................................................................31-24
31.9 USB DC and AC Characteristics..................................................................................31-24
32 Basic External Connection Diagram........................................................................32-1

CONTENTS
xvi Seiko Epson Corporation S1C33L26 TECHNICAL MANUAL
Appendix A List of I/O Registers................................................................................ AP-A-1
0x300010–0x300020 Misc Registers (MISC)................................................ AP-A-9
0x300100–0x300110 Clock Management Unit (CMU).................................. AP-A-9
0x300210–0x30022c Interrupt Controller (ITC) ........................................... AP-A-11
0x300300–0x30083f GPIO & Port MUX...................................................... AP-A-13
0x300400–0x300472 USI............................................................................. AP-A-25
0x300600–0x30069f USIL........................................................................... AP-A-27
0x300700–0x30070f FSIO Ch.0.................................................................. AP-A-30
0x300710–0x30071f FSIO Ch.1.................................................................. AP-A-31
0x300a00–0x300a0f Real-time Clock (RTC)............................................... AP-A-32
0x300b00–0x300b0f BBRAM...................................................................... AP-A-33
0x300c00–0x300c9f USB Function Controller (USB) ................................. AP-A-33
0x300e00 Prescaler (PSC)......................................................... AP-A-39
0x301000–0x30100c Watchdog Timer (WDT)............................................. AP-A-39
0x301100–0x301108 8-bit Timer (T8) Ch.0 (with Fine mode)...................... AP-A-40
0x301110–0x301118 8-bit Timer (T8) Ch.1 (with Fine mode)...................... AP-A-41
0x301120–0x301128 8-bit Timer (T8) Ch.2 (with Fine mode)...................... AP-A-41
0x301130–0x301138 8-bit Timer (T8) Ch.3 (with Fine mode)...................... AP-A-42
0x301140–0x301148 8-bit Timer (T8) Ch.4 ................................................. AP-A-43
0x301150–0x301158 8-bit Timer (T8) Ch.5 ................................................. AP-A-43
0x301160–0x301168 8-bit Timer (T8) Ch.6 ................................................. AP-A-44
0x301170–0x301178 8-bit Timer (T8) Ch.7 ................................................. AP-A-44
0x301180–0x30118c 16-bit PWM Timer (T16A5) Ch.0 ............................... AP-A-45
0x301190–0x30119c 16-bit PWM Timer (T16A5) Ch.1 ............................... AP-A-46
0x301200–0x30120e 16-bit Audio PWM Timer (T16P)................................ AP-A-47
0x301300–0x301306 A/D Converter (ADC10)............................................. AP-A-48
0x301400–0x301412 I2S.............................................................................. AP-A-49
0x301500–0x301506 Remote Controller (REMC) ....................................... AP-A-50
0x302000–0x302094 LCD Controller (LCDC).............................................. AP-A-51
0x302100–0x30211c DMA Controller (DMAC) ............................................ AP-A-54
0x302200–0x302210 SDRAM Controller (SDRAMC) .................................. AP-A-55
0x302220–0x302228 SRAM Controller (SRAMC) ....................................... AP-A-56
0x302300–0x302360 Cache Controller (CCU) ............................................ AP-A-57
0x30240c–0x302925 Graphics Engine (GE) ............................................... AP-A-58
Appendix B Power Saving .......................................................................................... AP-B-1
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Boot ......................................................................................................... AP-D-1
D.1 Boot Mode .................................................................................................................. AP-D-1
D.2 NOR Flash/External ROM Boot................................................................................... AP-D-1
D.2.1 Configuration of NOR Flash/External ROM Boot System ............................. AP-D-1
D.2.2 NOR Flash/External ROM Boot Sequence ................................................... AP-D-2
D.2.3 Reset Vector for NOR Flash/External ROM Boot .......................................... AP-D-2
D.3 SPI-EEPROM Boot ...................................................................................................... AP-D-3
D.3.1 Configuration of SPI-EEPROM Boot System ................................................ AP-D-3
D.3.2 SPI-EEPROM Boot Sequence ..................................................................... AP-D-4
D.3.3 EEPROM Data .............................................................................................. AP-D-5
D.4 PC RS232C Boot......................................................................................................... AP-D-6
D.4.1 Configuration of PC RS232C Boot System .................................................. AP-D-6
D.4.2 PC RS232C Boot Sequence ........................................................................ AP-D-6
D.4.3 Transfer Data ................................................................................................. AP-D-8
Revision History

1 OVERVIEW
S1C33L26 TECHNICAL MANUAL Seiko Epson Corporation 1-1
Overview1
The S1C33L26 is a 32-bit application specific RISC controller that features extensive peripheral circuits such as an
enhanced drawing graphics module, GPIO ports, serial interface modules, a USB module, PWM generators, and an
A/D converter. It is suitable for applications that require a high-resolution LCD display, e.g. control panels on OA/
FA equipment and intelligent remote controllers.
The S1C33L26 incorporates an LCD controller and VRAM supporting four-level gray scale QVGA display in
single-chip. Adding an external SDRAM expands this capability into a higher resolution and with more displayable
colors (e.g., 64K-color VGA display). An LCD driver interface with DMA function is also implemented allowing
efficient data transfer to LCD modules that include a built-in VRAM LCD driver.
In addition, the embedded Graphics Engine (GE) provides rich graphic features, such as drawing functions for dots,
straight lines, triangles, rectangles, and circles, resizing, and rotation, that can be used simply by calling commands.
The GE also supports drawing of lossless compressed image data, this makes it possible to reduce CPU load and
image data ROM size.
As for DSP functions, a 32-bit ×32-bit multiplier (MUL) and a 16-bit ÷16-bit divider (DIV) are implemented.
These functions help reduce CPU load for ADPCM audio data playback processing. Also the embedded I2S inter-
face module is capable of being used to connect an external audio DAC.
The S1C33L26 has adopted the EPSON SoC (System on Chip) design technology using 0.18 µm low power CMOS
process to install these features.
Features1.1
The features of the S1C33L26 are outlined below.
Technology
•0.18 µm AL-4-layers mixed analog low power CMOS process technology
CPU
•EPSON original C33 PE 32-bit RISC CPU-Core
•Maximum operating frequency: 60 MHz (36 MHz in SDRAM double frequency mode)
•Internal two-stage pipeline
•Instruction set: 125 instructions (16-bit fixed length)
•Dual AMBA bus system for CPU and GE
DSP
•Multiplier (MUL)
- 32 ×32 bits (seven cycles) or 16 ×16 bits (five cycles)
•Divider (DIV)
- 16 ÷16 bits (18 cycles)
Internal Memories
•IRAM (Internal RAM)
- 12K bytes
•IVRAM (Internal VRAM)
- 20K bytes
- Configurable as a 32K-byte general-purpose RAM sequentially addressed with IRAM
•Cache RAM
- 1K bytes (instruction cache RAM)
- 1K bytes (data cache RAM)
- Usable as a general-purpose RAM when not used as cache RAM
•DSTRAM (DMA descriptor RAM)/LUTRAM (look-up table RAM)
- 512 bytes (can exclusively be used as either DSTRAM or LUTRAM.)
- DMA descriptor RAM for storing DMA control table (128 ×32 bits)