Epson S1C17M20 User manual

Rev. 1.0
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M20/M21/M22/M23/M24/M25
Technical Manual

©
SEIKO EPSON CORPORATION 2017, All rights reserved.
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PREFACE
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TECHNICAL MANUAL (Rev. 1.0)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17M20/M21/
M22/M23/M24/M25. This document describes the functions of the IC, embedded peripheral circuit operations,
and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 S1C17M20/M23 Pin Configuration Diagram .................................................... 1-4
1.3.2 S1C17M21/M24 Pin Configuration Diagram .................................................... 1-6
1.3.3 S1C17M22/M25 Pin Configuration Diagram .................................................... 1-7
1.3.4 Pin Descriptions................................................................................................ 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG).................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode......................................................................... 2-1
2.2 System Reset Controller (SRC)....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin............................................................................................................ 2-2
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-3
2.3 Clock Generator (CLG).................................................................................................... 2-4
2.3.1 Overview ........................................................................................................... 2-4
2.3.2 Input/Output Pins ............................................................................................. 2-5
2.3.3 Clock Sources .................................................................................................. 2-5
2.3.4 Operations ........................................................................................................ 2-8
2.4 Operating Mode ............................................................................................................. 2-12
2.4.1 Initial Boot Sequence....................................................................................... 2-12
2.4.2 Transition between Operating Modes.............................................................. 2-12
2.5 Interrupts........................................................................................................................ 2-14
2.6 Control Registers ........................................................................................................... 2-14
PWG VD1 Regulator Control Register ....................................................................................... 2-14
CLG System Clock Control Register........................................................................................ 2-15
CLG Oscillation Control Register ............................................................................................. 2-16
CLG OSC1 Control Register .................................................................................................... 2-17
CLG OSC3 Control Register .................................................................................................... 2-18
CLG Interrupt Flag Register ..................................................................................................... 2-19
CLG Interrupt Enable Register ................................................................................................. 2-20
CLG FOUT Control Register..................................................................................................... 2-21
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-2
3.3.3 List of Debugger Input/Output Pins.................................................................. 3-3

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3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-3
3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers................................................................................ 4-3
4.5.1 System-Protect Function.................................................................................. 4-8
4.6 Control Registers ............................................................................................................ 4-8
MISC System Protect Register ................................................................................................. 4-8
MISC IRAM Size Register.......................................................................................................... 4-8
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-3
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-3
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-3
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-4
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-4
6.4 Operations ...................................................................................................................... 6-4
6.4.1 Initialization ....................................................................................................... 6-4
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6

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6.6 Control Registers ............................................................................................................ 6-7
PxPort Data Register................................................................................................................ 6-7
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-8
PxPort Interrupt Flag Register.................................................................................................. 6-8
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-9
PxPort Mode Select Register ................................................................................................... 6-9
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register .................................................................................................. 6-10
P Port Interrupt Flag Group Register........................................................................................ 6-11
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-12
6.7.1 P0 Port Group.................................................................................................. 6-12
6.7.2 P1 Port Group.................................................................................................. 6-14
6.7.3 P2 Port Group.................................................................................................. 6-17
6.7.4 P3 Port Group.................................................................................................. 6-19
6.7.5 P4 Port Group.................................................................................................. 6-21
6.7.6 Pd Port Group.................................................................................................. 6-23
6.7.7 Common Registers between Port Groups....................................................... 6-24
7 Universal Port Multiplexer (UPMUX)...........................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Peripheral Circuit I/O Function Assignment.................................................................... 7-1
7.3 Control Registers ............................................................................................................ 7-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 7-2
8 Watchdog Timer (WDT2)..............................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Clock Settings................................................................................................................. 8-1
8.2.1 WDT2 Operating Clock..................................................................................... 8-1
8.2.2 Clock Supply in DEBUG Mode......................................................................... 8-1
8.3 Operations ...................................................................................................................... 8-2
8.3.1 WDT2 Control ................................................................................................... 8-2
8.3.2 Operations in HALT and SLEEP Modes............................................................ 8-3
8.4 Control Registers ............................................................................................................ 8-3
WDT2 Clock Control Register ................................................................................................... 8-3
WDT2 Control Register ............................................................................................................. 8-4
WDT2 Counter Compare Match Register ................................................................................. 8-4
9 Real-Time Clock (RTCA) ..............................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Output Pin and External Connection .............................................................................. 9-1
9.2.1 Output Pin......................................................................................................... 9-1
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 RTCA Operating Clock ..................................................................................... 9-2
9.3.2 Theoretical Regulation Function....................................................................... 9-2
9.4 Operations ...................................................................................................................... 9-3
9.4.1 RTCA Control ................................................................................................... 9-3
9.4.2 Real-Time Clock Counter Operations............................................................... 9-4
9.4.3 Stopwatch Control............................................................................................ 9-4
9.4.4 Stopwatch Count-up Pattern ........................................................................... 9-4
9.5 Interrupts......................................................................................................................... 9-5
9.6 Control Registers ............................................................................................................ 9-6
RTC Control Register ................................................................................................................ 9-6
RTC Second Alarm Register ..................................................................................................... 9-7

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RTC Hour/Minute Alarm Register.............................................................................................. 9-8
RTC Stopwatch Control Register .............................................................................................. 9-8
RTC Second/1Hz Register ........................................................................................................ 9-9
RTC Hour/Minute Register ....................................................................................................... 9-10
RTC Month/Day Register ......................................................................................................... 9-11
RTC Year/Week Register .......................................................................................................... 9-11
RTC Interrupt Flag Register...................................................................................................... 9-12
RTC Interrupt Enable Register ................................................................................................. 9-13
10 Supply Voltage Detector (SVD3)...............................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pins and External Connection ............................................................................ 10-2
10.2.1 Input Pins....................................................................................................... 10-2
10.2.2 External Connection ...................................................................................... 10-2
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 SVD3 Operating Clock................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-3
10.4 Operations ................................................................................................................... 10-3
10.4.1 SVD3 Control ................................................................................................. 10-3
10.4.2 SVD3 Operations ........................................................................................... 10-4
10.5 SVD3 Interrupt and Reset ............................................................................................ 10-4
10.5.1 SVD3 Interrupt ............................................................................................... 10-4
10.5.2 SVD3 Reset.................................................................................................... 10-5
10.6 Control Registers ......................................................................................................... 10-5
SVD3 Clock Control Register ................................................................................................... 10-5
SVD3 Control Register ............................................................................................................. 10-6
SVD3 Status and Interrupt Flag Register ................................................................................. 10-7
SVD3 Interrupt Enable Register ............................................................................................... 10-8
11 16-bit Timers (T16).....................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input Pin....................................................................................................................... 11-1
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 T16 Operating Clock...................................................................................... 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-2
11.3.4 Event Counter Clock...................................................................................... 11-2
11.4 Operations ................................................................................................................... 11-2
11.4.1 Initialization .................................................................................................... 11-2
11.4.2 Counter Underflow ........................................................................................ 11-3
11.4.3 Operations in Repeat Mode........................................................................... 11-3
11.4.4 Operations in One-shot Mode ....................................................................... 11-3
11.4.5 Counter Value Read....................................................................................... 11-4
11.5 Interrupt........................................................................................................................ 11-4
11.6 Control Registers ......................................................................................................... 11-4
T16 Ch.nClock Control Register ............................................................................................. 11-4
T16 Ch.nMode Register .......................................................................................................... 11-5
T16 Ch.nControl Register........................................................................................................ 11-5
T16 Ch.nReload Data Register................................................................................................ 11-6
T16 Ch.nCounter Data Register .............................................................................................. 11-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 11-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 11-7

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12 UART (UART3)............................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Input Pin Pull-Up Function............................................................................. 12-2
12.2.4 Output Pin Open-Drain Output Function ...................................................... 12-2
12.2.5 Input/Output Signal Inverting Function.......................................................... 12-2
12.3 Clock Settings.............................................................................................................. 12-2
12.3.1 UART3 Operating Clock ................................................................................ 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-3
12.3.3 Clock Supply in DEBUG Mode...................................................................... 12-3
12.3.4 Baud Rate Generator..................................................................................... 12-3
12.4 Data Format ................................................................................................................. 12-3
12.5 Operations ................................................................................................................... 12-4
12.5.1 Initialization .................................................................................................... 12-4
12.5.2 Data Transmission ......................................................................................... 12-5
12.5.3 Data Reception .............................................................................................. 12-6
12.5.4 IrDA Interface................................................................................................. 12-7
12.5.5 Carrier Modulation ......................................................................................... 12-7
12.6 Receive Errors.............................................................................................................. 12-8
12.6.1 Framing Error ................................................................................................. 12-8
12.6.2 Parity Error..................................................................................................... 12-8
12.6.3 Overrun Error ................................................................................................. 12-9
12.7 Interrupts...................................................................................................................... 12-9
12.8 Control Registers ......................................................................................................... 12-9
UART3 Ch.nClock Control Register ........................................................................................ 12-9
UART3 Ch.nMode Register.................................................................................................... 12-10
UART3 Ch.nBaud–Rate Register ........................................................................................... 12-11
UART3 Ch.nControl Register ................................................................................................. 12-12
UART3 Ch.nTransmit Data Register ....................................................................................... 12-12
UART3 Ch.nReceive Data Register........................................................................................ 12-12
UART3 Ch.nStatus and Interrupt Flag Register ..................................................................... 12-13
UART3 Ch.nInterrupt Enable Register.................................................................................... 12-14
UART3 Ch.nCarrier Waveform Register ................................................................................. 12-14
13 Synchronous Serial Interface (SPIA)........................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Pin Functions in Master Mode and Slave Mode............................................ 13-3
13.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 13-3
13.3 Clock Settings.............................................................................................................. 13-3
13.3.1 SPIA Operating Clock.................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode...................................................................... 13-4
13.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 13-4
13.4 Data Format ................................................................................................................. 13-5
13.5 Operations ................................................................................................................... 13-5
13.5.1 Initialization .................................................................................................... 13-5
13.5.2 Data Transmission in Master Mode ............................................................... 13-5
13.5.3 Data Reception in Master Mode.................................................................... 13-7
13.5.4 Terminating Data Transfer in Master Mode.................................................... 13-8

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13.5.5 Data Transfer in Slave Mode.......................................................................... 13-8
13.5.6 Terminating Data Transfer in Slave Mode ..................................................... 13-10
13.6 Interrupts..................................................................................................................... 13-10
13.7 Control Registers ........................................................................................................ 13-11
SPIA Ch.nMode Register ....................................................................................................... 13-11
SPIA Ch.nControl Register..................................................................................................... 13-12
SPIA Ch.nTransmit Data Register .......................................................................................... 13-13
SPIA Ch.nReceive Data Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Flag Register ........................................................................................... 13-13
SPIA Ch.nInterrupt Enable Register ....................................................................................... 13-14
14 I2C (I2C).......................................................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins and External Connections .............................................................. 14-2
14.2.1 List of Input/Output Pins................................................................................ 14-2
14.2.2 External Connections .................................................................................... 14-2
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 I2C Operating Clock ...................................................................................... 14-3
14.3.2 Clock Supply in DEBUG Mode...................................................................... 14-3
14.3.3 Baud Rate Generator..................................................................................... 14-3
14.4 Operations ................................................................................................................... 14-4
14.4.1 Initialization .................................................................................................... 14-4
14.4.2 Data Transmission in Master Mode ............................................................... 14-5
14.4.3 Data Reception in Master Mode.................................................................... 14-7
14.4.4 10-bit Addressing in Master Mode ................................................................ 14-9
14.4.5 Data Transmission in Slave Mode................................................................. 14-10
14.4.6 Data Reception in Slave Mode ..................................................................... 14-12
14.4.7 Slave Operations in 10-bit Address Mode.................................................... 14-14
14.4.8 Automatic Bus Clearing Operation ............................................................... 14-14
14.4.9 Error Detection.............................................................................................. 14-15
14.5 Interrupts..................................................................................................................... 14-16
14.6 Control Registers ........................................................................................................ 14-17
I2C Ch.nClock Control Register............................................................................................. 14-17
I2C Ch.nMode Register.......................................................................................................... 14-18
I2C Ch.nBaud-Rate Register.................................................................................................. 14-18
I2C Ch.nOwn Address Register ............................................................................................. 14-18
I2C Ch.nControl Register ....................................................................................................... 14-19
I2C Ch.nTransmit Data Register ............................................................................................. 14-20
I2C Ch.nReceive Data Register.............................................................................................. 14-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 14-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 14-21
15 16-bit PWM Timers (T16B) ........................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins......................................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-3
15.3.1 T16B Operating Clock ................................................................................... 15-3
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-3
15.3.3 Clock Supply in DEBUG Mode...................................................................... 15-3
15.3.4 Event Counter Clock...................................................................................... 15-3
15.4 Operations ................................................................................................................... 15-4
15.4.1 Initialization .................................................................................................... 15-4
15.4.2 Counter Block Operations ............................................................................. 15-5
15.4.3 Comparator/Capture Block Operations......................................................... 15-8
15.4.4 TOUT Output Control ................................................................................... 15-16

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15.5 Interrupt....................................................................................................................... 15-22
15.6 Control Registers ........................................................................................................ 15-22
T16B Ch.nClock Control Register.......................................................................................... 15-22
T16B Ch.nCounter Control Register ...................................................................................... 15-23
T16B Ch.nMax Counter Data Register................................................................................... 15-24
T16B Ch.nTimer Counter Data Register................................................................................. 15-24
T16B Ch.nCounter Status Register........................................................................................ 15-25
T16B Ch.nInterrupt Flag Register........................................................................................... 15-26
T16B Ch.nInterrupt Enable Register ...................................................................................... 15-27
T16B Ch.nComparator/Capture mControl Register.............................................................. 15-28
T16B Ch.nCompare/Capture mData Register....................................................................... 15-30
16 Sound Generator (SNDA) ..........................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Output Pins and External Connections........................................................................ 16-2
16.2.1 List of Output Pins ......................................................................................... 16-2
16.2.2 Output Pin Drive Mode .................................................................................. 16-2
16.2.3 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 SNDA Operating Clock.................................................................................. 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Buzzer Output in Normal Buzzer Mode......................................................... 16-3
16.4.3 Buzzer Output in One-shot Buzzer Mode...................................................... 16-6
16.4.4 Output in Melody Mode................................................................................. 16-7
16.5 Interrupts...................................................................................................................... 16-9
16.6 Control Registers ......................................................................................................... 16-9
SNDA Clock Control Register .................................................................................................. 16-9
SNDA Select Register ............................................................................................................. 16-10
SNDA Control Register............................................................................................................ 16-11
SNDA Data Register................................................................................................................ 16-11
SNDA Interrupt Flag Register.................................................................................................. 16-12
SNDA Interrupt Enable Register.............................................................................................. 16-13
17 IR Remote Controller (REMC3) ................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input/Output Pins and External Connections .............................................................. 17-1
17.2.1 Output Pin...................................................................................................... 17-1
17.2.2 External Connections .................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-2
17.3.1 REMC3 Operating Clock ............................................................................... 17-2
17.3.2 Clock Supply in SLEEP Mode ....................................................................... 17-2
17.3.3 Clock Supply in DEBUG Mode...................................................................... 17-2
17.4 Operations ................................................................................................................... 17-2
17.4.1 Initialization .................................................................................................... 17-2
17.4.2 Data Transmission Procedures...................................................................... 17-3
17.4.3 REMO Output Waveform ............................................................................... 17-3
17.4.4 Continuous Data Transmission and Compare Buffers................................... 17-5
17.5 Interrupts...................................................................................................................... 17-6
17.6 Application Example: Driving EL Lamp........................................................................ 17-7
17.7 Control Registers ......................................................................................................... 17-7
REMC3 Clock Control Register................................................................................................ 17-7

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REMC3 Data Bit Counter Control Register .............................................................................. 17-8
REMC3 Data Bit Counter Register........................................................................................... 17-9
REMC3 Data Bit Active Pulse Length Register....................................................................... 17-10
REMC3 Data Bit Length Register............................................................................................ 17-10
REMC3 Status and Interrupt Flag Register............................................................................. 17-10
REMC3 Interrupt Enable Register ........................................................................................... 17-11
REMC3 Carrier Waveform Register......................................................................................... 17-11
REMC3 Carrier Modulation Control Register .......................................................................... 17-12
18 R/F Converter (RFC)..................................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Input/Output Pins and External Connections .............................................................. 18-2
18.2.1 List of Input/Output Pins................................................................................ 18-2
18.2.2 External Connections .................................................................................... 18-2
18.3 Clock Settings.............................................................................................................. 18-3
18.3.1 RFC Operating Clock..................................................................................... 18-3
18.3.2 Clock Supply in SLEEP Mode ....................................................................... 18-3
18.3.3 Clock Supply in DEBUG Mode...................................................................... 18-3
18.4 Operations ................................................................................................................... 18-3
18.4.1 Initialization .................................................................................................... 18-3
18.4.2 Operating Modes........................................................................................... 18-4
18.4.3 RFC Counters ................................................................................................ 18-4
18.4.4 Converting Operations and Control Procedure ............................................. 18-5
18.4.5 CR Oscillation Frequency Monitoring Function............................................. 18-7
18.5 Interrupts...................................................................................................................... 18-7
18.6 Control Registers ......................................................................................................... 18-8
RFC Ch.nClock Control Register ............................................................................................ 18-8
RFC Ch.nControl Register....................................................................................................... 18-8
RFC Ch.nOscillation Trigger Register...................................................................................... 18-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 18-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 18-10
RFC Ch.nInterrupt Flag Register............................................................................................ 18-11
RFC Ch.nInterrupt Enable Register........................................................................................ 18-11
19 12-bit A/D Converter (ADC12A)................................................................................19-1
19.1 Overview ...................................................................................................................... 19-1
19.2 Input Pins and External Connections........................................................................... 19-2
19.2.1 List of Input Pins............................................................................................ 19-2
19.2.2 External Connections .................................................................................... 19-2
19.3 Clock Settings.............................................................................................................. 19-2
19.3.1 ADC12A Operating Clock.............................................................................. 19-2
19.3.2 Sampling Time............................................................................................... 19-2
19.4 Operations ................................................................................................................... 19-3
19.4.1 Initialization .................................................................................................... 19-3
19.4.2 Conversion Start Trigger Source.................................................................... 19-3
19.4.3 Conversion Mode and Analog Input Pin Settings.......................................... 19-4
19.4.4 A/D Conversion Operations and Control Procedures.................................... 19-4
19.5 Interrupts...................................................................................................................... 19-6
19.6 Control Registers ......................................................................................................... 19-6
ADC12A Ch.nControl Register ................................................................................................ 19-6
ADC12A Ch.nTrigger/Analog Input Select Register ................................................................ 19-7
ADC12A Ch.nConfiguration Register ...................................................................................... 19-8
ADC12A Ch.nInterrupt Flag Register ...................................................................................... 19-9
ADC12A Ch.nInterrupt Enable Register ................................................................................. 19-10
ADC12A Ch.nResult Register m............................................................................................. 19-10

CONTENTS
xSeiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
20 Multiplier/Divider (COPRO2).....................................................................................20-1
20.1 Overview ...................................................................................................................... 20-1
20.2 Operation Mode and Output Mode.............................................................................. 20-1
20.3 Multiplication................................................................................................................ 20-2
20.4 Division......................................................................................................................... 20-3
20.5 MAC ............................................................................................................................. 20-5
20.6 Reading Operation Results .......................................................................................... 20-7
21 Electrical Characteristics .........................................................................................21-1
21.1 Absolute Maximum Ratings ......................................................................................... 21-1
21.2 Recommended Operating Conditions ......................................................................... 21-1
21.3 Current Consumption................................................................................................... 21-2
21.4 System Reset Controller (SRC) Characteristics........................................................... 21-4
21.5 Clock Generator (CLG) Characteristics........................................................................ 21-4
21.6 Flash Memory Characteristics ..................................................................................... 21-7
21.7 Input/Output Port (PPORT) Characteristics ................................................................. 21-7
21.8 Supply Voltage Detector (SVD3) Characteristics ......................................................... 21-8
21.9 UART (UART3) Characteristics ................................................................................... 21-10
21.10 Synchronous Serial Interface (SPIA) Characteristics ................................................ 21-10
21.11 I2C (I2C) Characteristics............................................................................................ 21-11
21.12 R/F Converter (RFC) Characteristics......................................................................... 21-12
21.13 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 21-13
22 Basic External Connection Diagram .......................................................................22-1
23 Package......................................................................................................................23-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC)............................................................... AP-A-1
0x4020 Power Generator (PWG)............................................................ AP-A-1
0x4040–0x4050 Clock Generator (CLG).............................................................. AP-A-1
0x4080–0x4094 Interrupt Controller (ITC) ........................................................... AP-A-2
0x40a0–0x40a4 Watchdog Timer (WDT2) ........................................................... AP-A-4
0x40c0–0x40d2 Real-time Clock (RTCA) ............................................................ AP-A-4
0x4100–0x4106 Supply Voltage Detector (SVD3) ............................................... AP-A-6
0x4160–0x416c 16-bit Timer (T16) Ch.0 ............................................................. AP-A-6
0x41b0 Flash Controller (FLASHC) ........................................................ AP-A-7
0x4200–0x42e2 I/O Ports (PPORT) ..................................................................... AP-A-7
0x4300–0x431e Universal Port Multiplexer (UPMUX) ........................................ AP-A-17
0x4380–0x4390 UART (UART3) Ch.0 ................................................................. AP-A-19
0x43a0–0x43ac 16-bit Timer (T16) Ch.1 ............................................................ AP-A-20
0x43b0–0x43ba Synchronous Serial Interface (SPIA) Ch.0................................ AP-A-20
0x43c0–0x43d2 I2C (I2C) Ch.0 ........................................................................... AP-A-21
0x5000–0x501a 16-bit PWM Timer (T16B) Ch.0 ................................................ AP-A-22
0x5040–0x505a 16-bit PWM Timer (T16B) Ch.1 ................................................ AP-A-23
0x5200–0x5210 UART (UART3) Ch.1 ................................................................. AP-A-25
0x5260–0x526c 16-bit Timer (T16) Ch.2 ............................................................ AP-A-26
0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1................................ AP-A-27
0x5300–0x530a Sound Generator (SNDA) ......................................................... AP-A-27
0x5320–0x5332 IR Remote Controller (REMC3) ................................................ AP-A-28
0x5440–0x5450 R/F Converter (RFC) Ch.0 (S1C17M22/M25)........................... AP-A-29
0x5460–0x5470 R/F Converter (RFC) Ch.1 (S1C17M22/M25)........................... AP-A-30
0x5480–0x548c 16-bit Timer (T16) Ch.3 ............................................................ AP-A-31

CONTENTS
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation xi
TECHNICAL MANUAL (Rev. 1.0)
0x54a0–0x54ba 12-bit A/D Converter (ADC12A) ............................................... AP-A-31
0xffff90 Debugger (DBG)....................................................................... AP-A-33
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History

1 OVERVIEW
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation 1-1
TECHNICAL MANUAL (Rev. 1.0)
1 Overview
The S1C17M20/M21/M22/M23/M24/M25 is a 16-bit embedded Flash MCU that features low power consump-
tion. The embedded Flash memory can also be used as an EEPROM emulation data memory via software. The
S1C17M20/M21/M22/M23/M24/M25 includes various serial interfaces, an A/D converter, and various timers as
well as a high-performance 16-bit CPU. It is suitable for applications that require an A/D conversion function, such
as household equipment and FA products.
1.1 Features
Table 1.1.1 Features
Model S1C17M20/M23 S1C17M21/M24 S1C17M22/M25
24-pin PKG 32-pin PKG
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Other On-chip debugger
Embedded Flash memory
Capacity
(for both instructions and data)
16K bytes (S1C17M20/M21/M22)
32K bytes (S1C17M23/M24/M25)
Erase/program count 1,000 times (min.) *Programming by the debugging tool ICDmini
Other Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Flash programming voltage can be generated internally.
Embedded RAM
Capacity 2K bytes
Clock generator (CLG)
System clock source 4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency
(operating frequency)
21 MHz (max.)
IOSC oscillator circuit
(boot clock source)
700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by the CPU)
OSC1 oscillator circuit
– 32.768 kHz (typ.) crystal oscillator
32 kHz (typ.) embedded oscillator
– Oscillation stop detection circuit included
OSC3 oscillator circuit – 21 MHz (max.) crystal/ceramic oscillator
12, 16, and 20 MHz-switchable embedded oscillator
– Auto-trimming function for the embedded oscillator
EXOSC clock input 21 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of
general-
purpose
ports
I/O port 17 bits (max.) 23 bits (max.) 39 bits (max.)
Output port 1 bit (max.)
Other Pins are shared with the peripheral I/O.
Number of input interrupt ports 15 bits (max.) 19 bits (max.) 35 bits (max.)
Number of ports that support
universal port multiplexer (UPMUX)
15 bits 19 bits 32 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 4 channels
Generates the SPIA master clocks and the ADC12A trigger signal.
16-bit PWM timer (T16B) 2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
Supply voltage detector (SVD3)
Detection voltage VDD or external voltage (one external voltage input port is provided and an external voltage level
can be detected even if it exceeds VDD.)
Detection level VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Model S1C17M20/M23 S1C17M21/M24 S1C17M22/M25
24-pin PKG 32-pin PKG
Serial interfaces
UART (UART3) 2 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface
(SPIA)
2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
I2C (I2C) 1 channel
Baud-rate generator included
Sound generator (SNDA)
Buzzer output function 512 Hz to 16 kHz output frequencies
One-shot output function
Melody generation function Pitch: 128 Hz to 16 kHz ≈ C3 to C6
Duration: 7 notes/rests (Half note/rest to thirty-second note/rest)
Tempo: 16 tempos (30 to 480)
Tie/slur may be specified.
IR remote controller (REMC3)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated for an application example.
Output inversion function
R/F converter (RFC)
Conversion method – CR oscillation type
with 24-bit counters
Number of conversion channels 2 channels (Up to two sensors
can be connected to each
channel.)
Supported sensors
DC-bias resistive sensors
12-bit A/D converter (ADC12A)
Conversion method Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal input ports 4 ports 6 ports 8 ports
Multiplier/divider (COPRO2)
Arithmetic functions 16-bit ×16-bit multiplier
16-bit ×16-bit + 32-bit multiply and accumulation unit
32-bit ÷32-bit divider
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Brownout reset Reset when the power supply voltage drops.
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be enabled/disabled
using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset
Reset when the supply voltage detector detects the set voltage level (can be enabled/disabled us-
ing a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable
interrupt
External int. 1 system (8 levels)
Internal int. 17 systems (8 levels) 19 systems (8 levels)
Power supply voltage
VDD operating voltage 1.8 to 5.5 V
VDD operating voltage for Flash
programming
2.4 to 5.5 V (When VPP (7.5 V) is supplied externally)
2.7 to 5.5 V (When VPP is generated internally)
Operating temperature
Operating temperature range -40 to 85°C
Current consumption (typ. value)
SLEEP mode 0.36 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
HALT mode 0.7 µA
OSC1 = 32.768 kHz (crystal oscillator), RTC = ON
RUN mode 5 µA
OSC1 = 32.768 kHz (crystal oscillator), RTC = ON, CPU = OSC1
160 µA
OSC3 = 1 MHz (ceramic oscillator), OSC1 = 32.768 kHz (crystal oscillator), RTC = ON, CPU = OSC3
Shipping form
Package
(Lead pitch)
SQFN4-24
(0.5 mm)
SQFN5-32
(0.5 mm)
TQFP12-32pin
(0.8 mm)
TQFP12-48pin
(0.5 mm)

1 OVERVIEW
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation 1-3
TECHNICAL MANUAL (Rev. 1.0)
1.2 Block Diagram
CPU core & debugger
(S1C17)
Internal RAM
2KB
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Multiplier/divider
(COPRO2)
Coprocessor bus
Instruction bus
16-bit internal bus
Power generator
(PWG)
VDD
VSS
VD1
SDA0
SCL0
EXSVD0
P00–07
P10–17
P20–27
P30–37
P40–42
PD0–D1
PD2
PD3–D4
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
I2C
(I2C)
1 Ch.
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
4 Ch.
TOUT00–01
TOUT10–11
CAP00–01
CAP10–11
EXCL00–01
EXCL10–11
16-bit PWM timer
(T16B)
2Ch.
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
Synchronous
serial interface
(SPIA)
2 Ch.
USIN0–1
USOUT0–1
UART
(UART3)
2 Ch.
Flash memory
16KB (M20/M21/M22)
32KB (M23/M24/M25)
VPP
Flash
programming
voltage booster
IOSC
oscillator
OSC1
oscillator
EXOSC
input circuit
Clock generator
(CLG)
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC
OSC3
oscillator
RTC1S
Real-time clock
(RTCA)
Power-on reset
(POR)
System reset controller
(SRC)
#RESET
Brownout reset
(BOR)
∗
∗
∗
REMO
CLPLS
IR remote
controller
(REMC3)
BZOUT
#BZOUT
Sound generator
(SNDA)
R/F converter
(RFC)
2 Ch.
RFIN0–1
REF0–1
SENA0–1
SENB0–1
#ADTRG0
ADIN00–07
VREFA0
12-bit A/D
converter
(ADC12A)
1 Ch.
∗
∗
*The pin configuration and peripheral circuit function depends on the model. For detailed information, refer to Section 1.3, “Pins.”
Figure 1.2.1 S1C17M20/M21/M22/M23/M24/M25 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
1.3 Pins
1.3.1 S1C17M20/M23 Pin Configuration Diagram
SQFN4-24
1 2 3 4 5 6
18 17 16 15 14 13
P14 P15
VSS
P24 P25 P26
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
VSS
P24/EXCL10/UPMUX/ADIN03 P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P00 PD2 PD1 PD0 VDD #RESET
P00/EXCL00/UPMUX DCLK/PD2 DSIO/PD1 DST2/PD0 VDD
#RESET
12
11
10
9
8
7
19
20
21
22
23
24
VSS
VD1
P32
P31
P30
P27
VSS
VD1
P32/RTC1S/UPMUX/EXSVD0
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
Pin
name
P01
P02
P03
VPP
P12
P13
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P03/#BZOUT/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX (Top View)
S1C17M20
S1C17M23
Figure 1.3.1.1 S1C17M20/M23 Pin Configuration Diagram (SQFN4-24)

1 OVERVIEW
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation 1-5
TECHNICAL MANUAL (Rev. 1.0)
SQFN5-32
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
P14 P15
VSS
P22 P23 P24 P25 P26
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
VSS
P22/UPMUX/ADIN05 P23/UPMUX/ADIN04
P24/EXCL10/UPMUX/ADIN03 P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P00 PD2 PD1 PD0 PD3 PD4 VDD #RESET
P00/EXCL00/UPMUX DCLK/PD2 DSIO/PD1 DST2/PD0 PD3/OSC3 PD4/OSC4 VDD
#RESET
16
15
14
13
12
11
10
9
(Top View)
25
26
27
28
29
30
31
32
VSS
VD1
OSC2
OSC1
P32
P31
P30
P27
VSS
VD1
OSC2
OSC1
P32/RTC1S/UPMUX/EXSVD0
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
Pin
name
P01
P02
P03
P10
P11
VPP
P12
P13
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P03/#BZOUT/UPMUX
P10/UPMUX
P11/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
S1C17M20
S1C17M23
Figure 1.3.1.2 S1C17M20/M23 Pin Configuration Diagram (SQFN5-32)

1 OVERVIEW
1-6 Seiko Epson Corporation S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
1.3.2 S1C17M21/M24 Pin Configuration Diagram
TQFP12-32pin
P14 P15
VSS
P22 P23 P24 P25 P26
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
VSS
P22/UPMUX/ADIN05 P23/UPMUX/ADIN04
P24/EXCL10/UPMUX/ADIN03 P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P00 PD2 PD1 PD0 PD3 PD4 VDD #RESET
P00/EXCL00/UPMUX DCLK/PD2 DSIO/PD1 DST2/PD0 PD3/OSC3 PD4/OSC4 VDD
#RESET
S1C17M21
S1C17M24
VSS
VD1
OSC2
OSC1
P32
P31
P30
P27
VSS
VD1
OSC2
OSC1
P32/RTC1S/UPMUX/EXSVD0
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
Pin name
P01
P02
P03
P10
P11
VPP
P12
P13
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P03/#BZOUT/UPMUX
P10/UPMUX
P11/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32
Figure 1.3.2.1 S1C17M21/M24 Pin Configuration Diagram (TQFP12-32pin)

1 OVERVIEW
S1C17M20/M21/M22/M23/M24/M25 Seiko Epson Corporation 1-7
TECHNICAL MANUAL (Rev. 1.0)
1.3.3 S1C17M22/M25 Pin Configuration Diagram
TQFP12-48pin
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
P14 P15
VSS
P16 P17 P20 P21 P22 P23 P24 P25 P26
P14/#ADTRG0/UPMUX
P15/CLPLS/UPMUX
VSS
P16/UPMUX P17/UPMUX
P20/UPMUX/ADIN07 P21/UPMUX/ADIN06 P22/UPMUX/ADIN05 P23/UPMUX/ADIN04
P24/EXCL10/UPMUX/ADIN03 P25/EXCL11/UPMUX/ADIN02
P26/UPMUX/ADIN01
P00 PD2 PD1 PD0 P42 P41 P40 P37 PD3 PD4 VDD #RESET
P00/EXCL00/UPMUX DCLK/PD2 DSIO/PD1 DST2/PD0 P42/RFIN1 P41/REF1 P40/SENA1 P37/SENB1/UPMUX PD3/OSC3 PD4/OSC4 VDD
#RESET
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
VSS
VD1
OSC2
OSC1
P36
P35
P34
P33
P32
P31
P30
P27
VSS
VD1
OSC2
OSC1
P36/RFIN0/UPMUX
P35/REF0/UPMUX
P34/SENA0/UPMUX
P33/SENB0/UPMUX
P32/RTC1S/UPMUX/EXSVD0
P31/EXOSC/UPMUX
P30/UPMUX/VREFA0
P27/UPMUX/ADIN00
Pin name
P01
P02
P03
P10
P04
P05
P06
P07
P11
VPP
P12
P13
Port function
or signal
assignment
P01/EXCL01/UPMUX
P02/BZOUT/UPMUX
P03/#BZOUT/UPMUX
P10/UPMUX
P04/RFCLKO0/UPMUX
P05/RFCLKO1/UPMUX
P06/UPMUX
P07/UPMUX
P11/UPMUX
VPP
P12/REMO/UPMUX
P13/FOUT/UPMUX
S1C17M22
S1C17M25
Figure 1.3.3.1 S1C17M22/M25 Pin Configuration Diagram (TQFP12-48pin)