Epson S1C17M01 User manual

Rev. 1.2
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M01
Technical Manual

©
SEIKO EPSON CORPORATION 2021, All rights reserved.
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PREFACE
S1C17M01 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.2)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17M01. This
document describes the functions of the IC, embedded peripheral circuit operations, and their control methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

CONTENTS
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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (TQFP13-64PIN) .................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip).................................................................... 1-5
1.3.3 Pin Descriptions................................................................................................ 1-6
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG).................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode......................................................................... 2-1
2.2 System Reset Controller (SRC)....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin............................................................................................................ 2-2
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-3
2.3 Clock Generator (CLG).................................................................................................... 2-3
2.3.1 Overview ........................................................................................................... 2-3
2.3.2 Input/Output Pins ............................................................................................. 2-4
2.3.3 Clock Sources .................................................................................................. 2-4
2.3.4 Operations ........................................................................................................ 2-6
2.4 Operating Mode ............................................................................................................. 2-10
2.4.1 Initial Boot Sequence....................................................................................... 2-10
2.4.2 Transition between Operating Modes.............................................................. 2-10
2.5 Interrupts........................................................................................................................ 2-11
2.6 Control Registers ........................................................................................................... 2-12
PWG VD1 Regulator Control Register ....................................................................................... 2-12
CLG System Clock Control Register........................................................................................ 2-12
CLG Oscillation Control Register ............................................................................................. 2-13
CLG IOSC Control Register ..................................................................................................... 2-14
CLG OSC1 Control Register .................................................................................................... 2-15
CLG Interrupt Flag Register ..................................................................................................... 2-16
CLG Interrupt Enable Register ................................................................................................. 2-17
CLG FOUT Control Register..................................................................................................... 2-17
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-3
3.3.3 List of debugger input/output pins ................................................................... 3-3
3.3.4 External Connection ......................................................................................... 3-3

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3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-3
4.3.4 Flash Security Function .................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Display Data RAM ........................................................................................................... 4-4
4.6 Peripheral Circuit Control Registers................................................................................ 4-4
4.6.1 System-Protect Function.................................................................................. 4-7
4.7 Control Registers ............................................................................................................ 4-7
MISC System Protect Register ................................................................................................. 4-7
MISC IRAM Size Register.......................................................................................................... 4-7
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-2
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-3
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-4
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-2
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-2
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-3
6.4 Operations ...................................................................................................................... 6-3
6.4.1 Initialization ....................................................................................................... 6-3
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6

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6.6 Control Registers ............................................................................................................ 6-6
PxPort Data Register................................................................................................................ 6-6
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-7
PxPort Interrupt Flag Register.................................................................................................. 6-7
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-8
PxPort Mode Select Register ................................................................................................... 6-8
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register........................................................................................ 6-10
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-11
6.7.1 P0 Port Group.................................................................................................. 6-11
6.7.2 P1 Port Group.................................................................................................. 6-12
6.7.3 P2 Port Group.................................................................................................. 6-12
6.7.4 P3 Port Group.................................................................................................. 6-13
6.7.5 P4 Port Group.................................................................................................. 6-14
6.7.6 P5 Port Group.................................................................................................. 6-15
6.7.7 Pd Port Group.................................................................................................. 6-16
6.7.8 Common Registers between Port Groups....................................................... 6-16
7 Watchdog Timer (WDT)................................................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Clock Settings................................................................................................................. 7-1
7.2.1 WDT Operating Clock....................................................................................... 7-1
7.2.2 Clock Supply in DEBUG Mode......................................................................... 7-2
7.3 Operations ...................................................................................................................... 7-2
7.3.1 WDT Control ..................................................................................................... 7-2
7.3.2 Operations in HALT and SLEEP Modes............................................................ 7-2
7.4 Control Registers ............................................................................................................ 7-3
WDT Clock Control Register ..................................................................................................... 7-3
WDT Control Register ............................................................................................................... 7-3
8 Real-Time Clock (RTCA) ..............................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Output Pin and External Connection .............................................................................. 8-1
8.2.1 Output Pin......................................................................................................... 8-1
8.3 Clock Settings................................................................................................................. 8-2
8.3.1 RTCA Operating Clock ..................................................................................... 8-2
8.3.2 Theoretical Regulation Function....................................................................... 8-2
8.4 Operations ...................................................................................................................... 8-3
8.4.1 RTCA Control ................................................................................................... 8-3
8.4.2 Real-Time Clock Counter Operations............................................................... 8-4
8.4.3 Stopwatch Control............................................................................................ 8-4
8.4.4 Stopwatch Count-up Pattern ........................................................................... 8-4
8.5 Interrupts......................................................................................................................... 8-5
8.6 Control Registers ............................................................................................................ 8-6
RTC Control Register ................................................................................................................ 8-6
RTC Second Alarm Register ..................................................................................................... 8-7
RTC Hour/Minute Alarm Register.............................................................................................. 8-8
RTC Stopwatch Control Register .............................................................................................. 8-8
RTC Second/1Hz Register ........................................................................................................ 8-9
RTC Hour/Minute Register ....................................................................................................... 8-10
RTC Month/Day Register ......................................................................................................... 8-11
RTC Year/Week Register .......................................................................................................... 8-11

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RTC Interrupt Flag Register...................................................................................................... 8-12
RTC Interrupt Enable Register ................................................................................................. 8-13
9 Supply Voltage Detector (SVD)....................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Input Pin and External Connection ................................................................................. 9-2
9.2.1 Input Pin............................................................................................................ 9-2
9.2.2 External Connection ......................................................................................... 9-2
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 SVD Operating Clock........................................................................................ 9-2
9.3.2 Clock Supply in SLEEP Mode .......................................................................... 9-2
9.3.3 Clock Supply in DEBUG Mode......................................................................... 9-3
9.4 Operations ...................................................................................................................... 9-3
9.4.1 SVD Control ...................................................................................................... 9-3
9.4.2 SVD Operations ................................................................................................ 9-4
9.5 SVD Interrupt and Reset ................................................................................................. 9-4
9.5.1 SVD Interrupt .................................................................................................... 9-4
9.5.2 SVD Reset......................................................................................................... 9-5
9.6 Control Registers ............................................................................................................ 9-5
SVD Clock Control Register ...................................................................................................... 9-5
SVD Control Register ................................................................................................................ 9-6
SVD Status and Interrupt Flag Register .................................................................................... 9-7
SVD Interrupt Enable Register .................................................................................................. 9-8
10 16-bit Timers (T16).....................................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pin....................................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 T16 Operating Clock...................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-2
10.3.4 Event Counter Clock...................................................................................... 10-2
10.4 Operations ................................................................................................................... 10-2
10.4.1 Initialization .................................................................................................... 10-2
10.4.2 Counter Underflow ........................................................................................ 10-3
10.4.3 Operations in Repeat Mode........................................................................... 10-3
10.4.4 Operations in One-shot Mode ....................................................................... 10-3
10.4.5 Counter Value Read....................................................................................... 10-4
10.5 Interrupt........................................................................................................................ 10-4
10.6 Control Registers ......................................................................................................... 10-4
T16 Ch.nClock Control Register ............................................................................................. 10-4
T16 Ch.nMode Register .......................................................................................................... 10-5
T16 Ch.nControl Register........................................................................................................ 10-5
T16 Ch.nReload Data Register................................................................................................ 10-6
T16 Ch.nCounter Data Register .............................................................................................. 10-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 10-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 10-7
11 UART (UART)..............................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input/Output Pins and External Connections .............................................................. 11-2
11.2.1 List of Input/Output Pins................................................................................ 11-2
11.2.2 External Connections .................................................................................... 11-2
11.2.3 Input Pin Pull-Up Function............................................................................. 11-2
11.2.4 Output Pin Open-Drain Output Function ...................................................... 11-2

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11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 UART Operating Clock .................................................................................. 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-2
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-3
11.3.4 Baud Rate Generator..................................................................................... 11-3
11.4 Data Format ................................................................................................................. 11-3
11.5 Operations ................................................................................................................... 11-4
11.5.1 Initialization .................................................................................................... 11-4
11.5.2 Data Transmission ......................................................................................... 11-4
11.5.3 Data Reception .............................................................................................. 11-5
11.5.4 IrDA Interface................................................................................................. 11-6
11.6 Receive Errors.............................................................................................................. 11-7
11.6.1 Framing Error ................................................................................................. 11-7
11.6.2 Parity Error..................................................................................................... 11-8
11.6.3 Overrun Error ................................................................................................. 11-8
11.7 Interrupts...................................................................................................................... 11-8
11.8 Control Registers ......................................................................................................... 11-8
UART Ch.nClock Control Register .......................................................................................... 11-8
UART Ch.nMode Register....................................................................................................... 11-9
UART Ch.nBaud–Rate Register ............................................................................................. 11-10
UART Ch.nControl Register ................................................................................................... 11-10
UART Ch.nTransmit Data Register ......................................................................................... 11-11
UART Ch.nReceive Data Register.......................................................................................... 11-11
UART Ch.nStatus and Interrupt Flag Register ....................................................................... 11-11
UART Ch.nInterrupt Enable Register...................................................................................... 11-12
12 Synchronous Serial Interface (SPIA)........................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Pin Functions in Master Mode and Slave Mode............................................ 12-3
12.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 12-3
12.3 Clock Settings.............................................................................................................. 12-3
12.3.1 SPIA Operating Clock.................................................................................... 12-3
12.3.2 Clock Supply in DEBUG Mode...................................................................... 12-4
12.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 12-4
12.4 Data Format ................................................................................................................. 12-5
12.5 Operations ................................................................................................................... 12-5
12.5.1 Initialization .................................................................................................... 12-5
12.5.2 Data Transmission in Master Mode ............................................................... 12-5
12.5.3 Data Reception in Master Mode.................................................................... 12-7
12.5.4 Terminating Data Transfer in Master Mode.................................................... 12-8
12.5.5 Data Transfer in Slave Mode.......................................................................... 12-8
12.5.6 Terminating Data Transfer in Slave Mode ..................................................... 12-10
12.6 Interrupts..................................................................................................................... 12-10
12.7 Control Registers ........................................................................................................ 12-11
SPIA Ch.nMode Register ....................................................................................................... 12-11
SPIA Ch.nControl Register..................................................................................................... 12-12
SPIA Ch.nTransmit Data Register .......................................................................................... 12-13
SPIA Ch.nReceive Data Register ........................................................................................... 12-13
SPIA Ch.nInterrupt Flag Register ........................................................................................... 12-13
SPIA Ch.nInterrupt Enable Register ....................................................................................... 12-14

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13 I2C (I2C).......................................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-3
13.3.1 I2C Operating Clock ...................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode...................................................................... 13-3
13.3.3 Baud Rate Generator..................................................................................... 13-3
13.4 Operations ................................................................................................................... 13-4
13.4.1 Initialization .................................................................................................... 13-4
13.4.2 Data Transmission in Master Mode ............................................................... 13-5
13.4.3 Data Reception in Master Mode.................................................................... 13-7
13.4.4 10-bit Addressing in Master Mode ................................................................ 13-9
13.4.5 Data Transmission in Slave Mode................................................................. 13-10
13.4.6 Data Reception in Slave Mode ..................................................................... 13-12
13.4.7 Slave Operations in 10-bit Address Mode.................................................... 13-14
13.4.8 Automatic Bus Clearing Operation ............................................................... 13-14
13.4.9 Error Detection.............................................................................................. 13-15
13.5 Interrupts..................................................................................................................... 13-16
13.6 Control Registers ........................................................................................................ 13-17
I2C Ch.nClock Control Register............................................................................................. 13-17
I2C Ch.nMode Register.......................................................................................................... 13-18
I2C Ch.nBaud-Rate Register.................................................................................................. 13-18
I2C Ch.nOwn Address Register ............................................................................................. 13-18
I2C Ch.nControl Register ....................................................................................................... 13-19
I2C Ch.nTransmit Data Register............................................................................................. 13-20
I2C Ch.nReceive Data Register.............................................................................................. 13-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 13-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 13-21
14 LCD Driver (LCD8A)...................................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Output Pins and External Connections........................................................................ 14-2
14.2.1 List of Output Pins ......................................................................................... 14-2
14.2.2 External Connections .................................................................................... 14-2
14.3 Clock Settings.............................................................................................................. 14-2
14.3.1 LCD8A Operating Clock ................................................................................ 14-2
14.3.2 Clock Supply in SLEEP Mode ....................................................................... 14-3
14.3.3 Clock Supply in DEBUG Mode...................................................................... 14-3
14.3.4 Frame Frequency........................................................................................... 14-3
14.4 LCD Power Supply....................................................................................................... 14-3
14.4.1 Internal Generation Mode .............................................................................. 14-4
14.4.2 External Voltage Application Mode 1............................................................. 14-4
14.4.3 External Voltage Application Mode 2............................................................. 14-4
14.4.4 LCD Voltage Regulator Settings .................................................................... 14-4
14.4.5 LCD Voltage Booster Setting......................................................................... 14-5
14.4.6 LCD Contrast Adjustment.............................................................................. 14-5
14.5 Operations ................................................................................................................... 14-5
14.5.1 Initialization .................................................................................................... 14-5
14.5.2 Display On/Off ............................................................................................... 14-6
14.5.3 Inverted Display ............................................................................................. 14-6
14.5.4 Drive Duty Switching ..................................................................................... 14-6
14.5.5 Drive Waveforms............................................................................................ 14-7

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14.5.6 Partial Common Output Drive........................................................................ 14-9
14.5.7 n-Segment-Line Inverse AC Drive ................................................................. 14-9
14.6 Display Data RAM ........................................................................................................ 14-9
14.6.1 Display Area Selection................................................................................... 14-9
14.6.2 Segment Pin Assignment ............................................................................. 14-10
14.6.3 Common Pin Assignment ............................................................................. 14-10
14.7 Interrupt....................................................................................................................... 14-11
14.8 Control Registers ........................................................................................................ 14-12
LCD8A Clock Control Register................................................................................................ 14-12
LCD8A Control Register.......................................................................................................... 14-12
LCD8A Timing Control Register .............................................................................................. 14-13
LCD8A Power Control Register............................................................................................... 14-13
LCD8A Display Control Register ............................................................................................. 14-14
LCD8A Interrupt Flag Register ................................................................................................ 14-15
LCD8A Interrupt Enable Register ............................................................................................ 14-16
15 R/F Converter (RFC) ..................................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-2
15.2.1 List of Input/Output Pins................................................................................ 15-2
15.2.2 External Connections .................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-3
15.3.1 RFC Operating Clock..................................................................................... 15-3
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-3
15.3.3 Clock Supply in DEBUG Mode...................................................................... 15-3
15.4 Operations ................................................................................................................... 15-3
15.4.1 Initialization .................................................................................................... 15-3
15.4.2 Operating Modes........................................................................................... 15-4
15.4.3 RFC Counters ................................................................................................ 15-4
15.4.4 Converting Operations and Control Procedure ............................................. 15-5
15.4.5 CR Oscillation Frequency Monitoring Function............................................. 15-7
15.5 Interrupts...................................................................................................................... 15-7
15.6 Control Registers ......................................................................................................... 15-8
RFC Ch.nClock Control Register ............................................................................................ 15-8
RFC Ch.nControl Register....................................................................................................... 15-8
RFC Ch.nOscillation Trigger Register...................................................................................... 15-9
RFC Ch.nMeasurement Counter Low and High Registers .................................................... 15-10
RFC Ch.nTime Base Counter Low and High Registers ......................................................... 15-10
RFC Ch.nInterrupt Flag Register............................................................................................ 15-11
RFC Ch.nInterrupt Enable Register........................................................................................ 15-11
16 MR Sensor Controller (AMRC) .................................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins and External Connections .............................................................. 16-2
16.2.1 List of Input/Output Pins................................................................................ 16-2
16.2.2 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-3
16.3.1 AMRC Operating Clock ................................................................................. 16-3
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-3
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Measurement Control and Operations .......................................................... 16-4
16.4.3 Pulse Output Function................................................................................... 16-6

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16.4.4 Hysteresis Control Function .......................................................................... 16-7
16.5 Interrupts...................................................................................................................... 16-7
16.6 Control Registers ......................................................................................................... 16-8
AMRC Clock Control Register.................................................................................................. 16-8
AMRC AFE Control Register .................................................................................................... 16-8
AMRC Pulse Control Register.................................................................................................. 16-9
AMRC Control Register............................................................................................................ 16-9
AMRC Normal Rotation Counter Register .............................................................................. 16-11
AMRC Reverse/Stop Counter Register................................................................................... 16-11
AMRC Event Counter Ch.xRegister ....................................................................................... 16-11
AMRC Unit Counter Compare Setting Register...................................................................... 16-12
AMRC Unit Counter Register .................................................................................................. 16-12
AMRC Status Register ............................................................................................................ 16-12
AMRC Interrupt Flag Register ................................................................................................. 16-13
AMRC Interrupt Enable Register ............................................................................................. 16-14
17 Electrical Characteristics .........................................................................................17-1
17.1 Absolute Maximum Ratings ......................................................................................... 17-1
17.2 Recommended Operating Conditions ......................................................................... 17-1
17.3 Current Consumption................................................................................................... 17-2
17.4 System Reset Controller (SRC) Characteristics........................................................... 17-3
17.5 Clock Generator (CLG) Characteristics........................................................................ 17-3
17.6 Flash Memory Characteristics ..................................................................................... 17-4
17.7 Input/Output Port (PPORT) Characteristics ................................................................. 17-5
17.8 Supply Voltage Detector (SVD) Characteristics ........................................................... 17-6
17.9 UART (UART) Characteristics ...................................................................................... 17-7
17.10 Synchronous Serial Interface (SPIA) Characteristics ................................................. 17-7
17.11 I2C (I2C) Characteristics............................................................................................. 17-8
17.12 LCD Driver (LCD8A) Characteristics .......................................................................... 17-9
17.13 R/F Converter (RFC) Characteristics......................................................................... 17-11
17.14 MR Sensor Controller (AMRC) Characteristics ......................................................... 17-12
18 Basic External Connection Diagram .......................................................................18-1
19 Package......................................................................................................................19-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC)................................................................. AP-A-1
0x4020 Power Generator (PWG).............................................................. AP-A-1
0x4040–0x404e Clock Generator (CLG) ................................................................ AP-A-1
0x4080–0x408e Interrupt Controller (ITC).............................................................. AP-A-2
0x40a0–0x40a2 Watchdog Timer (WDT) ............................................................... AP-A-3
0x40c0–0x40d2 Real-time Clock (RTCA)............................................................... AP-A-4
0x4100–0x4106 Supply Voltage Detector (SVD).................................................... AP-A-5
0x4160–0x416c 16-bit Timer (T16) Ch.0................................................................ AP-A-6
0x41b0 Flash Controller (FLASHC) .......................................................... AP-A-6
0x4200–0x42e2 I/O Ports (PPORT) ....................................................................... AP-A-6
0x4380–0x438e UART (UART)............................................................................... AP-A-9
0x43a0–0x43ac 16-bit Timer (T16) Ch.1............................................................... AP-A-10
0x43b0–0x43ba Synchronous Serial Interface (SPIA) Ch.0.................................. AP-A-11
0x43c0–0x43d2 I2C (I2C) ...................................................................................... AP-A-12
0x5100–0x510c 16-bit Timer (T16) Ch.2............................................................... AP-A-13
0x5120–0x512c 16-bit Timer (T16) Ch.3............................................................... AP-A-13
0x5260–0x526c 16-bit Timer (T16) Ch.4............................................................... AP-A-14
0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1 .................................. AP-A-14

CONTENTS
xSeiko Epson Corporation S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
0x5400–0x540c LCD Driver (LCD8A).................................................................... AP-A-15
0x5440–0x5450 R/F Converter (RFC) ................................................................... AP-A-16
0x5480–0x549e MR Sensor Controller (AMRC).................................................... AP-A-17
0xffff90 Debugger (DBG) ......................................................................... AP-A-18
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions ............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History

1 OVERVIEW
S1C17M01 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.2)
1 Overview
The S1C17M01 is an ultra low-power MCU equipped with an MR (magnetoresistive) sensor controller that al-
lows an MR sensor array optimized for flow measurement (recommended sensor: KG1205-61 manufactured by
KOHDEN Co., Ltd.) to be connected directly. This IC includes an LCD driver to display the flow count and the
readouts on the indicator, and the synchronous serial interface, UART, and I2C interface for wireless communica-
tion with a remote meter reading system. This IC allows measurement of various environmental conditions such
as a temperature and humidity measurement using the R/F converter, and a supply voltage measurement using the
supply voltage detector.
1.1 Features
Table 1.1.1 Features
Model S1C17M01
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Other On-chip debugger
Embedded Flash memory
Capacity 32K bytes (for both instructions and data)
Erase/program count 50 times (min.) *Programming by the debugging tool ICDmini
Other Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Embedded RAM
Capacity 4K bytes
Embedded display RAM
Capacity 32 bytes
Clock generator (CLG)
System clock source 3 sources (IOSC/OSC1/EXOSC)
System clock frequency (operating fre-
quency)
16.3 MHz (max.)
IOSC oscillator circuit (boot clock source) 7.37 MHz (typ.) embedded oscillator
5 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by
the CPU)
OSC1 oscillator circuit 32.768 kHz (typ.) crystal oscillator
Oscillation stop detection circuit included
EXOSC clock input 16.3 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports 19 bits (max.) (Pins are shared with the peripheral I/O.)
Number of input interrupt ports 8 bits
Timers
Watchdog timer (WDT) Generates watchdog timer reset.
Real-time clock (RTCA) 128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16) 5 channels
2 channels can generate the SPIA master clock.
Supply voltage detector (SVD)
Detection level 20 levels (1.8 to 3.7 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Serial interfaces
UART (UART) 1 channel
Baud-rate generator included, IrDA1.0 supported
Synchronous Serial Interface (SPIA) 2 channels
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
I2C (I2C) 1 channel
Baud-rate generator included

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
LCD driver (LCD8A)
LCD output 32 SEG ×1 to 4 COM (max.), 28 SEG ×5 to 8 COM (max.)
LCD contrast 16 levels (2.55 to 3.44 V)
Other 1/3 bias power supply included, external voltage can be applied.
R/F converter (RFC)
Conversion method CR oscillation type with 24-bit counters
Number of conversion channels 1 channel (Up to two sensors can be connected.)
Supported sensors DC-bias resistive sensors and AC-bias resistive sensors
MR sensor controller (AMRC)
MR sensor interface MR sensor is directly connectable.
Measurement functions Evaluates normal rotation, reverse rotation, stop, and phase dropout by inputting
analog rotation phase signals from an MR sensor.
External interface Pulse output function
External hysteresis resistor control function
Reset
#RESET pin Reset when the reset pin is set to low.
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/
disabled using a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable interrupt External interrupt: 1 system (8 levels)
Internal interrupt: 15 systems (8 levels)
Power supply voltage
VDD operating voltage 1.8 to 5.5 V
VDD operating voltage when AMRC is active 2.0 to 5.5 V
VDD operating voltage for Flash programming 1.8 to 5.5 V (VPP = 7.5 V external power supply is required.)
Operating temperature
Operating temperature range -40 to 85 °C
Current consumption
SLEEP mode 0.35 µA
IOSC = OFF, OSC1 = OFF, VDD = 3.6 V
HALT mode 0.8 µA
IOSC = OFF, OSC1 = 32 kHz, RTC = ON, VDD = 3.6 V
1.3 µA
IOSC = OFF, OSC1 = 32 kHz, RTC = ON, CPU = OSC1, LCD = ON (no panel load, VC2
reference)
RUN mode 12.5 µA
IOSC = OFF, OSC1 = 32 kHz, RTC = ON, CPU = OSC1, LCD = ON (no panel load, VC2
reference)
2.5 mA @ 1/1 divided clock
IOSC = ON, OSC1 = 32 kHz, RTC = ON, CPU = IOSC, LCD = OFF (no panel load)
500 µA @ 1/8 divided clock
IOSC = ON, OSC1 = 32 kHz, RTC = ON, CPU = IOSC, LCD = OFF (no panel load)
Shipping form
1 *1QFP13-64PIN (P-LQFP064-1010-0.50, 10 ×10 mm, t = 1.7 mm, 0.5 mm pitch)
2 Die form (Pad pitch: 100 µm)
*1 Shown in parentheses is a JEITA package name.

1 OVERVIEW
S1C17M01 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.2)
1.2 Block Diagram
CPU core & debugger
(S1C17)
Internal RAM
4K bytes
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Instruction bus
16-bit internal bus
IOSC
oscillator
OSC1
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power generator
(PWG)
System reset controller
(SRC)
VDD
VSS
VD1
VPP
RTC1S
SDA0
SCL0
EXSVD
EXCL0–1
USIN0
USOUT0
P00–07,
P14–17,
P20–21,
P56–57,
PD0–D2
FOUT
OSC1
OSC2
EXOSC
#RESET
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT)
Real-time clock
(RTCA)
I2C
(I2C)
R/F converter
(RFC)
Supply voltage
detector
(SVD)
16-bit timer
(T16)
5 Ch.
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
RFIN0
REF0
SENA0
SENB0
RFCLKO0
MR sensor
controller
(AMRC)
CMPIN0–1P
CMPIN0–1N
EVPLS
SENSEN
EXHYS0–1
Synchronous
serial interface
(SPIA)
2 Ch.
VC1–3
CP1–2
COM0–7
SEG0–31
LFRO
LCD driver
(LCD8A)
8 bit
Display RAM
32 bytes
UART
(UART)
Flash memory
32K bytes
Figure 1.2.1 S1C17M01 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
1.3 Pins
1.3.1 Pin Configuration Diagram (TQFP13-64PIN)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30
VDD
CP1 CP2
P14/#SPISS0
P15/CMPIN1P
P16/CMPIN1N P17/CMPIN0N
P20/USIN0/CMPIN0P
P21/USOUT0/SENSEN/SEG7
SEG8 SEG9
SEG10 SEG11 SEG12 SEG13
EXCL0/SEG14
VDD
CP1 CP2
VSS VD1 P57 P56 PD2 PD1 PD0 VPP P55 P54 P53 P52 P51 P50 P47 P46
VSS
VD1 P57 P56 DCLK/PD2 DSIO/PD1 DST2/PD0 VPP COM0 COM1 COM2 COM3
SEG31/COM4 SEG30/COM5 SEG29/COM6 SEG28/COM7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
P33
P32
P31
VC3
VC2
VC1
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
#SPISS1/SEG20
SPICLK1/SEG19
SDO1/SEG18
SDI1/SEG17
FOUT/SEG16
EXCL1/SEG15
VC3
VC2
VC1
Pin name
#RESET
VDD
OSC1
OSC2
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
Port function or signal assignment
#RESET
VDD
OSC1
OSC2
P00/EXOSC/RFCLKO0/SEG0
P01/LFRO/USIN0/SEG1
P02/RTC1S/USOUT0/SEG2
P03/SCL0/SENB0
P04/SDA0/SENA0
P05/SDI0/REF0
P06/SDO0/RFIN0
P07/SPICLK0/EVPLS/EXSVD
SDI0/SCL0/SEG3
SDO0/SDA0/SEG4
SPICLK0/EXHYS1/SEG5
#SPISS0/EXHYS0/SEG6
Figure 1.3.1.1 S1C17M01 Pin Configuration Diagram (TQFP13-64PIN)

1 OVERVIEW
S1C17M01 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.2)
1.3.2 Pad Configuration Diagram (Chip)
Die No. CJxxxxxxx
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Y
X
(0, 0)
P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30
VDD
CP1 CP2
P14/#SPISS0
P15/CMPIN1P
P16/CMPIN1N P17/CMPIN0N
P20/USIN0/CMPIN0P
P21/USOUT0/SENSEN/SEG7
SEG8 SEG9
SEG10 SEG11 SEG12 SEG13
EXCL0/SEG14
VDD
CP1 CP2
VSS VD1 P57 P56 PD2 PD1 PD0 VPP P55 P54 P53 P52 P51 P50 P47 P46
VSS
VD1 P57 P56 DCLK/PD2 DSIO/PD1 DST2/PD0 VPP COM0 COM1 COM2 COM3
SEG31/COM4 SEG30/COM5 SEG29/COM6 SEG28/COM7
P45
P44
P43
P42
P41
P40
P37
P36
P35
P34
P33
P32
P31
VC3
VC2
VC1
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
#SPISS1/SEG20
SPICLK1/SEG19
SDO1/SEG18
SDI1/SEG17
FOUT/SEG16
EXCL1/SEG15
VC3
VC2
VC1
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
2.826 mm
2.446 mm
Pad name
#RESET
VDD
OSC1
OSC2
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
Port function or signal assignment
#RESET
VDD
OSC1
OSC2
P00/EXOSC/RFCLKO0/SEG0
P01/LFRO/USIN0/SEG1
P02/RTC1S/USOUT0/SEG2
P03/SCL0/SENB0
P04/SDA0/SENA0
P05/SDI0/REF0
P06/SDO0/RFIN0
P07/SPICLK0/EVPLS/EXSVD
SDI0/SCL0/SEG3
SDO0/SDA0/SEG4
SPICLK0/EXHYS1/SEG5
#SPISS0/EXHYS0/SEG6
Figure 1.3.2.1 S1C17M01 Pad Configuration Diagram (Chip)
Pad opening No. 1–16, 33–48: X = 76 µm, Y = 90 µm
No. 17–32, 49–64: X = 90 µm, Y = 76 µm
Chip thickness 400 µm
Table 1.3.2.1 Pad Coordinates
No. X µm Y µm No. X µm Y µm No. X µm Y µm No. X µm Y µm
1 -755.0 -1,322.3 17 1,132.3 -945.0 33 755.0 1,322.3 49 -1,132.3 945.0
2 -655.0 -1,322.3 18 1,132.3 -845.0 34 655.0 1,322.3 50 -1,132.3 845.0
3 -555.0 -1,322.3 19 1,132.3 -745.0 35 555.0 1,322.3 51 -1,132.3 745.0
4 -455.0 -1,322.3 20 1,132.3 -545.0 36 455.0 1,322.3 52 -1,132.3 645.0
5 -355.0 -1,322.3 21 1,132.3 -445.0 37 355.0 1,322.3 53 -1,132.3 545.0
6 -245.0 -1,322.3 22 1,132.3 -345.0 38 255.0 1,322.3 54 -1,132.3 445.0
7 -145.0 -1,322.3 23 1,132.3 -245.0 39 155.0 1,322.3 55 -1,132.3 345.0
8 -45.0 -1,322.3 24 1,132.3 -145.0 40 55.0 1,322.3 56 -1,132.3 245.0
9 55.0 -1,322.3 25 1,132.3 -45.0 41 -55.0 1,322.3 57 -1,132.3 145.0
10 155.0 -1,322.3 26 1,132.3 55.0 42 -155.0 1,322.3 58 -1,132.3 45.0
11 255.0 -1,322.3 27 1,132.3 445.0 43 -255.0 1,322.3 59 -1,132.3 -55.0
12 355.0 -1,322.3 28 1,132.3 545.0 44 -355.0 1,322.3 60 -1,132.3 -545.0
13 455.0 -1,322.3 29 1,132.3 645.0 45 -455.0 1,322.3 61 -1,132.3 -645.0
14 555.0 -1,322.3 30 1,132.3 745.0 46 -555.0 1,322.3 62 -1,132.3 -745.0
15 655.0 -1,322.3 31 1,132.3 845.0 47 -655.0 1,322.3 63 -1,132.3 -845.0
16 755.0 -1,322.3 32 1,132.3 945.0 48 -755.0 1,322.3 64 -1,132.3 -945.0

1 OVERVIEW
1-6 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
1.3.3 Pin Descriptions
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
Table 1.3.3.1 Pin description
Pin/pad
name
Assigned
signal I/O Initial state Tolerant fail-safe structure Function
VDD VDD P – – Power supply (+)
VSS VSS P – – GND
VPP VPP P – – Power supply for Flash programming
VD1 VD1 A – – Embedded regulator output
VC1 VC1 P – – LCD panel drive power
VC2 VC2 P – – LCD panel drive power
VC3 VC3 P – – LCD panel drive power
CP1 CP1 A – – LCD voltage boost capacitor connect pin
CP2 CP2 A – – LCD voltage boost capacitor connect pin
#RESET #RESET I I (Pull-up) –Reset input
P00 P00 I/O Hi-Z ✓I/O port
EXOSC I Clock generator external clock input
RFCLKO0 O R/F converter Ch.0 clock monitor output
SEG0 O LCD segment output
P01 P01 I/O Hi-Z ✓I/O port
LFRO O LCD frame signal monitor output
USIN0 I UART Ch.0 data input
SEG1 O LCD segment output
P02 P02 I/O Hi-Z ✓I/O port
RTC1S O Real-time clock 1-second cycle pulse output
USOUT0 O UART Ch.0 data output
SEG2 O LCD segment output
P03 P03 I/O Hi-Z –I/O port
SCL0 I/O I2C Ch.0 clock input/output
SENB0 A R/F converter Ch.0 sensor B oscillator pin
P04 P04 I/O Hi-Z –I/O port
SDA0 I/O I2C Ch.0 data input/output
SENA0 A R/F converter Ch.0 sensor A oscillator pin
P05 P05 I/O Hi-Z –I/O port
SDI0 I Synchronous serial interface Ch.0 data input
REF0 A R/F converter Ch.0 reference oscillator pin
P06 P06 I/O Hi-Z –I/O port
SDO0 O Synchronous serial interface Ch.0 data output
RFIN0 A R/F converter Ch.0 oscillation input
P07 P07 I/O Hi-Z –I/O port
SPICLK0 I/O Synchronous serial interface Ch.0 clock input/output
EVPLS O MR sensor controller pulse output
EXSVD A External power supply voltage detection input

1 OVERVIEW
S1C17M01 TECHNICAL MANUAL Seiko Epson Corporation 1-7
(Rev. 1.2)
Pin/pad
name
Assigned
signal I/O Initial state Tolerant fail-safe structure Function
P10 – Hi-Z Hi-Z ✓–
SDI0 I Synchronous serial interface Ch.0 data input
SCL0 I/O I2C Ch.0 clock input/output
SEG3 A LCD segment output
P11 – Hi-Z Hi-Z ✓–
SDO0 O Synchronous serial interface Ch.0 data output
SDA0 I/O I2C Ch.0 data input/output
SEG4 A LCD segment output
P12 – Hi-Z Hi-Z ✓–
SPICLK0 I/O Synchronous serial interface Ch.0 clock input/output
EXHYS1 O MR sensor controller external hysteresis control output
Ch.1
SEG5 A LCD segment output
P13 – Hi-Z Hi-Z ✓–
#SPISS0 I Synchronous serial interface Ch.0 slave-select input
EXHYS0 O MR sensor controller external hysteresis control output Ch.0
SEG6 A LCD segment output
P14 P14 I/O Hi-Z –I/O port
#SPISS0 I Synchronous serial interface Ch.0 slave-select input
P15 P15 I/O Hi-Z –I/O port
CMPIN1P A MR sensor controller comparator Ch.1 input +
P16 P16 I/O Hi-Z –I/O port
CMPIN1N A MR sensor controller comparator Ch.1 input –
P17 P17 I/O Hi-Z –I/O port
CMPIN0N A MR sensor controller comparator Ch.0 input –
P20 P20 I/O Hi-Z –I/O port
USIN0 I UART Ch.0 data input
CMPIN0P A MR sensor controller comparator Ch.0 input +
P21 P21 I/O Hi-Z ✓I/O port
USOUT0 O UART Ch.0 data output
SENSEN O MR sensor controller magnetic sensor enable output
SEG7 A LCD segment output
P22 – Hi-Z Hi-Z ✓–
SEG8 A LCD segment output
P23 – Hi-Z Hi-Z ✓–
SEG9 A LCD segment output
P24 – Hi-Z Hi-Z ✓–
SEG10 A LCD segment output
P25 – Hi-Z Hi-Z ✓–
SEG11 A LCD segment output
P26 – Hi-Z Hi-Z ✓–
SEG12 A LCD segment output
P27 – Hi-Z Hi-Z ✓–
SEG13 A LCD segment output
P30 – Hi-Z Hi-Z ✓–
EXCL0 I 16-bit timer Ch.2 external clock input
SEG14 A LCD segment output
P31 – Hi-Z Hi-Z ✓–
EXCL1 I 16-bit timer Ch.3 external clock input
SEG15 A LCD segment output
P32 – Hi-Z Hi-Z ✓–
FOUT O Clock external output
SEG16 A LCD segment output
P33 – Hi-Z Hi-Z ✓–
SDI1 I Synchronous serial interface Ch.1 data input
SEG17 A LCD segment output

1 OVERVIEW
1-8 Seiko Epson Corporation S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Pin/pad
name
Assigned
signal I/O Initial state Tolerant fail-safe structure Function
P34 – Hi-Z Hi-Z ✓–
SDO1 O Synchronous serial interface Ch.1 data output
SEG18 A LCD segment output
P35 – Hi-Z Hi-Z ✓–
SPICLK1 I/O Synchronous serial interface Ch.1 clock input/output
SEG19 A LCD segment output
P36 – Hi-Z Hi-Z ✓–
#SPISS1 I Synchronous serial interface Ch.1 slave-select input
SEG20 A LCD segment output
P37 – Hi-Z Hi-Z ✓–
SEG21 A LCD segment output
P40 – Hi-Z Hi-Z ✓–
SEG22 A LCD segment output
P41 – Hi-Z Hi-Z ✓–
SEG23 A LCD segment output
P42 – Hi-Z Hi-Z ✓–
SEG24 A LCD segment output
P43 – Hi-Z Hi-Z ✓–
SEG25 A LCD segment output
P44 – Hi-Z Hi-Z ✓–
SEG26 A LCD segment output
P45 – Hi-Z Hi-Z ✓–
SEG27 A LCD segment output
P46 – Hi-Z Hi-Z ✓–
COM7 A LCD common output
SEG28 A LCD segment output
P47 – Hi-Z Hi-Z ✓–
COM6 A LCD common output
SEG29 A LCD segment output
P50 – Hi-Z Hi-Z ✓–
COM5 A LCD common output
SEG30 A LCD segment output
P51 – Hi-Z Hi-Z ✓–
COM4 A LCD common output
SEG31 A LCD segment output
P52 – Hi-Z Hi-Z ✓–
COM3 A LCD common output
P53 – Hi-Z Hi-Z ✓–
COM2 A LCD common output
P54 – Hi-Z Hi-Z ✓–
COM1 A LCD common output
P55 – Hi-Z Hi-Z ✓–
COM0 A LCD common output
P56 P56 I/O Hi-Z ✓I/O port
P57 P57 I/O Hi-Z ✓I/O port
PD0 DST2 O O (L) ✓On-chip debugger status output
PD0 I/O I/O port
PD1 DSIO I/O I (pull-up) ✓On-chip debugger data input/output
PD1 I/O I/O port
PD2 DCLK O O (H) ✓On-chip debugger clock output
PD2 O Output port
OSC1 OSC1 A – –OSC1 oscillator circuit input
OSC2 OSC2 A – –OSC1 oscillator circuit output
Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name.