Freescale Semiconductor DSP56374 User manual

Document Number: DSP56374UG
Rev. 1.2
07/2007
DSP56374
24-Bit Digital Signal Processor
User Guide

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Table of Contents
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Preface i
Chapter 1
DSP56374 Overview
1.1 Introduction ...............................................................................................................................................................1-1
1.2 DSP56300 Core Description .....................................................................................................................................1-2
1.3 DSP56374 Audio Processor Architecture .................................................................................................................1-3
1.4 DSP56300 Core Functional Blocks ...........................................................................................................................1-3
1.4.1 Data ALU ............................................................................................................................................................1-3
1.4.1.1 Data ALU Registers ......................................................................................................................................1-3
1.4.1.2 Multiplier-Accumulator (MAC) ...................................................................................................................1-3
1.4.2 Address Generation Unit (AGU) ........................................................................................................................1-4
1.4.3 Program Control Unit (PCU) ..............................................................................................................................1-4
1.4.4 Internal Buses ......................................................................................................................................................1-4
1.4.5 Direct Memory Access (DMA) ...........................................................................................................................1-5
1.4.6 PLL-based Clock Oscillator ................................................................................................................................1-5
1.4.7 On-Chip Memory ................................................................................................................................................1-5
1.4.8 Off-Chip Memory Expansion .............................................................................................................................1-5
1.4.9 Power Requirements ...........................................................................................................................................1-5
1.5 Peripheral Overview ..................................................................................................................................................1-6
1.5.1 General Purpose Input/Output (GPIO) ...............................................................................................................1-6
1.5.2 Triple Timer (TEC) .............................................................................................................................................1-6
1.5.3 Enhanced Serial Audio Interface (ESAI) ............................................................................................................1-7
1.5.4 Enhanced Serial Audio Interface 1 (ESAI_1) .....................................................................................................1-7
1.5.5 Serial Host Interface (SHI) .................................................................................................................................1-7
1.5.6 Watchdog timer (WDT) ......................................................................................................................................1-7
Chapter 2
Signal/Connection Descriptions
2.1 Signal Groupings .......................................................................................................................................................2-1
2.2 Power .........................................................................................................................................................................2-1
2.3 Ground .......................................................................................................................................................................2-3
2.4 SCAN ........................................................................................................................................................................2-4
2.5 Clock and PLL ...........................................................................................................................................................2-4
2.6 Interrupt and Mode Control .......................................................................................................................................2-4
2.7 Serial Host Interface ..................................................................................................................................................2-6
2.8 Enhanced Serial Audio Interface ...............................................................................................................................2-8
2.9 Enhanced Serial Audio Interface_1 .........................................................................................................................2-12
2.10 Dedicated GPIO - Port G .........................................................................................................................................2-16
2.11 Timer .......................................................................................................................................................................2-18
2.12 JTAG/OnCE Interface .............................................................................................................................................2-19
Chapter 3
Memory Configuration
3.1 Data and Program Memory Maps .............................................................................................................................3-1
3.1.1 Reserved Memory Spaces ...................................................................................................................................3-5
3.1.2 Bootstrap CODE .................................................................................................................................................3-5
3.1.3 Dynamic Memory Configuration Switching ......................................................................................................3-5

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3.1.4 External Memory Support ...................................................................................................................................3-5
3.1.5 DMA and Memory ..............................................................................................................................................3-5
3.1.6 Memory BLOCKS ..............................................................................................................................................3-6
3.2 Memory Patch Module ..............................................................................................................................................3-6
3.3 Internal I/O Memory Map .........................................................................................................................................3-7
Chapter 4
Core Configuration
4.1 Introduction ...............................................................................................................................................................4-1
4.2 Operating Mode Register (OMR) ..............................................................................................................................4-1
4.2.1 RESERVED - Bits 4, 5, 10 - 15 and 23 ..............................................................................................................4-1
4.3 Operating Modes .......................................................................................................................................................4-1
4.4 Interrupt Priority Registers ........................................................................................................................................4-3
4.5 DMA Request Sources ..............................................................................................................................................4-9
4.6 PLL Initialization ....................................................................................................................................................4-10
4.6.1 PLL Pre-Divider Factor (PD0-PD4) .................................................................................................................4-10
4.6.2 PLL Multiplication Factor (MF0-MF7) ............................................................................................................4-10
4.6.3 PLL Feedback Multiplier (OD1) ......................................................................................................................4-10
4.6.4 PLL Output Divide Factor (OD0-OD1) ............................................................................................................4-10
4.6.5 PLL Divider Factor (DF0-DF2) ........................................................................................................................4-10
4.6.6 PLL LOCK MUX (PLKM) ..............................................................................................................................4-10
4.7 Device Identification (ID) Register .........................................................................................................................4-10
4.8 JTAG Identification (ID) Register ..........................................................................................................................4-11
Chapter 5
PLL and Clock generator
5.1 Introduction ...............................................................................................................................................................5-1
5.2 PLL and Clock Signals ..............................................................................................................................................5-1
5.3 PLL Block .................................................................................................................................................................5-1
5.3.1 Frequency Predivider ..........................................................................................................................................5-2
5.3.2 Phase Detector and Charge Pump Loop Filter ....................................................................................................5-2
5.3.3 Voltage Controlled Oscillator (VCO) .................................................................................................................5-2
5.3.4 PLL DividerS ......................................................................................................................................................5-2
5.3.5 PLL Multiplication Factor (MF) .........................................................................................................................5-3
5.4 PLL Operation ...........................................................................................................................................................5-3
5.4.1 EXTAL Clock Input Division .............................................................................................................................5-3
5.4.2 PLL Frequency Multiplication ............................................................................................................................5-3
5.4.3 PLL Output Frequency (PLL Out) ......................................................................................................................5-4
5.5 Clock Generator ........................................................................................................................................................5-6
5.5.1 Low-Power Divider (LPD) .................................................................................................................................5-6
5.6 Operating Frequency (Fosc) ......................................................................................................................................5-6
5.7 PLL Programming Model .........................................................................................................................................5-7
5.8 PLL Initialization Procedure ...................................................................................................................................5-10
5.9 PLL Programming Examples ..................................................................................................................................5-11
Chapter 6
General Purpose Input/Output
6.1 Introduction ..............................................................................................................................................................6-1
6.2 Programming Model ..................................................................................................................................................6-1

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6.2.1 Port C and E Signals and Registers .....................................................................................................................6-1
6.2.2 Port G Signals and Registers ...............................................................................................................................6-1
6.2.2.1 Port G Control Register (PCRG) ..................................................................................................................6-1
6.2.2.2 Port G Direction Register (PRRG) ...............................................................................................................6-1
6.2.2.3 Port G Data register (PDRG) ........................................................................................................................6-2
6.2.2.4 ESAI/EXTAL clocking control ....................................................................................................................6-2
6.2.3 Port H Signals and Registers ...............................................................................................................................6-3
6.2.3.1 Port H Control Register (PCRH) ..................................................................................................................6-3
6.2.3.2 Port H Direction Register (PRRH) ...............................................................................................................6-3
6.2.3.3 Port H Data register (PDRH) ........................................................................................................................6-4
6.2.4 Timer/Event Counter Signals ..............................................................................................................................6-4
Chapter 7
Serial Host Interface
7.1 Introduction ...............................................................................................................................................................7-1
7.2 Serial Host Interface Internal Architecture ...............................................................................................................7-1
7.3 SHI Clock Generator .................................................................................................................................................7-2
7.4 Serial Host Interface Programming Model ...............................................................................................................7-2
7.4.1 SHI Input/Output Shift Register (IOSR)—Host Side .........................................................................................7-4
7.4.2 SHI Host Transmit Data Register (HTX)—DSP Side ........................................................................................7-4
7.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side ..............................................................................................7-5
7.4.4 SHI Slave Address Register (HSAR)—DSP Side ..............................................................................................7-5
7.4.4.1 HSAR Reserved Bits—Bits 19, 17– 0 ..........................................................................................................7-5
7.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)—Bits 23–20,18 .......................................................................7-5
7.4.5 SHI Clock Control Register (HCKR)—DSP Side ..............................................................................................7-5
7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0 ............................................................................7-5
7.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 .................................................................................................7-6
7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3 ............................................................................7-7
7.4.5.4 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 ............................................................................................7-7
7.4.5.5 HCKR Reserved Bits—Bits 23–14, 11 ........................................................................................................7-7
7.4.6 SHI Control/Status Register (HCSR)—DSP Side ..............................................................................................7-7
7.4.6.1 HCSR Host Enable (HEN)—Bit 0 ...............................................................................................................7-7
7.4.6.1.1 SHI Individual Reset ..............................................................................................................................7-8
7.4.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1 ......................................................................................................7-8
7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2 ............................................................................7-8
7.4.6.4 HCSR I2C Clock Freeze (HCKFR)—Bit 4 ..................................................................................................7-8
7.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 .............................................................................................7-8
7.4.6.6 HCSR Master Mode (HMST)—Bit 6 ...........................................................................................................7-8
7.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7 .................................................................................7-9
7.4.6.8 HCSR Idle (HIDLE)—Bit 9 .........................................................................................................................7-9
7.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 .....................................................................................7-9
7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 ......................................................................................7-9
7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12 .......................................................................7-10
7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14 ............................................................................7-10
7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15 .................................................................................7-10
7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16 .................................................................................................7-10
7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17 ......................................................................................7-10
7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19 ..................................................................................................7-10
7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20 ...........................................................................................7-11

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7.4.6.18 Host Bus Error (HBER)—Bit 21 ................................................................................................................7-11
7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22 .........................................................................................................7-11
7.5 Characteristics Of The SPI Bus ...............................................................................................................................7-11
7.6 Characteristics Of The I2C Bus ...............................................................................................................................7-11
7.6.1 Overview ...........................................................................................................................................................7-11
7.6.2 I2C Data Transfer Formats ................................................................................................................................7-13
7.7 SHI Programming Considerations ...........................................................................................................................7-13
7.7.1 SPI Slave Mode .................................................................................................................................................7-13
7.7.2 SPI Master Mode ..............................................................................................................................................7-14
7.7.3 I2C Slave Mode .................................................................................................................................................7-14
7.7.3.1 Receive Data in I2C Slave Mode ................................................................................................................7-15
7.7.3.2 Transmit Data In I2C Slave Mode ..............................................................................................................7-15
7.7.4 I2C Master Mode ...............................................................................................................................................7-15
7.7.4.1 Receive Data in I2C Master Mode ..............................................................................................................7-16
7.7.4.2 Transmit Data In I2C Master Mode ............................................................................................................7-16
7.7.5 SHI Operation During DSP Stop ......................................................................................................................7-17
7.7.6 GPIO- HREQ Signal and Registers ..................................................................................................................7-17
Chapter 8
Enhanced Serial Audio Interface (ESAI)
8.1 Introduction ...............................................................................................................................................................8-1
8.2 ESAI Data and Control Pins ......................................................................................................................................8-2
8.2.1 Serial Transmit 0 Data Pin (SDO0) ....................................................................................................................8-3
8.2.2 Serial Transmit 1 Data Pin (SDO1) ....................................................................................................................8-3
8.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) ..........................................................................................8-3
8.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) ..........................................................................................8-3
8.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) ..........................................................................................8-3
8.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) ..........................................................................................8-3
8.2.7 Receiver Serial Clock (SCKR) ...........................................................................................................................8-4
8.2.8 Transmitter Serial Clock (SCKT) .......................................................................................................................8-4
8.2.9 Frame Sync for Receiver (FSR) ..........................................................................................................................8-5
8.2.10 Frame Sync for Transmitter (FST) .....................................................................................................................8-6
8.2.11 High Frequency Clock for Transmitter (HCKT) ................................................................................................8-6
8.2.12 High Frequency Clock for Receiver (HCKR) .....................................................................................................8-6
8.3 ESAI Programming Model ........................................................................................................................................8-6
8.3.1 ESAI Transmitter Clock Control Register (TCCR) ............................................................................................8-6
8.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 7–0 .........................................................8-7
8.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8 .........................................................................................8-8
8.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 13–9 ............................................................8-8
8.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 17–14 ........................................................8-8
8.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18 .........................................................................................8-9
8.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 ................................................................................8-9
8.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20 ...........................................................8-9
8.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21 ..........................................................................8-9
8.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22 ..................................................................8-9
8.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23 ........................................................8-9
8.3.2 ESAI Transmit Control Register (TCR) .............................................................................................................8-9
8.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0 ..............................................................................................8-10
8.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1 ..............................................................................................8-10

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8.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2 ..............................................................................................8-10
8.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3 ..............................................................................................8-11
8.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4 ..............................................................................................8-11
8.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5 ..............................................................................................8-11
8.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6 .........................................................................................8-11
8.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7 ............................................................................8-11
8.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 9-8 ......................................................8-12
8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 14-10 .....................................................8-13
8.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15 ..................................................................................8-14
8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16 ...................................................................8-15
8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17 ..............................................................................8-16
8.3.2.14 TCR Reserved Bit - Bits 18 ........................................................................................................................8-16
8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19 ...............................................................................8-16
8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 .......................................................................8-16
8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21 ............................................................8-16
8.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22 ...........................................................................................8-16
8.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 .........................................................................8-16
8.3.3 ESAI Receive Clock Control Register (RCCR) ...............................................................................................8-16
8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0 .......................................................8-17
8.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8 .......................................................................................8-17
8.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 13–9 .........................................................8-17
8.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 17-14 ......................................................8-17
8.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18 .......................................................................................8-18
8.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19 ..............................................................................8-18
8.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20 .........................................................8-18
8.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21 ........................................................................8-18
8.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22 ................................................................8-19
8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23 ......................................................8-19
8.3.4 ESAI Receive Control Register (RCR) .............................................................................................................8-19
8.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0 ..............................................................................................8-20
8.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1 ..............................................................................................8-20
8.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2 .............................................................................................. 8-20
8.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3 ..............................................................................................8-20
8.3.4.5 RCR Reserved Bits - Bits 5-4, 18-17 .........................................................................................................8-20
8.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6 ........................................................................................8-20
8.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7 ...........................................................................8-21
8.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 9-8 .....................................................8-21
8.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 14-10 .......................................................8-21
8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15 ..................................................................................8-22
8.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16 ...................................................................8-22
8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19 ...............................................................................8-22
8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20 ........................................................................8-23
8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21 .............................................................8-23
8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22 ............................................................................................8-23
8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 ..........................................................................8-23
8.3.5 ESAI Common Control Register (SAICR) .......................................................................................................8-23
8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0 .................................................................................................8-23
8.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1 .................................................................................................8-24
8.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2 .................................................................................................8-24
8.3.5.4 SAICR Reserved Bits - Bits 5-3, 23-9 ........................................................................................................8-24

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8.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6 .................................................................................8-24
8.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7 ..........................................................................8-24
8.3.5.7 SAICR Alignment Control (ALC) - Bit 8 ..................................................................................................8-24
8.3.6 ESAI Status Register (SAISR) ..........................................................................................................................8-25
8.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0 ......................................................................................................8-26
8.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1 ......................................................................................................8-26
8.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2 ......................................................................................................8-26
8.3.6.4 SAISR Reserved Bits - Bits 5-3, 12-11, 23-18 ...........................................................................................8-26
8.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6 .........................................................................................8-26
8.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7 ...................................................................................8-26
8.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8 ......................................................................................8-27
8.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9 ..........................................................................8-27
8.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10 .........................................................................8-27
8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13 .....................................................................................8-27
8.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14 ...............................................................................8-27
8.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15 ..............................................................................8-27
8.3.6.14 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16 ..................................................................8-27
8.3.6.13 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17................................................................... 8-28
8.3.7 ESAI Receive Shift Registers ...........................................................................................................................8-29
8.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0) ....................................................................................8-30
8.3.9 ESAI Transmit Shift Registers ..........................................................................................................................8-30
8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0) ..................................................................8-30
8.3.11 ESAI Time Slot Register (TSR) .......................................................................................................................8-30
8.3.12 Transmit Slot Mask Registers (TSMA, TSMB) ...............................................................................................8-30
8.3.13 Receive Slot Mask Registers (RSMA, RSMB) ................................................................................................8-31
8.4 Operating Modes .....................................................................................................................................................8-32
8.4.1 ESAI After Reset ..............................................................................................................................................8-32
8.4.2 ESAI Initialization ............................................................................................................................................8-32
8.4.3 ESAI Interrupt Requests ...................................................................................................................................8-33
8.4.4 Operating Modes – Normal, Network and On-Demand ...................................................................................8-33
8.4.4.1 Normal/Network/On-Demand Mode Selection ..........................................................................................8-33
8.4.4.2 Synchronous/Asynchronous Operating Modes ..........................................................................................8-34
8.4.4.3 Frame Sync Selection 3...............................................................................................................................8-34
8.4.4.4 Shift Direction Selection ............................................................................................................................8-34
8.4.5 Serial I/O Flags .................................................................................................................................................8-34
8.5 GPIO - Pins and Registers .......................................................................................................................................8-35
8.5.1 Port C (ESAI) GPIO - Pins and Registers ........................................................................................................8-35
8.5.1.1 Port C Control Register (PCRC) ................................................................................................................8-35
8.5.1.2 Port C Direction Register (PRRC) ..............................................................................................................8-35
8.5.1.3 Port C Data register (PDRC) ...................................................................................................................... 8-36
8.5.2 Port E (ESAI_1) GPIO - Pins and Registers .....................................................................................................8-36
8.5.2.1 Port E Control Register (PCRE) .................................................................................................................8-37
8.5.2.2 Port E Direction Register (PRRE) ..............................................................................................................8-37
8.5.2.3 Port E Data register (PDRE) .......................................................................................................................8-37
8.6 ESAI Initialization Examples ..................................................................................................................................8-38
8.6.1 Initializing the ESAI Using Individual Reset ...................................................................................................8-38
8.6.2 Initializing Just the ESAI Transmitter Section .................................................................................................8-38
8.6.3 Initializing Just the ESAI Receiver Section ......................................................................................................8-38

Table of Contents
Paragraph Page
Number Number
DSP56374 Users Guide, Rev. 1.2
Freescale Semiconductor TOC-7
Chapter 9
Triple Timer Module
9.1 Overview ...................................................................................................................................................................9-1
9.1.1 Triple Timer Module Block Diagram .................................................................................................................9-1
9.1.2 Individual Timer Block Diagram ........................................................................................................................9-1
9.2 Operation ...................................................................................................................................................................9-2
9.2.1 Timer After Reset ...............................................................................................................................................9-2
9.2.2 Timer Initialization .............................................................................................................................................9-2
9.2.3 Timer Exceptions ................................................................................................................................................9-3
9.3 Operating Modes .......................................................................................................................................................9-3
9.3.1 Triple Timer Modes ............................................................................................................................................9-3
9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................................................9-4
9.3.1.2 Timer Pulse (Mode 1) ...................................................................................................................................9-5
9.3.1.3 Timer Toggle (Mode 2) ................................................................................................................................9-7
9.3.1.4 Timer Event Counter (Mode 3) ....................................................................................................................9-9
9.3.2 Signal Measurement Modes ..............................................................................................................................9-10
9.3.2.1 Measurement Input Width (Mode 4) ..........................................................................................................9-10
9.3.2.2 Measurement Input Period (Mode 5) ..........................................................................................................9-12
9.3.2.3 Measurement Capture (Mode 6) .................................................................................................................9-13
9.3.3 Pulse Width Modulation (PWM, Mode 7) ........................................................................................................9-14
9.3.4 Watchdog Modes ..............................................................................................................................................9-16
9.3.4.1 Watchdog Pulse (Mode 9) ..........................................................................................................................9-16
9.3.4.2 Watchdog Toggle (Mode 10) .....................................................................................................................9-17
9.3.4.3 Reserved Modes .........................................................................................................................................9-18
9.3.5 Special Cases ....................................................................................................................................................9-18
9.3.6 DMA Trigger ....................................................................................................................................................9-18
9.4 Triple Timer Module Programming Model .............................................................................................................9-18
9.4.1 Prescaler Counter ..............................................................................................................................................9-18
9.4.2 Timer Prescaler Load Register (TPLR) ............................................................................................................9-19
9.4.3 Timer Prescaler Count Register (TPCR) ..........................................................................................................9-20
9.4.4 Timer Control/Status Register (TCSR) .............................................................................................................9-21
9.4.5 Timer Load Register (TLR) ..............................................................................................................................9-25
9.4.6 Timer Compare Register (TCPR) .....................................................................................................................9-25
9.4.7 Timer Count Register (TCR) ............................................................................................................................9-25
Chapter 10
Watchdog Timer Module
10.1 Introduction ............................................................................................................................................................10-1
10.2 WDT Pin ..................................................................................................................................................................10-1
10.3 WDT Operation ......................................................................................................................................................10-1
10.4 Description of Registers ..........................................................................................................................................10-2
10.4.1 Watchdog Control Register (WCR) .................................................................................................................10-2
10.4.2 Watchdog Counter & WCNTR Register ..........................................................................................................10-2
10.4.3 Watchdog Modulus Register (WMR) ..............................................................................................................10-3
10.4.4 Watchdog Service Register (WSR) ..................................................................................................................10-3
10.5 Operation in Different Modes ................................................................................................................................10-3
10.5.1 WAIT Mode .....................................................................................................................................................10-3
10.5.2 DEBUG Mode .................................................................................................................................................10-3
10.5.3 STOP MODE ....................................................................................................................................................10-3

Table Of Contents
Paragraph Page
Number Number
DSP56374 Users Guide, Rev. 1.2
TOC-8 Freescale Semiconductor
Appendix A
Bootstrap Source Code
A.1 DSP56374 Bootstrap Program .................................................................................................................................A-1
A.2 Using The Serial EEPROM Boot Mode ...................................................................................................................A-5
Appendix B
Equates
Appendix C
Programmer’s Reference
C.1 Introduction ..............................................................................................................................................................C-1
C.1.1 Peripheral Addresses ..........................................................................................................................................C-1
C.1.2 Interrupt Addresses ............................................................................................................................................C-1
C.1.3 Interrupt Priorities ..............................................................................................................................................C-1
C.1.4 Programming Sheets ..........................................................................................................................................C-1
C.1.5 Internal I/O Memory Map ..................................................................................................................................C-1
C.1.6 Interrupt Vector Addresses ................................................................................................................................C-7
C.2 Interrupt Source Priorities (within an IPL) .............................................................................................................C-10
C.3 Programming Sheets ...............................................................................................................................................C-11
Appendix D
BSDL
D.1 52-pin BSDL ............................................................................................................................................................D-1
D.2 80-pin BSDL ............................................................................................................................................................D-6