Fujitsu FR Series Installation and operating instructions

Fujitsu Microelectronics Europe
Application Note
FMEMCU-AN-910011-18
FR FAMILY
32-BIT MICROCONTROLLER
MB91360
EMULATION OF THE MB91360
SERIES
APPLICATION NOTE

Revision History
AN-910011-18 - 2 - © Fujitsu Microelectronics Europe GmbH
Revision History
Date Version Issue
04th Jan. 02 AG V1.0 initial release (preliminary)
08.03.02 AG V1.1 flow chart integrated (preliminary)
21.05.02 AG V1.2 flash programming procedure added
10.07.02 AG V1.3 FAQ’s added
12.07.2002 MSt V1.4 Typo’s corrected
18.07.2002 AG V1.5 Code of check_mode_byte.prc set to I-RAM
29. Oct. 02 DFi V1.6 New format, adapted to new procedure files for flash
programming
22. Sept. 03 DFi V1.7 corrected Table 4, ROMA=1 internal ROM mode
07. Nov. 03 DFi V1.8 corrected typos
This document contains 35 pages.

Warranty and Disclaimer
©Fujitsu Microelectronics Europe GmbH - 3 - AN-910011-18
Warranty and Disclaimer
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Contents
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Contents
REVISION HISTORY ............................................................................................................2
WARRANTY AND DISCLAIMER..........................................................................................3
CONTENTS ..........................................................................................................................4
0INTRODUCTION ..............................................................................................................6
1THE FR EMULATION SYSTEM .......................................................................................7
1.1 Hardware of the Emulation System for the FR-family...............................................7
1.2 Evaluation chip MB91FV360....................................................................................8
1.3 Softune Workbench Debugger.................................................................................8
2MB91FV360 OPERATING MODES..................................................................................9
3SETTING THE MB91FV360 TO EXTERNAL ROM-MODE ............................................12
3.1 Routing the CS0-line to the external RAM of the emulation adapter board ............13
3.2 Configuration of the debugger ...............................................................................13
3.3 Set mode pins MD0-MD2 on the starterkit .............................................................14
3.4 Start the debugger without loading the target.........................................................14
3.5 Setting the mode pin MD0 at dipswitch S1 (Figure 6) to OFF ................................15
3.6 Call the batch file ...................................................................................................15
3.7 FAQ’s ....................................................................................................................17
3.7.1 Verify error at address 0x1FFFF8 ............................................................17
3.7.2 Verify error at address of area between 0x80000 and 0xFFFFF .............. 18
4SETTING THE MB91FV360 TO INTERNAL ROM MODE AND PROGRAMMING THE
INTERNAL FLASH.........................................................................................................19
4.1 Start debugging without programming the FLASH memory ...................................19
4.2 Programming the internal FLASH memory ............................................................20
4.2.1 Routing of the chip select CS0 signal.......................................................21
4.2.2 Generation of the binary file .....................................................................21
4.2.3 Adaption of prog_flash.prc file..................................................................21
4.2.4 Summary .................................................................................................22
5APPENDIX .....................................................................................................................23
5.1 Comparison between debugging with external SRAM and internal FLASH memory
..............................................................................................................................23
5.2 Source Code of the procedure files........................................................................23
5.2.1 CS0_ADR_000000h.PRC ........................................................................23
5.2.2 CS0_ADR_180000h.PRC ........................................................................24

Contents
©Fujitsu Microelectronics Europe GmbH - 5 - AN-910011-18
5.2.3 PLL_32MHz.PRC.....................................................................................24
5.2.4 prog_flash.prc ..........................................................................................25
5.2.5 set_EVA_mode.PRC................................................................................25
5.2.6 flash.prc ...................................................................................................26
5.2.7 start_FLASH.prc ......................................................................................31
5.2.8 start_RAM.prc..........................................................................................33

Introduction
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0 Introduction
This document describes the procedure to start an emulator debugging session. There are 2
possible approaches:
1. Using external RAM for program code
2. Using MCU internal Flash memory for program code
Acomparison between these 2 possibilities is listed in section 5.1

Chapter 1 The FR Emulation System
©Fujitsu Microelectronics Europe GmbH - 7 - AN-910011-18
1 The FR Emulation System
1.1 Hardware of the Emulation System for the FR-family
Fujitsu provides a complete emulation system for their 32bit RISC-MCU’s of the MB91360-
serie.
Figure 1 shows this emulation system, it consists of the Main Unit MB2197-01, the
Evaluation-Board MB2197-120 and the target StarterkitMB91360. All devices what are
connected to the MCU at the target board of emulation system at Figure 1 are supplied with
5V. The MB91360 evaluation chip does not support a 3.3 V bus interface. Instead of the
Starterkit the user can use its own target board. If 3.3V devices are connected to the
external bus the 5V bus voltage level of the evaluation chip must be transformed. The bus
voltage level is transformed by the “level-shifter-board”. This board is available and
completes the emulation system to support specific hardware with 3.3V devices at the
external bus.
Figure 1 Emulation system for MB91360-serie
The Evaluation-chip of this series is the MB91FV360. This chip can be used for emulating
software for each derivative of the MB91360 series.
MB2197-120 :
Emulation Adapter Board
-MB91FV360
-1MB Emulation SRAM
-1MB additonal FlashROM
-Trace-RAM
-Routing for CS, Oscillator
MB2197-127:
Probecable / Headerboard
User Target System
StarterkitMB91360
with NQPACK
-type socket
MB2197-01 :
Emulator Main Unit for FR
Handles communication
PC DSU (on Eva-Chip)
MB2197
-
10 :
DSU Interface (depending of device)

Chapter 1 The FR Emulation System
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1.2 Evaluation chip MB91FV360
The Evaluation-Chip MB91FV360 covers the features of all devices of the MB91360 family
and is located on the evaluation-board. This Eva-chip can emulate software for all MB91360-
devices. It possess 512 KB internal flash memory at the address 0x80000-0xFFFFF
according to the most 360-flash-devices.
Thus the emulator has two locations to keep the code of the application:
1. external SRAM located at the evaluation-board
2. internal flash of the evaluation chip MB91FV360
1.3 Softune Workbench Debugger
The Emulation system (shown in 1.1) can be connected to a PC via LAN- or RS232-
interface. The debugger of Softune Workbench (installed on PC) completes the emulation
system and provides the interface to the user. Via this interface the user can operate the
emulation system.
Before an application can be debugged the code must be loaded to the emulation system.
The code can be loaded to the SRAM of the evaluation-board or can be programmed to the
flash-memory of the evaluation chip.
The procedure to load the code located at 0x80000-0xFFFFF to the external SRAM is
different than programming the code to the internal flash memory of the Eva-chip.
After the debugger of Softune’s Workbench is started the code is usually loaded to the
emulator via the debugger menu “Debug->Load target”- this means that the code is loaded
to the SRAM located at the Evaluation board. Therefore it is necessary that the SRAM of the
Evaluation board can be accessed.
To emulate application where the code is located at the addresses 0x80000 to
0xFFFFF, the Eva-Chip must be set to EXTERNAL-ROM-mode because the debugger
can upload the code only to the external SRAM of the evaluation board. The debugger can’t
upload the code to the MCU-internal flash memory.

Chapter 2 MB91FV360 Operating modes
©Fujitsu Microelectronics Europe GmbH - 9 - AN-910011-18
2MB91FV360 Operating modes
Before the procedures for loading the code are described it is necessary to point out some
details of the different operating modes of the MCU.
All MCU’s (with external bus interface) of the MB91360-serie can be set to Internal ROM-
mode or to External ROM-mode.Figure 2 shows the memory map of these devices.
Internal ROM mode External ROM mode
Figure 2 operating mode’s of the MB91360‘s
The important difference between both modes is the access to addresses of the area
0x40000-0xFFFFF.
Internal ROM-mode External ROM-mode
•all accesses at addresses between
0x40000 and 0xFFFFF are accesses to
internal resources
•All accesses at addresses between
0x40000 and 0xFFFFF are accesses via
the external bus interface.
•Internal resources like Fast-RAM, Boot-
ROM and Flash memory are disabled
and can’t be accessed
Table 1 details of each operating mode
00:0000
00:07FF
00:1000
01:0000
01:FFFF
03:C000
03:FFFF
04:0000
04:3FFC
DMA
I-RAM
Data RAM (16k)
Fast RAM
CAN
512k FLASH ROM
00:0000
00:07FF
00:1000
01:0000
01:FFFF
03:C000
03:FFFF
04:0000
04:3FFC
IO Area
DMA
I-RAM
Data RAM (16k)
external access
area can be used for
emulation

Chapter 2 MB91FV360 Operating modes
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The operating mode is defined by the value of the ROMA-bit of the register MODR. The user
can’t influence the setting of MODR directly. This register is set at reset automatically. At
reset the address 0xFFFF8 (mode byte in vector table) is read and the value is set to
MODR. After reset the value of MODR can’t be changed.
ROMA mode comment
0external ROM
mode
F-bus area*1) disabled
1internal ROM mode F-bus area*1) enabled
Table 2 ROMA-bit setting
*1) F-bus area: resources (Fast-RAM, Boot-ROM, flash memory) are located in the area
between 0x40000-0xFFFFF
The user can influence the operation mode by setting the mode byte at the address
0xFFFF8.
Depending on the setting of the ROMA-bit of MODR the MCU is set to External- or Internal
ROM-mode.
At reset the mode byte is read from address 0xFFFF8 and the reset-vector is read from
address 0xFFFFC. Both vectors can be read from two locations, either from internal or
from external memory. The level at pin MD0 defines whether these vectors are read
from internal area or from external memory.
Mode Pins
MD2 MD1 MD0
Reset vector and mode data
are read…
0 0 0 from internal flash memory
(fixed value, can’t be
programmed)
0 0 1 from external memory
Table 3 mode pin MD0
The values at the addresses 0xFFFF8 (mode byte) and 0xFFFFC (reset vector) determine
the behaviour of the MCU after reset.
The internal values at these addresses are fixed and can’t be programmed. The internal
mode byte sets the MCU to INTERNAL ROM mode.
Thus the MCU can only be set to EXTERNAL ROM mode, when pin MD0 is set to high and
the ROMA bit at the external address is set to low.

Chapter 2 MB91FV360 Operating modes
©Fujitsu Microelectronics Europe GmbH - 11 - AN-910011-18
Row 3 of Table 4 shows the necessary conditions to set the MCU to External ROM-mode.
pin value mode byte operating mode
MD0 = 0 value is fix INTERNAL ROM mode
MD0 = 1 MODR.ROMA = 1 INTERNAL ROM mode
MD0 = 1 MODR.ROMA = 0 EXTERNAL ROM
mode
Table 4

Chapter 3 Setting the MB91FV360 to External ROM-mode
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3 Setting the MB91FV360 to External ROM-mode
The MCU can be set to External-ROM mode only if mode data is read (at reset) from
external memory. Immediately after power-on, the MCU can’t be set to external ROM mode
by one step. After power on the contents of the external SRAM is undefined. Invalid mode
data can set the MCU to an undefined mode. To avoid that invalid mode data are read at
reset, the MCU is set to internal ROM mode at first.
Then mode data can be set to a valid value and at the next reset the MCU can be set to the
external ROM mode.
The following steps (Figure 3) set the MCU to external ROM-mode and allow the loading of
the application to the emulation RAM of the Eva-board.
Figure 3 sequence to set the MCU to external ROM mode
set MCU to internal ROM mode
settings:
MD0-MD2 to GND (dipswitch S1:MD0-MD2 to ON)
action:
Start debugger
MCU:
internal ROM mode
set MCU to external ROM mo
de
settings:
MD0 to VCC (dipswitch S1:MD0 to OFF)
action:
set mode data and reset vector
reset MCU in external memory
MCU:
external ROM
mode
Start

Chapter 3 Setting the MB91FV360 to External ROM-mode
©Fujitsu Microelectronics Europe GmbH - 13 - AN-910011-18
Fujitsu provides a set of batch files (start_ram.prc, etc.), which can be called form the
debugger of Softune Workbench. “start_ram.prc” is the main procedure file which calls other
procedure files as subroutines. Sub-procedure files are CS0_ADR_000000h.prc,
PLL_32MHz.prc and set_EVA_mode.prc.
The sequence of “start_ram.prc” sets the mode byte and reset-vector to dedicated values in
external memory. When mode pin MD0 is set to high (dipswitch S1:MD0 to OFF) these
values are read at the next reset and set the MCU to external ROM-mode.
After power on of the evaluation board, the following sequence should be kept to set the
MCU in the external ROM-mode.
3.1 Routing the CS0-line to the external RAM of the emulation adapter board
On the emulation adapter board: routing of CS0 to the SRAM, jumper S5 and S6 of CS0 to
right position
Figure 4 enabling chip select CS0 at the Eva-board
3.2 Configuration of the debugger
In the debugger configuration, a procedure file can be specified which is started before the
code is loaded to the emulator. Choose the batch file “start_ram.prc”. It is useful to disable
the automatic loading of the application at start of the debugger.
Figure 5 configuration of the debugger
jumper setting
for chip select
CS0
automatic loading of
the application at
start of the debugger
should be disabled
batch file
start_ram.prc has
to be called before
the code is loaded
to the emulator

Chapter 3 Setting the MB91FV360 to External ROM-mode
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3.3 Set mode pins MD0-MD2 on the starterkit
Set all mode pins MD0-MD2 to GND (dipswitch S1 all to ON) and jumper J7 to GND. These
mode pin settings set the MCU to internal ROM-mode at next reset, what is executed when
debugger is started.
Figure 6 enabling the dipswitch and setting the mode pins at the starterkit
3.4 Start the debugger without loading the target
Figure 7 starting the debugger
Mode pin MD0 should be set to GND (dipswitch S1:MD0 to ON). The start of the debugger
of Softune’s Workbench resets the MCU to internal mode. Now mode data and reset vector
can be set in external SRAM by the sequence of the batch file “start_ram.prc”. This batch file
is called before the application is loaded to the emulator.
set the mode
pins via
dipswitch S1
jumper J7
enables the
dipswitch S1

Chapter 3 Setting the MB91FV360 to External ROM-mode
©Fujitsu Microelectronics Europe GmbH - 15 - AN-910011-18
3.5 Setting the mode pin MD0 at dipswitch S1 (Figure 6) to OFF
MD0 is set to high. The level at pin MD0 is high when MD0 at dipswitch S1 on the Starterkit
(see Figure 6 ) is set to OFF. At next reset, the mode byte is read from external memory.
3.6 Call the batch file
Figure 8 load the application to the emulator
If the debugger is configured as recommended, the batch file is called automatically before
the application is loaded. Figure 8 shows how to load the application. The batch file sets the
mode byte in external memory and resets the MCU to external ROM-mode. Afterwards the
application is loaded to the external memory.
If no „verify-error“ is displayed, the downloading was successful completed.
Beside the automatically execution of the procedure file before loading the application (set in
the debugging configuration, refer to section 3.2), the procedure file can be called manually
via the command window of the debugger (Figure 9) or by the command
batch start_ram.prc.

Chapter 3 Setting the MB91FV360 to External ROM-mode
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Figure 9 command window of the debugger

Chapter 3 Setting the MB91FV360 to External ROM-mode
©Fujitsu Microelectronics Europe GmbH - 17 - AN-910011-18
3.7 FAQ’s
3.7.1 Verify error at address 0x1FFFF8
Figure 10 Verify error during setting the mode byte
Meaning:mode byte could not be set
Cause:CS0 not routed to external RAM
Solution:check routing of signal CS0 according Figure 4
Cause:MCU is set to invalid operating mode because of invalid mode data
Solution:set mode pin MD0 to low ( MDO at dipswitch S1 to on) and click reset button at
debugger of Softune Workbench.
Afterwards set mode pin MD0 to high ( MDO at dipswitch S1 to off) and call the batch file
(Figure 8)
*2)
•
when mode byte is set, MCU is in internal
ROM mode
•between 0x40000 and 0x
FFFFF external
access is not possible
•
therefore external 1MB RAM is mapped to
area 0x180000 to 0x1FFFFF via CS0 and
mode byte is set at address 0x1FFFF8
instead of at address 0xFFFF8
mode byte could not
be set at external
memory
*2)

Chapter 3 Setting the MB91FV360 to External ROM-mode
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3.7.2 Verify error at address of area between 0x80000 and 0xFFFFF
Figure 11 Verify error during loading the code
Meaning:application could not be loaded to external SRAM
Cause:MCU is not set to external ROM mode
Solution:check routing CS0
set MD0 to low
click reset button of debugger of Softune Workbench
set MD0 to high
call menu Debug->Load Target
code of the
application could
not be loaded

Chapter 4 Setting the MB91FV360 to Internal ROM mode and programming the internal flash
©Fujitsu Microelectronics Europe GmbH - 19 - AN-910011-18
4 Setting the MB91FV360 to Internal ROM mode and
programming the internal flash
To set the MB91FV360 to internal ROM mode, the value at pin MD0 is set to GND (Figure 6:
dipswitch S1:MD0 to ON).
In this mode, the code in the area 0x80000-0xFFFFF can’t be loaded to the external SRAM.
But the application can be programmed into the internal flash memory of the Eva-chip and
can be executed there.
FME provides a set of batch-files and the according routines to program the internal flash
memory of the Evaluation-chip.
If the application shall be debugged in the internal FLASH memory, two cases must be
considered:
1. The internal FLASH memory is already programmed.
2. The application must be programmed into the internal FLASH memory.
4.1 Start debugging without programming the FLASH memory
If the internal FLASH memory contains the application code already, the debugging session
can be started without programming the FLASH. In this case, the procedure file
“start_flash.prc” must be executed before loading the target file. This can be done
automatically in the debugger configuration as shown in Figure 12. Note that the “Auto load
when starting debug” option is enabled. The Modepins MD0, MD1 and MD2 must be set to
GND (Figure 6: dipswitch S1: MD0, MD1 and MD2 to ON). It is not necessary to route the
chip select signal CS0 to the external SRAM on the emulation adapter board.
Figure 12: Configuration of debugger for debugging in flash memory.
The procedure file “start_flash.prc” calls the following procedure files as sub-functions:
CS0_ADR_180000h.prc, PLL_32MHz.prc.

Chapter 4 Setting the MB91FV360 to Internal ROM mode and programming the internal flash
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4.2 Programming the internal FLASH memory
If the FLASH memory does not contain the application code, it must be programmed before
the debugging session can be started.
Figure 13 shows the programming procedure.
Figure 13 programming the internal flash of the MB91FV360
The programming is performed through the procedure file “prog_flash.prc”. This can be done
automatically in the debugger configuration as shown in Figure 12 (with changed procedure
filename). Note that the “Auto load when starting debug” option is enabled. The Modepins
MD0, MD1 and MD2 must be set to GND (Figure 6: dipswitch S1: MD0, MD1 and MD2 to
ON).
The procedure file “prog_flash.prc” calls the following procedure files as sub-functions:
start_flash.prc and flash.prc.
The procedure file “flash.prc” calls the following procedure file as sub-function:
CS0_ADR_180000h.prc.
Furthermore the flash programming routines, which are uploaded to the MCU by the
flash.prc procedure file, must be present in the PRC\ subdirectory. These routines are
contained in the abs-file: “flash.abs”.
set CS0 to area 0x180000-
0x1FFFFF
End
erase
flash
Start
flash empty ?
•
load application to external
SRAM
•load debug info
•copy code from SRAM to flash