Fujitsu MB91260B Series User manual

Corporate names revised in the documents
The Fujitsu Limited reorganized its LSI business into a wholly owned subsidiary, the Fujitsu
Microelectronics Limited on March 21, 2008.
The corporate names “Fujitsu” and “Fujitsu Limited” described all in this document have been
revised to the “Fujitsu Microelectronics Limited”. Thank you for your cooperation and understanding
this notice.
Moreover, there are no changes in the related documents other than corporate names revised.
Customers are advised to consult with sales representatives before ordering.
March 21, 2008
Fujitsu Microelectronics Limited

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91260B Series
HARDWARE MANUAL
CM71-10127-2E

FUJITSU LIMITED
FR60Lite
32-BIT MICROCONTROLLER
MB91260B Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

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PREFACE
■Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
The FR family is a line of single-chip microcontrollers based on a 32-bit high-performance RISC CPU and
integrating a variety of I/O resources for embedded control applications which require high - performance,
high-speed CPU processing.
The MB91260B is designed to be best suited for embedded applications which require high-performance
processing power of the CPU, such as DVD players, printers, TV sets, and the PDP control.
The MB91260B series is a line of CPUs in the FR60Lite implemented by FR family.
This manual describes the functions and operations of the MB91260B Series for engineers who develop
products using the MB91260B Series. Please read through this manual.
■Trademarks
FR is the abbreviation of FUJITSU RISC CONTROLLER, which is a product of Fujitsu Limited.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■Sample Program
We provide sample programs free of charge to operate peripheral functions of the F2MC-16LX family. The
programs can be used to check the operational specification and usage of our microcontroller device.
MPU/MCU Support Information
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
Note: The sample programs are subject to change without notice. The software is designed to show the
standard operation and usage of the product, therefore, it must be used after full evaluation before
using it on your system. Moreover, we assume no liability for any damage resulting from or caused
by the use of the programs.
■Organization of this document
This manual consists of the following 18 chapters and appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information for understanding the MB91260B series as a whole, covering
its features, block diagram, and functions.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on caution of using devices the MB91260B series.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter describes the basics of the architecture, specifications, and instructions of the MB91260B
series of CPU cores to introduce their features.

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CHAPTER 4 I/O PORTS
This chapter outlines the I/O ports and describes the configuration and functions of their registers.
CHAPTER 5 INTERRUPT CONTROLLER
This chapter outlines the interrupt control, describes its register configuration/functions and its
operations, and gives an example of using the hold request cancel request.
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter describes the external interrupt and NMI controller, the configuration and functions of
registers, and operation of the external interrupt and NMI controller.
CHAPTER 7 REALOS-RELATED HARDWARE
REALOS-related hardware is used by the realtime OS. Therefore, when using REALOS, the hardware
cannot be used with the user program.
CHAPTER 8 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit
reload timer operation.
CHAPTER 9 PPG (Programmable Pulse Generator)
This chapter describes the overview of the PPG (Programmable Pulse Generator) timer, the
configuration and functions of registers, and the operation of the PPG timer.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
This chapter explains the overview of the pulse width counter (PWC), the register configuration and
functions and the counter operation.
CHAPTER 11 MULTIFUNCTIONAL TIMER
This chapter explains the overview of the multifunction timer, the configuration and functions of
registers, and operation of the multifunction timer.
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation)
This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER
operation.
CHAPTER 13 UART
This chapter describes the overview of the UART, the configuration and functions of registers, and
UART operation.
CHAPTER 14 8/10-BIT A/D CONVERTER
This chapter describes the overview of the 8/10-bit A/D converter, the configuration and functions of
registers, and the operation of the 8/10-bit A/D converter.
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
This chapter explains the overview of the multiply and accumulate circuit, the configuration and
functions of registers, and the macro (the definition and each instruction) of the multiply and
accumulate circuit.
CHAPTER 16 DMAC (DMA Controller)
This chapter explains the overview of the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 17 FLASH MEMORY
This chapter describes an overview of flash memory and the configuration and functions of registers,
access modes, automatic algorithm and sector protect operations.

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CHAPTER 18 SERIAL PROGRAMMING CONNECTION
This chapter describes basic configuration of serial programming and examples of the connection.
APPENDIX
This appendix contains the following items: I/O map, interrupt vector, pin status list, notes when little
endian area is used, instruction lists, and the precautions on handling.

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Copyright ©2005-2006 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no
liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such
information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with
above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export
of those products from Japan.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Overview ............................................................................................................................................. 2
1.2 Block Diagram .................................................................................................................................... 4
1.3 Package Dimension ............................................................................................................................ 5
1.4 Pin Assignment ................................................................................................................................... 7
1.5 Pin Description .................................................................................................................................... 9
1.6 I/O Circuit Types ............................................................................................................................... 18
CHAPTER 2 HANDLING DEVICES ................................................................................ 21
2.1 Handling Devices .............................................................................................................................. 22
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 25
3.1 Memory Space .................................................................................................................................. 26
3.2 Internal Architecture .......................................................................................................................... 28
3.3 Programming Model ......................................................................................................................... 33
3.4 Data Structure ................................................................................................................................... 40
3.5 Word Alignment ................................................................................................................................ 41
3.6 Memory Map ..................................................................................................................................... 42
3.7 Branch Instructions ........................................................................................................................... 45
3.8 EIT (Exception/Interrupt/Trap) .......................................................................................................... 48
3.8.1 Interrupt Level .............................................................................................................................. 49
3.8.2 ICR (Interrupt Control Register) ................................................................................................... 51
3.8.3 SSP (System Stack Pointer) ........................................................................................................ 52
3.8.4 TBR (Table Base Register) ......................................................................................................... 53
3.8.5 Multi-EIT Servicing ...................................................................................................................... 56
3.8.6 Operation ..................................................................................................................................... 58
3.9 Operation Modes .............................................................................................................................. 62
3.10 Reset (Device Initialization) .............................................................................................................. 64
3.11 Clock Generation Control ................................................................................................................. 70
3.11.1 PLL Control .................................................................................................................................. 71
3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 72
3.11.3 Clock Distribution ......................................................................................................................... 74
3.11.4 Clock Frequency Division ............................................................................................................ 75
3.11.5 Block Diagram of the Clock Generation Control Unit .................................................................. 76
3.11.6 Registers in the Clock Generation Control Unit ........................................................................... 77
3.11.7 Peripheral Circuits in the Clock Control Unit ............................................................................... 90
3.12 Device Status Control ....................................................................................................................... 93
CHAPTER 4 I/O PORTS ................................................................................................ 101
4.1 Overview of I/O Ports ...................................................................................................................... 102
4.2 Registers of I/O Port ....................................................................................................................... 104
4.3 Analog Input Ports .......................................................................................................................... 110