Fujitsu MB91260B Series User manual

Corporate names revised in the documents
The Fujitsu Limited reorganized its LSI business into a wholly owned subsidiary, the Fujitsu
Microelectronics Limited on March 21, 2008.
The corporate names “Fujitsu” and “Fujitsu Limited” described all in this document have been
revised to the “Fujitsu Microelectronics Limited”. Thank you for your cooperation and understanding
this notice.
Moreover, there are no changes in the related documents other than corporate names revised.
Customers are advised to consult with sales representatives before ordering.
March 21, 2008
Fujitsu Microelectronics Limited

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60Lite
32-BIT MICROCONTROLLER
MB91260B Series
HARDWARE MANUAL
CM71-10127-2E

FUJITSU LIMITED
FR60Lite
32-BIT MICROCONTROLLER
MB91260B Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

i
PREFACE
■Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
The FR family is a line of single-chip microcontrollers based on a 32-bit high-performance RISC CPU and
integrating a variety of I/O resources for embedded control applications which require high - performance,
high-speed CPU processing.
The MB91260B is designed to be best suited for embedded applications which require high-performance
processing power of the CPU, such as DVD players, printers, TV sets, and the PDP control.
The MB91260B series is a line of CPUs in the FR60Lite implemented by FR family.
This manual describes the functions and operations of the MB91260B Series for engineers who develop
products using the MB91260B Series. Please read through this manual.
■Trademarks
FR is the abbreviation of FUJITSU RISC CONTROLLER, which is a product of Fujitsu Limited.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as
defined by Philips.
■Sample Program
We provide sample programs free of charge to operate peripheral functions of the F2MC-16LX family. The
programs can be used to check the operational specification and usage of our microcontroller device.
MPU/MCU Support Information
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
Note: The sample programs are subject to change without notice. The software is designed to show the
standard operation and usage of the product, therefore, it must be used after full evaluation before
using it on your system. Moreover, we assume no liability for any damage resulting from or caused
by the use of the programs.
■Organization of this document
This manual consists of the following 18 chapters and appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information for understanding the MB91260B series as a whole, covering
its features, block diagram, and functions.
CHAPTER 2 HANDLING DEVICES
This chapter provides precautions on caution of using devices the MB91260B series.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter describes the basics of the architecture, specifications, and instructions of the MB91260B
series of CPU cores to introduce their features.

ii
CHAPTER 4 I/O PORTS
This chapter outlines the I/O ports and describes the configuration and functions of their registers.
CHAPTER 5 INTERRUPT CONTROLLER
This chapter outlines the interrupt control, describes its register configuration/functions and its
operations, and gives an example of using the hold request cancel request.
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter describes the external interrupt and NMI controller, the configuration and functions of
registers, and operation of the external interrupt and NMI controller.
CHAPTER 7 REALOS-RELATED HARDWARE
REALOS-related hardware is used by the realtime OS. Therefore, when using REALOS, the hardware
cannot be used with the user program.
CHAPTER 8 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit
reload timer operation.
CHAPTER 9 PPG (Programmable Pulse Generator)
This chapter describes the overview of the PPG (Programmable Pulse Generator) timer, the
configuration and functions of registers, and the operation of the PPG timer.
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement)
This chapter explains the overview of the pulse width counter (PWC), the register configuration and
functions and the counter operation.
CHAPTER 11 MULTIFUNCTIONAL TIMER
This chapter explains the overview of the multifunction timer, the configuration and functions of
registers, and operation of the multifunction timer.
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation)
This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER
operation.
CHAPTER 13 UART
This chapter describes the overview of the UART, the configuration and functions of registers, and
UART operation.
CHAPTER 14 8/10-BIT A/D CONVERTER
This chapter describes the overview of the 8/10-bit A/D converter, the configuration and functions of
registers, and the operation of the 8/10-bit A/D converter.
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
This chapter explains the overview of the multiply and accumulate circuit, the configuration and
functions of registers, and the macro (the definition and each instruction) of the multiply and
accumulate circuit.
CHAPTER 16 DMAC (DMA Controller)
This chapter explains the overview of the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 17 FLASH MEMORY
This chapter describes an overview of flash memory and the configuration and functions of registers,
access modes, automatic algorithm and sector protect operations.

iii
CHAPTER 18 SERIAL PROGRAMMING CONNECTION
This chapter describes basic configuration of serial programming and examples of the connection.
APPENDIX
This appendix contains the following items: I/O map, interrupt vector, pin status list, notes when little
endian area is used, instruction lists, and the precautions on handling.

iv
Copyright ©2005-2006 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no
liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such
information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with
above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export
of those products from Japan.

v
CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Overview ............................................................................................................................................. 2
1.2 Block Diagram .................................................................................................................................... 4
1.3 Package Dimension ............................................................................................................................ 5
1.4 Pin Assignment ................................................................................................................................... 7
1.5 Pin Description .................................................................................................................................... 9
1.6 I/O Circuit Types ............................................................................................................................... 18
CHAPTER 2 HANDLING DEVICES ................................................................................ 21
2.1 Handling Devices .............................................................................................................................. 22
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 25
3.1 Memory Space .................................................................................................................................. 26
3.2 Internal Architecture .......................................................................................................................... 28
3.3 Programming Model ......................................................................................................................... 33
3.4 Data Structure ................................................................................................................................... 40
3.5 Word Alignment ................................................................................................................................ 41
3.6 Memory Map ..................................................................................................................................... 42
3.7 Branch Instructions ........................................................................................................................... 45
3.8 EIT (Exception/Interrupt/Trap) .......................................................................................................... 48
3.8.1 Interrupt Level .............................................................................................................................. 49
3.8.2 ICR (Interrupt Control Register) ................................................................................................... 51
3.8.3 SSP (System Stack Pointer) ........................................................................................................ 52
3.8.4 TBR (Table Base Register) ......................................................................................................... 53
3.8.5 Multi-EIT Servicing ...................................................................................................................... 56
3.8.6 Operation ..................................................................................................................................... 58
3.9 Operation Modes .............................................................................................................................. 62
3.10 Reset (Device Initialization) .............................................................................................................. 64
3.11 Clock Generation Control ................................................................................................................. 70
3.11.1 PLL Control .................................................................................................................................. 71
3.11.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ...................................................... 72
3.11.3 Clock Distribution ......................................................................................................................... 74
3.11.4 Clock Frequency Division ............................................................................................................ 75
3.11.5 Block Diagram of the Clock Generation Control Unit .................................................................. 76
3.11.6 Registers in the Clock Generation Control Unit ........................................................................... 77
3.11.7 Peripheral Circuits in the Clock Control Unit ............................................................................... 90
3.12 Device Status Control ....................................................................................................................... 93
CHAPTER 4 I/O PORTS ................................................................................................ 101
4.1 Overview of I/O Ports ...................................................................................................................... 102
4.2 Registers of I/O Port ....................................................................................................................... 104
4.3 Analog Input Ports .......................................................................................................................... 110

vi
CHAPTER 5 INTERRUPT CONTROLLER ................................................................... 113
5.1 Overview ......................................................................................................................................... 114
5.2 Interrupt Control Registers .............................................................................................................. 118
5.3 Operation of Interrupt Controller ..................................................................................................... 120
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 129
6.1 Overview of External Interrupt/NMI Controller ................................................................................ 130
6.2 Registers of External Interrupt/NMI Controller ................................................................................ 132
6.3 Operation of External Interrupt/NMI Controller ............................................................................... 134
CHAPTER 7 REALOS-RELATED HARDWARE .......................................................... 141
7.1 Delayed Interrupt Module ............................................................................................................... 142
7.2 Register of Delayed Interrupt Module ............................................................................................. 143
7.3 Operation of Delayed Interrupt Module ........................................................................................... 144
7.4 Bit Search Module .......................................................................................................................... 145
7.5 Register of Bit Search Module ........................................................................................................ 146
7.6 Operation of Bit Search Module ...................................................................................................... 148
CHAPTER 8 16-BIT RELOAD TIMER ........................................................................... 151
8.1 Overview ......................................................................................................................................... 152
8.2 16-bit Reload Timer Block Diagram ................................................................................................ 153
8.3 16-bit Reload Timer Registers ........................................................................................................ 154
8.4 Operation of 16-bit Reload Timer ................................................................................................... 158
CHAPTER 9 PPG (Programmable Pulse Generator) ................................................. 163
9.1 Overview ......................................................................................................................................... 164
9.2 Block Diagram ................................................................................................................................ 168
9.3 Register of PPG .............................................................................................................................. 172
9.4 Operation Explanation .................................................................................................................... 177
CHAPTER 10 PWC (Pulse Width Count: Pulse Width Measurement) ....................... 183
10.1 Overview ......................................................................................................................................... 184
10.2 Block Diagram ................................................................................................................................ 185
10.3 Register of PWC ............................................................................................................................. 186
10.4 Operation Explanation .................................................................................................................... 192
CHAPTER 11 MULTIFUNCTIONAL TIMER ................................................................... 203
11.1 Overview ......................................................................................................................................... 204
11.2 Block Diagram ................................................................................................................................ 206
11.3 Pins of Multifunctional Timer ........................................................................................................... 212
11.4 Multifunctional Timer Register ........................................................................................................ 213
11.4.1 Compare Clear Buffer Register (CPCLRBH, CPCLRBL) /Compare Clear Register (CPCLRH,
CPCLRL) 218
11.4.2 Timer Data Register (TCDTH, TCDTL) ..................................................................................... 220
11.4.3 Timer State Control Register (TCCSH, TCCSL) ....................................................................... 221
11.4.4 A/D Trigger Control Register (ADTRGC) ................................................................................... 226

vii
11.4.5 Output Compare Buffer Register (OCCPBH0 to OCCPBH5, OCCPBL0 to OCCPBL5) / Output
Compare Register (OCCPH0 to OCCPH5, OCCPL0 to OCCPL5) 227
11.4.6 Compare Control Register (OCSH0 to OCSH5, OCSL0 to OCSL5) ......................................... 229
11.4.7 Compare Mode Control Register (OCMOD) .............................................................................. 234
11.4.8 Input Capture Data Registers (IPCPH0 to IPCPH3, IPCPL0 to IPCPL3) .................................. 236
11.4.9 Input Capture State Control/PPG Output Control Register (ICSH23, ICSL23, PICSH01, PICSL01)
237
11.4.10 16-bit Dead Timer Register (TMRRH0 to TMRRH2, TMRRL0 to TMRRL2) ............................. 244
11.4.11 16-bit Dead Timer Control Register (DTCR0 to DTCR2) ........................................................... 245
11.4.12 Waveform Control Register (SIGCR1, SIGCR2) ....................................................................... 251
11.4.13 A/D Activation Compare Register (ADCOMP0, ADCOMP1, ADCOMP2, ADCOMPC) ............. 254
11.5 Multifunctional Timer Interrupt ........................................................................................................ 256
11.6 Operation of Multifunctional Timer .................................................................................................. 260
11.6.1 Operation of 16-bit Free-run Timer ............................................................................................ 261
11.6.2 Operation of 16-bit Output Compare ......................................................................................... 267
11.6.3 Operation of 16-bit Input Capture .............................................................................................. 277
11.6.4 Waveform Generator Operation ................................................................................................ 279
11.6.4.1 Operation of Timer Mode ........................................................................................................ 283
11.6.4.2 Operation During Dead Time Timer Mode ............................................................................. 285
11.6.4.3 DTTI Pin Control Operation .................................................................................................... 289
11.6.5 A/D Activation Compare Operation ........................................................................................... 291
11.7 Notes on Using Multifunctional Timer ............................................................................................. 292
11.8 Program Example of Multifunctional Timer ..................................................................................... 294
CHAPTER 12 U-TIMER (16-bit Timer for UART Baud Rate Generation) .................... 297
12.1 Overview ......................................................................................................................................... 298
12.2 Description of Registers .................................................................................................................. 299
12.3 Description of Operation ................................................................................................................. 302
CHAPTER 13 UART ........................................................................................................ 303
13.1 Overview ......................................................................................................................................... 304
13.2 Detail Description of Registers ....................................................................................................... 307
13.3 Operation of UART ......................................................................................................................... 313
13.4 Example of Using the UART ........................................................................................................... 319
13.5 Example of Setting Baud Rates and U-TIMER Reload Values ...................................................... 321
CHAPTER 14 8/10-BIT A/D CONVERTER ..................................................................... 323
14.1 Overview ......................................................................................................................................... 324
14.2 Configuration .................................................................................................................................. 325
14.3 Pin ................................................................................................................................................... 328
14.4 Registers ......................................................................................................................................... 330
14.4.1 A/D Channel Control Register (ADCH) ...................................................................................... 331
14.4.2 A/D Mode Setting Register (ADMD) .......................................................................................... 333
14.4.3 A/D Control Status Register (ADCS) ......................................................................................... 336
14.4.4 A/D Data Register (ADCD) ........................................................................................................ 339
14.4.5 Analog Input Control Register (AICR) ....................................................................................... 340
14.5 Interrupt .......................................................................................................................................... 341

viii
14.6 Operation Explanation .................................................................................................................... 342
14.7 A/D Conversion Data Protection Function ...................................................................................... 346
14.8 Precautions on Using ...................................................................................................................... 347
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR .............................. 349
15.1 Overview ......................................................................................................................................... 350
15.2 Register Description ....................................................................................................................... 355
15.3 Operation Explanation .................................................................................................................... 359
15.4 Instruction Detail Explanation ......................................................................................................... 363
CHAPTER 16 DMAC (DMA Controller) ......................................................................... 367
16.1 Overview ......................................................................................................................................... 368
16.2 Register Details Explanation ........................................................................................................... 371
16.3 Operation Explanation .................................................................................................................... 385
16.4 Setting Up Transfer Request .......................................................................................................... 387
16.5 Transfer Sequence ......................................................................................................................... 388
16.6 Overview of DMA Transfer ............................................................................................................. 390
16.7 Operation Flow ............................................................................................................................... 398
16.8 Data Path ........................................................................................................................................ 400
CHAPTER 17 FLASH MEMORY ..................................................................................... 403
17.1 Overview of Flash Memory ............................................................................................................. 404
17.2 Flash Memory Registers ................................................................................................................. 409
17.2.1 Flash Memory Status Register (FLCR) ..................................................................................... 410
17.2.2 Flash Wait Register (FLWC) ...................................................................................................... 412
17.3 Access Modes of Flash Memory ..................................................................................................... 414
17.4 Starting the Flash Memory Automatic Algorithm ............................................................................ 416
17.5 Automatic Algorithm Execution Status ............................................................................................ 420
17.6 Sector Protect Operation ................................................................................................................ 426
CHAPTER 18 SERIAL PROGRAMMING CONNECTION .............................................. 431
18.1 Overview ......................................................................................................................................... 432
APPENDIX ......................................................................................................................... 437
APPENDIX A I/O Map ................................................................................................................................ 438
APPENDIX B Vector Table ......................................................................................................................... 446
APPENDIX C Pin Status In Each CPU State ............................................................................................. 450
APPENDIX D Notes When Little Endian Area Is Used ............................................................................... 453
APPENDIX E Instruction Lists .................................................................................................................... 460
APPENDIX F Precautions on Handling ...................................................................................................... 475
INDEX................................................................................................................................... 479

ix
Main changes in this edition
Page Changes (For details, refer to main body.)
i■Sample Program is added.
23 ●Note on Operation in PLL Clock Mode is changed.
53 Table 3.8-3 Vector Table (1 / 3) is changed. (Instruction break exception →System-reserved)
(Operand break trap →System-reserved)
66 ●Watchdog reset is changed.
(WPR (watchdog reset defer register) →CTBR (timebase counter clear register))
70
■Selecting the Source Clock Signal is changed.
(φis the base clock that is generated from the source clock divided by two or by using the PLL oscillation.
Therefore, the system base clock is a clock generated in the above-mentioned internal base clock generation.
is added.)
76 Figure 3.11-1 Block Diagram of the Clock Generation Control Unit is changed.
(The WPR register part of [Watchdog controller] is deleted.)
78 The table in [bit9, bit8] WT1,WT0 (Watchdog interval Time select) is changed.
(WPR →CTBR)
78 ■STCR: Standby Control Register is changed.
83
■CTBR: Timebase Counter Clear Register is changed.
(Note, however, that the FF is cleared automatically when the CPU is not operating such as in the stop or
sleep mode or during DMA transfer. If such a condition develops, therefore, a watchdog reset is deferred
automatically. For details, see the section "3.11.7 Peripheral Circuits in the Clock Control Unit". is added.)
85 ■WPR: Watchdog Reset Defer Register in 3.11.6 Registers in the Clock Generation Control Unit is deleted.
90 [Deferring the generation of a watchdog reset] in ●Watchdog timer is changed.
(WPR (watchdog reset defer register) →CTBR (timebase counter clear register))
96 ●Sleep mode is changed.
97 ●Stop mode is changed.
121 Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 3) is changed. (Instruction break exception →System-reserved)
(Operand break trap →System-reserved)
137 ■Precautions when Returning from STOP State Using External Interrupt is added.
138 ■Return Operation from STOP State is added.
304 ■Features of UART is changed.
(•The DMAC interrupt source is cleared by the writing operation to the DRCL register. is deleted.)
305 ■Register List is changed.
(DRCL part is deleted.)
312 ■DRCL is deleted.
318 ■Precautions on Usage is changed.
(Write to the DRCL register before starting DMA transfer by an interrupt for the first time. is deleted.)

x
362 Notes: is added.
445 Appendix Table A-1 I/O Map is changed.
(*3: These are reserved registers. These access are prohibited. is added.)
447 Appendix Table B-1 Vector Table (1 / 3) is changed. (Instruction break exception →System reserved)
(Operand break trap →System reserved)
475 ●Low-power consumption mode is changed.
439, 443 The sections of the following registers in Appendix Table A-1 I/O Map are changed.
(DRCL0, DRCL1, DRCL2, WPR)
Page Changes (For details, refer to main body.)

1
CHAPTER 1
OVERVIEW
This chapter provides basic information for
understanding the MB91260B series as a whole,
covering its features, block diagram, and functions.
1.1 Overview
1.2 Block Diagram
1.3 Package Dimension
1.4 Pin Assignment
1.5 Pin Description
1.6 I/O Circuit Types

2
CHAPTER 1 OVERVIEW
1.1 Overview
The MB91260B series is a line of Fujitsu's general-purpose 32-bit RISC microcontrollers
designed for embedded control applications which require high-speed processing. The
MB91260B contains an FR60Lite CPU core compatible with the FR family of CPUs.
■Features
●FR60Lite CPU
• 32-bit RISC, load/store architecture, five pipelines
• Maximum operating frequency: 33 MHz (oscillation frequency of 4.192 MHz multiplied by 8 (by PLL
clock multiplication)
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed: 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions:
Instructions suitable for embedded applications
• Function entry and exit instructions and register multi-load/store instructions: Instructions compatible
with the C language
• Register interlock function: Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
• Signed 32-bit multiplication: 5 cycles
• Signed 16-bit multiplication: 3 cycles
• Interrupts (PC/PS saving): 6 cycles (16 priority levels)
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instruction-compatible with the FR family
●Built-in peripheral resources
• Built-in ROM capacity and type
MASK ROM: 128 KB (MB91263B), 256 KB (MB91264B)
FLASH ROM: 256 KB (MB91F264B)
• Built-in RAM capacity: 8 KB
• A/D converters (successive approximation type)
Resolution: 10 bits:8 channels ×1 unit, 2 channels ×2 units
Conversion time: 1.2 µs (minimum conversion time at a system clock of 33 MHz)
1.35 µs (minimum conversion time at a system clock of 20 MHz)
• External interrupt inputs: 10 channels
• Bit search module (used by REALOS)
This feature searches for the first bit position causing a 1-to-0 transition in the MSB (most significant
bit) of a word.

3
CHAPTER 1 OVERVIEW
• UART (full duplex, double buffering): 3 channels
Choice of enabling/disabling parity
Choice of clock asynchronous (start-stop) or synchronous communication
Dedicated baud rate timer (U-TIMER) integrated for each channel
Capable of using an external clock as a transfer clock
Detection of parity, frame, and overrun errors
• 8/16-bit PPG timer: 16 channels (in 8-bit mode) / 8 channels (in 16-bit mode)
• 16-bit reload timer: 3 channels (cascade mode available, with no output of reload timer 0)
• 16-bit free-running timer: 1 channel
• 16-bit PWC timer: 2 channels
• Input capture unit: 4 channels (interlocking with the free-running timer)
• Output compare unit: 6 channels (interlocking with the free-running timer)
• Waveform generator
Capable of generating various waveforms using the output compare unit's output, 16-bit PPG timer 0,
and 16-bit dead timer.
• Multiplier-accumulator
RAM: Instruction RAM 256 ×16 bits
XRAM 64 ×16 bits
YRAM 64 ×16 bits
Executes a multiply-accumulate operation (16 bits ×16 bits + 40 bits) in one instruction cycle.
Extracts the operation result by rounding from 40 bits to 16 bits.
• DMAC (DMA Controller): 5 channels
Capable of starting transfer of built-in peripheral interrupts by means of software
• Watchdog timer
• Low-power consumption modes
Sleep and stop modes
●Others
• Package: QFP-100, LQFP-100
• CMOS 0.35 µm technology
• Single power supply [Vcc = 4.0 V to 5.5 V]

4
CHAPTER 1 OVERVIEW
1.2 Block Diagram
This section shows a block diagram of the MB91260B series.
■Block Diagram
Figure 1.2-1 Block Diagram
32 to 16
Adapter
Interrupt
controller
Clock
control
FR 60Lite
CPU Core
Multiply-
accumulate macro
Bit search
Bus
Converter
DMAC 5ch
32
32 32
16
ROM 128KB /
ROM 256KB /
Flash 256KB
RAM 8 KB
8ch
8/16-bit PPG timer
2ch
16-bit PWC timer
3ch
16-bit reload timer
PORT I/F
8ch input
8/10bit A/D-0
3ch
UART
3ch
U-TIMER
2ch input
8/10bit A/D-1
SIN0 to SIN2
SOT0 to SOT2
SCK0 to SCK2
PWI0 to PWI1
PPG0 to PPG15
ADTG1
AVRH1
AN8 to AN9
TIN0 to TIN2
TOT1 to TOT2
X0,X1
MD0 to MD2
INIT
2ch input
8/10bit A/D-2
10ch
external interrupt
INT0 to INT9
NMI
Multifunction timers
Free Run Timer 1ch
Input Capture 4ch
Output compare 6ch
Waveform generator
CKI
DTTI
RTO0 to RTO5
IC0 to IC3
AVcc
ADTG0
AN0 to AN7
AVRH0
ADTG2
AVRH2
AN10 to AN11
PORT

5
CHAPTER 1 OVERVIEW
1.3 Package Dimension
This section shows the package dimension of FPT-100P-M06 and FPT-100P-M05.
■Package Dimension
Figure 1.3-1 FPT-100P-M06 Package Dimensions
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 ×20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(
FPT-100P-M06
)
C
2002 FUJITSU LIMITED F100008S-c-5-5
1 30
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00 +0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8˚
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *: These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.