IDT EB8T5A Eval Board User manual

®
July 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: [phone] • [phone] • FAX: [phone]
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.
IDT™89EBPES8T5A
Evaluation Board Manual
(Eval Board: 18-636-002)

DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a
Failure Analysis be performed.
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Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes
EB8T5A Eval Board Manual i July 23, 2009
Table of Contents
®
Description of the EB8T5A Eval Board
Introduction .....................................................................................................................................1-1
Board Features ...............................................................................................................................1-2
Hardware ................................................................................................................................1-2
Software..................................................................................................................................1-2
Other.......................................................................................................................................1-2
Revision History..............................................................................................................................1-3
Installation of the EB8T5A Eval Board
EB8T5A Installation ........................................................................................................................2-1
Hardware Description .....................................................................................................................2-1
Host System ...........................................................................................................................2-1
Reference Clocks............................................................................................................................2-1
Power Sources................................................................................................................................2-3
External Power Source...........................................................................................................2-3
Vaux Support..........................................................................................................................2-4
PCI Express Serial Data Transmit Termination Voltage Converter........................................2-6
PCI Express Digital Power Voltage Converter........................................................................2-6
PCI Express Analog Power Voltage Converter ......................................................................2-6
Core Logic Voltage Converter ................................................................................................2-6
3.3V I/O Power Module...........................................................................................................2-6
Power-up Sequence ...............................................................................................................2-6
Required Jumpers ..................................................................................................................2-6
Reset...............................................................................................................................................2-6
Fundamental Reset ................................................................................................................2-6
Downstream Reset .................................................................................................................2-7
Boot Configuration Vector...............................................................................................................2-7
SMBus Interfaces............................................................................................................................2-8
SMBus Slave Interface ...........................................................................................................2-8
SMBus Master Interface .......................................................................................................2-10
JTAG Header................................................................................................................................ 2-10
Attention Buttons...........................................................................................................................2-11
Miscellaneous Jumpers, Headers................................................................................................. 2-11
LEDs .............................................................................................................................................2-12
PCI Express Connectors...............................................................................................................2-14
EB8T5A Board Figure...................................................................................................................2-16
Software for the EB8T5A Eval Board
Introduction .....................................................................................................................................3-1
Device Management Software........................................................................................................3-1
Schematics
Schematics .....................................................................................................................................4-1

IDT Table of Contents
EB8T5A Eval Board Manual ii July 23, 2009
Notes

Notes
EB8T5A Eval Board Manual iii July 23, 2009
List of Tables
®
Table 2.1 Clock Source Selection .......................................................................................................2-1
Table 2.2 Clock Frequency Selection .................................................................................................2-2
Table 2.3 Spread Spectrum Clock Selection ......................................................................................2-2
Table 2.4 SMA Connectors - Onboard Reference Clock ....................................................................2-2
Table 2.5 External Power Connector - J4 ...........................................................................................2-3
Table 2.6 Downstream Reset Selection .............................................................................................2-7
Table 2.7 Boot Configuration Vector Signals ......................................................................................2-7
Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1) ................................2-8
Table 2.9 Slave SMBus Interface Connector ......................................................................................2-9
Table 2.10 SMBus Slave Interface Address Configuration ...................................................................2-9
Table 2.11 PES8T5A SMBus Slave Interface Address Setting ............................................................2-9
Table 2.12 EEPROM SMBus Address Setting ...................................................................................2-10
Table 2.13 JTAG Connector Pin Out ..................................................................................................2-11
Table 2.14 Attention Buttons ..............................................................................................................2-11
Table 2.15 Miscellaneous Jumpers, Headers .....................................................................................2-11
Table 2.16 LED Indicators .................................................................................................................. 2-13
Table 2.17 PCI Express x4 Connector Pinout ....................................................................................2-14
Table 2.18 PCI Express x1 Connector Pinout ....................................................................................2-15

IDT List of Tables
EB8T5A Eval Board Manual iv July 23, 2009
Notes

Notes
EB8T5A Eval Board Manual v July 23, 2009
List of Figures
®
Figure 1.1 Function Block Diagram of the EB8T5A Eval Board ..........................................................1-1
Figure 2.1 Clock Distribution Block Diagram .......................................................................................2-3
Figure 2.2 Power Distribution Block Diagram ......................................................................................2-4
Figure 2.3 APWRDIS# Timing ............................................................................................................2-5
Figure 2.4 APWRDIS# Timing Circuit .................................................................................................2-5

IDT List of Figures
EB8T5A Eval Board Manual vi July 23, 2009
Notes

Notes
EB8T5A Eval Board Manual 1 - 1 July 23, 2009
®
Chapter 1
Description of the EB8T5A
Eval Board
Introduction
In this manual, references to the PES8T5A also apply to the PES6T5 and PES5T5 unless otherwise
indicated.
The 89HPES8T5A switch (also referred to as PES8T5A in this manual) is a member of IDT’s PCI
Express® standard (PCIe®) based line of products. It is an 8-lane, 5-port switch. One upstream port is
provided for connecting to the root complex (RC), and up to four downstream ports are available for
connecting to PCIe endpoints or to another switch. More information on this device can be found in the
appropriate User Manual (89HPES8T5A, 89HPES6T5, or 89HPES5T5).
The 89EBPES8T5A Evaluation Board (also referred to as EB8T5A in this manual) provides an evalua-
tion platform for the PES8T5A switch. It is also a cost effective way to add a PCIe downstream port (x1) to
an existing system with a limited number of PCIe downstream ports. The EB8T5A eval board is designed to
function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appro-
priate root complex, microprocessor(s), and four downstream ports. The EB8T5A is a vehicle to test and
evaluate the functionality of the PES8T5A chip. Customers can use this board to get a headstart on soft-
ware development prior to the arrival of their own hardware. The EB8T5A is also used by IDT to reproduce
system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block
diagram representing the main parts of the EB8T5A board.
Figure 1.1 Function Block Diagram of the EB8T5A Eval Board
JTAG
Header
Main
Reset
I/O Expander
PCA9555
PCIe x4 Upstream Edge
EEPROM
24LC512
SMBUS
HEADER
PES8T5A
PCI Express
Switch
External Power
PCIe x1 Downstream Slot
x4 (PES8T5A)
x1
25 MHz
SSC Clock
Buffer
Clock
Fanout
SMBus
Voltages on board
+12V, +3.3V, +1.5V, +1.0V
Connector
Power
Module
PTH08T240
x1
x1
x1
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
PCIe x1 Downstream Slot
x2 (PES6T5)
x1 (PES5T5)

IDT Description of the EB8T5A Eval Board
EB8T5A Eval Board Manual 1 - 2 July 23, 2009
Notes Board Features
Hardware
PCIe 5 port switch
– PES8T5A — Five ports (one x4 port and four x1 ports), 8 PCIe lanes
– PES6T5 — Five ports (one x2 port and four x1 ports), 6 PCIe lanes
– PES5T5 — Five ports (five x1 ports), 5 PCIe lanes
– PCIe Base Specification Revision 1.1 compliant
– Integrates eight 2.5 Gbps embedded SerDes
– Up to 256 byte maximum Payload Size
– Automatic lane reversal and polarity inversion supported on all lanes
– Automatic per port link width negotiation to x4, x2, x1
– Load configuration from an optional serial EEPROM via SMBUS
Upstream, Downstream Port
– One edge connector on the upstream port, to be plugged into a slot with at least x4 capable
mechanical slot connector on a host motherboard
– Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.
Numerous user selectable configurations set using onboard jumpers and DIP-switches
– Source of clock - host clock or onboard clock generator
– Two clock rates and spread spectrum settings
– Boot mode selection
Vaux Support
SMBUS Slave Interface (4 pin header)
SMBUS Master Interface connected to the Serial EEPROMs through I/O expander
“Attention” button for each downstream port to initiate a hot swap event on each port
Four pin connector for optional external power supply
Push button for Warm Reset
Several LEDs to display status, reset, power, “Attention”, etc.
One 14-pin JTAG header
Software
There is no software or firmware executed on the board. However, useful software is provided along
with the Evaluation Board to facilitate configuration and evaluation of the PES8T5A within host systems
running popular operating systems.
Installation programs
– Operating Systems Supported: Windows2000, WindowsXP, Linux
GUI based application for Windows and Linux
– Allows users to view and modify registers in the PES8T5A
– Binary file generator for programming the serial EEPROMs attached to the SMBUS.
Other
A metal bracket is required to firmly hold in place the four endpoints plugged into the EB8T5A
board.
An external power supply may be required under some conditions.
SMBUS cable may be required for certain evaluation exercises.
SMA connectors are provided on the EB8T5A board for specific test points.

IDT Description of the EB8T5A Eval Board
EB8T5A Eval Board Manual 1 - 3 July 23, 2009
Notes Revision History
September 10, 2007: Initial publication of board manual.
July 23, 2009: Added PES6T5 and PES5T5 devices to eval board manual. Updated Power Sources
section, Table 2.15, and Schematics. Added Note after Table 2.17.

IDT Description of the EB8T5A Eval Board
EB8T5A Eval Board Manual 1 - 4 July 23, 2009
Notes

Notes
EB8T5A Eval Board Manual 2 - 1 July 23, 2009
®
Chapter 2
Installation of the EB8T5A
Eval Board
EB8T5A Installation
This chapter discusses the steps required to configure and install the EB8T5A evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Insert the evaluation board into the host system (motherboard with root complex chipset).
4. Apply power to the host system.
The EB8T5A board is shipped with all jumpers and switches configured to their default settings. In most
cases, the board does not require further modification or setup.
Hardware Description
The PES8T5 is an 8-lane, 5-port PCI Express® switch. It is a peripheral chip that performs PCI Express
based switching with a feature set optimized for high performance applications such as servers and
storage. It provides fan-out and switching functions between a PCI Express upstream port and 4 down-
stream ports or peer-to-peer switching between downstream ports.
The EB8T5A has four PCI Express downstream ports, accessible through four x4 open-ended connec-
tors.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting x4 configuration through a PCI Express
x4 slot.
– PCI Express Endpoint Cards capable of training x1 link.
Host System
The evaluation board cannot be operated as a standalone unit. A host system implementing a PCI
Express root complex supporting x4 configuration through a PCI Express x4 slot is required to take full
advantage of the PES8T5’s capabilities.
Reference Clocks
The PES8T5A requires a differential reference clock. The EB8T5A derives this clock from a common
source which is user-selectable. The common source can be either the host system’s reference clock or the
onboard clock generator. Selection is made by resistor switch described in Table 2.1.
Clock Configuration Switch - S3[3]
S3[3] Clock Source
ON Onboard Reference Clock – Use onboard clock generator
OFF Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 2 July 23, 2009
Notes The source for the onboard clock is the ICS9FG104 clock generator device (U8) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the EB8T5A allows selection between multiple
clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.
Spread Spectrum technology reduces peak EMI emissions by modulating the frequency to spread the peak
energy over a wider bandwidth.
If the Clock Spread Spectrum is used to modulate data rate, then both ports must use same modulated
clock source. Therefore, if your system uses SSC, the on-board clock generator must be disabled and the
upstream reference clock should be used instead.
The output of the onboard clock generator is accessible through two SMA connectors located on the
Evaluation Board. See Table 2.4. This can be used to connect a scope for probing or capturing purposes
and cannot be used to drive the clock from an external source.
Figure 2.1 illustrates the clock distribution block diagram for the EB8T5A evaluation board.
Clock Frequency Switch - S3[1]
S3[1] Clock Frequency
OFF 125MHz
ON 100MHz (Default)
Table 2.2 Clock Frequency Selection
Clock Spread Spectrum Switch - S3[2]
S3[2] Spread Spectrum
OFF Enable Spread Spectrum
ON Disable Spread Spectrum (Default)
Table 2.3 Spread Spectrum Clock Selection
Onboard Reference Clock Output (Differential) – J18, J19
J19 Positive Reference Clock
J18 Negative Reference Clock
Table 2.4 SMA Connectors - Onboard Reference Clock

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 3 July 23, 2009
Notes
Figure 2.1 Clock Distribution Block Diagram
Power Sources
Power for the EB8T5A is generated from the 12.0V PCI Express upstream slot power or optionally from
3.3Vaux. A 12.0V to 3.3V DC-DC converter will be used to provide power to four DC-DC converters to
generate VDDcore, VDDpe, VDDpea, and VTT voltages. The 3.3V from the 12.0V converter is used to
power VDDio. When in power down mode the DC-DC converters is powered directly from 3.3Vaux through
a MOSFET switch.
If add-in cards require more power than the upstream slot can support, an external source is required to
supply this extra power via an auxiliary 4-pin power connector on the board. Header W1, W5, and W11 (see
Table 2.15) are used to select the proper power source for the switch and all downstream ports.
External Power Source
If necessary, external power is supplied to the EB8T5A board through a 4-pin auxiliary power connector
attached to J4. The external power supply provides +12V to the EB8T5A as described in Table 2.5. The
+5V is unused.
Pin Signal
1+12V
2GND
3GND
4+5V
Table 2.5 External Power Connector - J4
PEREFCLK0
Port2
Port3
Port4
Port5
Upstream PEREFCLK
25MHz
ICS557-06
ICS9DB803D
SMA - J18,J19
ISC9FG104

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 4 July 23, 2009
Notes
Figure 2.2 Power Distribution Block Diagram
Vaux Support
Power supply support will be provided to EB8T5A from 12.0V upstream power to 3.3Vaux upstream
power when in sleep mode. The WAKE# signal direction, both an input and output will be supported by
jumper selection. The APWRDIS# signal for auxiliary power disable requires the following timing on power-
up.

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 5 July 23, 2009
Notes
Figure 2.3 APWRDIS# Timing
On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it
must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will
not affect the APWRDIS# state. This timing will be provided by the following circuit.
Figure 2.4 APWRDIS# Timing Circuit

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 6 July 23, 2009
Notes PCI Express Serial Data Transmit Termination Voltage Converter
A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown
as VTTPE or VPETVTT) to the PES8T5A.
PCI Express Digital Power Voltage Converter
A separate DC-DC converter (U16) provides a 1.0V PCI Express digital power voltage (VDDPE) to the
PES8T5A.
PCI Express Analog Power Voltage Converter
A separate DC-DC converter (U7) provides a 1.0V PCI Express analog power voltage (shown as
VDDAPE or VDDPEA) to the PES8T5A.
Core Logic Voltage Converter
A separate DC-DC converter (U1) provides the 1.0V core voltage (VDDCORE) to the PES8T5A.
3.3V I/O Power Module
A 12V to 3.3V power module (U5) provides the 3.3V I/O voltage (VDDIO) to the PES8T5A.
Power-up Sequence
The power-up sequence must be as following:
1. VDDIO - 3.3V
2. VDDCORE, VDDAPE, VDDPE - 1.0V
3. VTTPE - 1.5V
When powering up, each voltage level must ramp up and stabilize prior to applying the next voltage in
the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations
between sequential valid power level requirements. To insure that the sequencing requirements are met, a
0.047µF is used at the SOFTSTART cap on the VTTPE’s voltage converter (U6 pin 36) in the EB8T5A.
Required Jumpers
To deliver power to the PES8T5A switch, the following jumpers must be shunted: W4, W10, W23, W24,
and W25. These jumpers were implemented so that the power consumption of the PES8T5A can be
measured.
Reset
The PES8T5A supports two types of reset mechanisms as described in the PCI Express specification:
– Fundamental Reset: This is a system-generated reset that propagates along the PCI Express
tree through a single side-band signal PERST# which is connected to the Root Complex, the
PES8T5A, and the endpoints.
– Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to
another. Hot Reset may be initiated by software. This is further discussed in the 89HPES8T5A
User Manual. The EB8T5A evaluation board provides seamless support for Hot Reset.
Fundamental Reset
There are two types of Fundamental Resets which may occur on the EB8T5A evaluation board:
– Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI
Express Reset (PERSTN) input pin of the PES8T5A.
– Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be
initiated by two methods:
• Pressing a push-button switch (S1) located on EB8T5A board

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 7 July 23, 2009
Notes • The host system board IO Controller Hub asserting PERST# signal, which propagates through
the PCIe upstream edge connector of the EB8T5A. Note that one can bypass the onboard
voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W2.
Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset
(PERSTN) input of the PES8T5A while power is on.
Downstream Reset
The PES8T5A provides a a choice of either a software-controlled reset for each downstream port
through GPIO pins or a fundamental reset through PERST#. Selection is made by jumpers described in
Table 2.6.
Boot Configuration Vector
A boot configuration vector consisting of the signals listed in Table 2.7 is sampled by the PES8T5A
during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential
parameters for switch operation and is set using DIP switches S3, S4, and S5 as defined in Table 2.8.
Port # Jumper Selection
5 W8 [1-2] Software controlled reset through GPIO10
[2-3] Fundamental reset PERST# (default)
4 W9 [1-2] Software controlled reset through GPIO1
[2-3] Fundamental reset PERST# (default)
3 W6 [1-2] Software controlled reset through GPIO9
[2-3] Fundamental reset PERST# (default)
2 W7 [1-2] Software controlled reset through GPIO0
[2-3] Fundamental reset PERST# (default)
Table 2.6 Downstream Reset Selection
Signal Description
CCLKDS Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a com-
mon clock is being used between the downstream device and the downstream port.
Default: 0x1
CCLKUS Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common
clock is being used between the upstream device and the upstream port. Default: 0x1
MSMBSMODE Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 kHz. Default: 0x0
RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES8T5A executes the reset procedure and remains in a reset state with the Master and
Slave SMBuses active. This allows software to read and write registers internal to the
device before normal device operation begins. The device exits the reset state when the
RSTHALT bit is cleared in the P0_SWCTL register through the SMBus.
The value may be overridden by modifying the RSTHALT bit in the P0_SWCTL register.
Default: 0x0
Table 2.7 Boot Configuration Vector Signals (Part 1 of 2)

IDT Installation of the EB8T5A Eval Board
EB8T5A Eval Board Manual 2 - 8 July 23, 2009
Notes
SMBus Interfaces
The System Management Bus (SMBus) is a two-wire interface through which various system compo-
nent chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus
signals in the PCI Express connector is optional and may not be present on the host system. The SMBus
interface consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins.
The PES8T5A contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface.
The slave SMBus interface allows a SMBus Master device (such as the Intel E7520) full access to all soft-
ware-visible registers. The Master SMBus interface provides connection to the external serial EEPROMs
used for initialization and the I/O expander used for hot-plug signals.
SMBus Slave Interface
On the PES8T5A board, the slave SMBus interface is accessible through the PCI Express edge
connector as well as a 4-pin header as described in Table 2.9.
SWMODE[2:0] Switch Mode. These configuration pins determine the PES8T5A switch operating mode.
Default: 0x0
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM-based initialization
0x2 through 0x8 - Reserved
REFCLKM PCI Express Reference Clock Mode Select. This signal selects the frequency of the ref-
erence clock input. Default: 0x0
0x0 - 100 MHz
0x1 - 125 MHz
MSMBADDR[2:0] Master SMBus Address. These pins determine the SMBus address of the serial EEPROM
from which configuration information is loaded. Default: 0x0
APWRDIS# Auxiliary Power Disable. When this pin is active, it disables the device from using auxil-
iary power supply. Default: 0x0
Signal Description Default
S3[4] CCLKDS OFF
S3[5] CCLKUS OFF
S3[6] MSMBSMODE ON
S5[6] RSTHALT ON
S5[1] SWMODE[0] ON
S5[2] SWMODE[1] ON
S5[3] SWMODE[2] ON
S5[5] APWRDIS# ON
S4[5] MSMBADDR[1] ON
S4[6] MSMBADDR[2] ON
S4[7] MSMBADDR[3] ON
S4[8] MSMBADDR[4] ON
Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1)
Signal Description
Table 2.7 Boot Configuration Vector Signals (Part 2 of 2)