Infineon XC800 Series User manual

Application Note, V1.0, Dec. 2006
Microcontrollers
XC800 Family
Power Saving Features -
Achieving Low Power Requirements on
Applications
AP08056

Edition 2006-12
Published by
Infineon Technologies AG
81726 München, Germany
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AP08056
Power Saving Features
Application Note V1.0, 2006-12
XC800 Family
Revision History: V1.0, 2006-12
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AP08056
Power Saving Features
Overview
Application Note 4 V1.0, 2006-12
1Overview
This application note describes the various power saving features in the XC800
architecture. It is intended to provide users of the XC866 and XC886/888 with
information and guidelines on how to apply these features to achieve low power
consumption requirements on applications via a combination of techniques which
include:
• Stopping the CPU clock (Idle Mode)
• Reducing clock speed (slow-down Mode)
• Power down of the entire system (Power-Down Mode)
• Stopping the clocks of individual system components (Peripheral Management)
• Operating on a lower frequency clock mode
In this document, users can find measurements of the current consumed by the XC866
and XC886/888 devices operating in different power modes. There is also a breakdown
of the current consumed by the peripherals at different clock speeds. Hopefully with
these measurements, the users will have a better understanding of how the different
power saving features can affect the power consumption of the devices and therefore
apply the power saving features effectively. However, these results were meant to serve
as a reference only as the measurements will vary from device to device. The power
consumption can be affected by various factors such as the type of instructions used in
the code, program flow, peripheral settings, measuring equipment, power supply,
temperature and frequency of the oscillator etc.
The measurements in this document were taken from four different devices, XC866-
1FR, XC866-4FR, XC886 and XC888. The XC866-4FR results can be used as a
reference for XC866-2FR.
Unless otherwise stated, all the results were measured under the following conditions:
1. Power supply of 5 V
2. Room temperature of approximately 25 oC
3. Port 2 of the devices were set to output to disable the analog driver
4. All the other port pins were configured with internal pull-down enabled
5. Peripherals were not programmed to perform any operations

AP08056
Power Saving Features
Stopping the CPU Clock (Idle Mode)
Application Note 5 V1.0, 2006-12
2 Stopping the CPU Clock (Idle Mode)
The microcontroller can reduce power consumption by stopping the CPU’s clock. This
can be achieved by putting the device in idle mode. In this mode, the oscillator continues
to run, but the CPU is stopped with its clock disabled. Peripherals whose input clocks are
not disabled are still functional.
Note: If the watchdog timer (WDT) is still active when the device goes into idle mode, it
will generate an internal reset when an overflow occurs. It is therefore necessary
to disable the WDT before entering idle mode.
The CPU status is preserved in its entirety; the stack pointer, program counter, program
status word, accumulator, and all other registers maintain their data during idle mode.
The port pins hold the logical state they had at the time the idle mode was activated.
2.1 Entering and Exiting Idle Mode
Idle mode can be entered by setting the bit PCON.IDLE.
PCON |= 0x01;
Table 1 look at the savings in current consumption between active mode and idle mode
of the different devices.
Consider a program that is constantly waiting to service a Timer interrupt. The program
can:
a) wait in an endless loop for the interrupt event to occur, or
b) wait for the interrupt event to occur while the CPU is disabled (idle mode) and then
enable the CPU to service the interrupt routine when an interrupt occurs.
Method (b) will consume less power as indicated in Table 1 and Table 15.
Table 1 Active and Idle mode current measurements
Current (mA)
Products CPU Clock Active 1)
1) Program waits in a continuos loop. i.e. while(1);.
Idle Difference
XC866-1FR 26.80 MHz 15.5 11.87 3.63
XC866-4FR 26.61 MHz 17.84 14.16 3.72
XC886 24.375 MHz 23.46 20.02 3.44
XC888 24.125 MHz 23.22 19.82 3.40

AP08056
Power Saving Features
Stopping the CPU Clock (Idle Mode)
Application Note 6 V1.0, 2006-12
The device in idle mode can be exited to active mode on the occurrence of any of the
two conditions:
1. Hardware reset. The device is put into the hardware reset state.
2. An interrupt has occurred from an enabled interrupt source. The device will service
the interrupt routine and continue its operation from the next instruction after the
instruction that sets the PCON.IDLE bit to 1.
2.2 Ineffective Idle Mode
Idle mode may not necessarily be useful in reducing power consumption. If interrupt
events keep occurring, the device will not be able to stay in idle mode and therefore is
unable to reduce power consumption. In the below example, the peripherals of the
devices were configured to operate as follows:
• Timers 0/1/2/21 in autoreload mode to overflow after 0xFFFF counts
• ADC to perform 10-bit parallel conversion in autoscan mode
• CCU to generate PWM output upon every period match
• UART0 and UART1 to transmit data at 19.2 kBaud upon each UART interrupt
• SSC to transmit at 3 MBaud upon each SSC interrupt
• CORDIC to start computation in circular rotation mode upon each CORDIC interrupt
• MDU to perform unsigned multiplication upon each MDU interrupt
• MCAN to start 8 bytes transmission in loopback mode upon each MCAN interrupt
Note: UART1, CORDIC, MDU and MCAN were configured for XC886/888 only.
The current consumption of the devices is as follow:
Looking at the amount of actives, the devices will be too busy serving the interrupt
routines that they may never be able to stay in idle mode (i.e. turn off the CPU). It can
be observed from Table 2 that idle mode has no effect on the current consumption since
the CPU is always active.
Table 2 Current consumed by devices with peripheral activities
Product CPU Clock Active
Current (mA)
Idle Current
(mA)
Difference 1)
(mA)
1) Negative value indicates that Idle mode current > Active mode current.
XC866-1FR 26.80 MHz 15.88 15.89 - 0.01 mA
XC866-4FR 26.61 MHz 18.52 18.53 - 0.01 mA
XC886 24.375 MHz 25.01 25.07 -0.06 mA
XC888 24.125 MHz 24.82 24.89 - 0.07 mA

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 7 V1.0, 2006-12
3 Reducing Clock Speed (Slow-Down Mode)
The slow-down mode is used to reduce the power consumption by dividing the CPU
clock and the peripherals clock with a programmable factor. The slow-down mode is
activated by setting the bit PMCON0.SD after the programmable factor in the bitfield
CMCON.CLKREL has been selected. The programmable factors may differ for different
XC800 products.
The slow-down mode is terminated by clearing bit PMCON0.SD, which is a protected bit.
It cannot be written directly when the protection scheme is activated. An example below
shows a software example of a XC866 device entering slow-down mode with system
clock reduced by a factor of 32.
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
CMCON &= 0xF0; //Clear CLKREL
CMCON |= 0x06; //Select clock divider = fsys/32
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 |= 0x08; //Set SD to enter slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Similarly, to exit the slow-down mode,
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 &= 0xF7; //Clear SD to exit slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Note: Flash programming and erasing operations are not guaranteed in slow-
down mode. Users must exit this mode before carrying out such operations.

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 8 V1.0, 2006-12
3.1 Combining slow-down Mode with Idle Mode
The slow-down mode can be combined with the idle mode (slow-down-idle mode). This
can be done by performing the following sequence:
1. Select the slow-down frequency in the bitfield CMCON.CLKREL.
2. Enter the slow-down mode by setting the bit PMCON0.SD.
3. Activate idle mode by setting the PCON.IDLE mode.
The slow-down-idle mode can be terminated by first exiting from idle mode and then
followed by clearing the bit PMCON0.SD. It will also be terminated by a hardware reset.
3.2 Slow-Down Mode vs. Slow-Down-Idle Mode Current
Measurements
This section illustrates the current measurements taken from XC866-1FR, XC866-4FR,
XC886 and XC888, and shows the effect of the current consumption by the devices in
slow-down mode and slow-down-idle mode. The measurements are tabulated in
Table 3, Table 4, Table 5 and Table 6 respectively.
From the tables, it can be observed that the amount of current that can be saved in slow-
down mode reduces with the peripheral frequency. This can be seen in the graphical
representations of each table. The peripherals require less power to operate when the
peripheral clock is reduced in slow-down mode. At low frequencies, the current drawn by
the peripherals become relatively constant and therefore less current can be saved when
the peripheral clock speed is further reduced. In any case, the devices draw the least
current at the lowest possible frequency.
The slow-down-idle mode does not necessary draw the least current at the lowest
possible frequency. This can be observed in Table 3, Table 4, Table 16 (XC866) and
Table 17 (XC888). The effectiveness of the slow-down-idle mode will depend on factors
such as peripheral activities and the operating frequency. It is therefore necessary to
perform measurements manually to determine whether slow-down-idle mode is more
effective than slow-down mode in reducing current consumption.

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 9 V1.0, 2006-12
Figure 1 Graphical representation of the X and Y series in Table 3
Table 3 Current comparison between slow-down mode and slow-down-idle
mode of a XC866-1FR device
fSYS = 80.4 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 3 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference 2)
X - Y
2) Negative value indicates that slow-down-idle mode current > slow-down mode current.
26.800 0000B15.50 11.87 3.63
6.700 0010B7.12 6.41 0.71
3.350 0011B5.70 5.47 0.23
1.675 0100B4.99 5.01 0.02
0.419 0110B4.45 4.66 -0.21
0.209 0111B4.36 4.36 -0.00
0.105 1000B4.32 4.57 -0.25
0.052 1001B4.30 4.56 -0.26
0.026 1010B4.28 4.55 -0.27
0.013 1011B4.28 4.54 -0.26
0
2
4
6
8
10
12
14
16
18
26.800 6.700 3.350 1.675 0.419 0.209 0.105 0.052 0.026 0.013
Peripheral Clock Frequency (M Hz) - XC846
Current (mA)
X Y

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 10 V1.0, 2006-12
Figure 2 Graphical representation of the X and Y series in Table 4
Table 4 Current comparison between slow-down mode and slow-down-idle
mode of a XC866-4FR device
fSYS = 79.84 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 3 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference 2)
X - Y
2) Negative value indicates that slow-down-idle mode current > slow-down mode current.
26.613 0000B17.84 14.16 3.68
6.653 0010B8.62 7.70 0.92
1.663 0100B6.19 6.02 0.17
0.832 0101B5.78 5.75 0.03
0.416 0110B5.58 5.60 -0.02
0.208 0111B5.48 5.53 -0.05
0.104 1000B5.43 5.50 -0.07
0.052 1001B5.40 5.48 -0.08
0.026 1010B5.39 5.47 -0.08
0.013 1011B5.38 5.47 -0.09
0
2
4
6
8
10
12
14
16
18
20
26.613 6.653 1.663 0.832 0.416 0.208 0.104 0.052 0.026 0.013
Peripheral Clock Frequency (MHz) - XC866
Current (mA)
X Y