Infineon XC800 Series User manual

Application Note, V1.0, Dec. 2006
Microcontrollers
XC800 Family
Power Saving Features -
Achieving Low Power Requirements on
Applications
AP08056

Edition 2006-12
Published by
Infineon Technologies AG
81726 München, Germany
©Infineon Technologies AG 2006.
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AP08056
Power Saving Features
Application Note V1.0, 2006-12
XC800 Family
Revision History: V1.0, 2006-12
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AP08056
Power Saving Features
Overview
Application Note 4 V1.0, 2006-12
1Overview
This application note describes the various power saving features in the XC800
architecture. It is intended to provide users of the XC866 and XC886/888 with
information and guidelines on how to apply these features to achieve low power
consumption requirements on applications via a combination of techniques which
include:
• Stopping the CPU clock (Idle Mode)
• Reducing clock speed (slow-down Mode)
• Power down of the entire system (Power-Down Mode)
• Stopping the clocks of individual system components (Peripheral Management)
• Operating on a lower frequency clock mode
In this document, users can find measurements of the current consumed by the XC866
and XC886/888 devices operating in different power modes. There is also a breakdown
of the current consumed by the peripherals at different clock speeds. Hopefully with
these measurements, the users will have a better understanding of how the different
power saving features can affect the power consumption of the devices and therefore
apply the power saving features effectively. However, these results were meant to serve
as a reference only as the measurements will vary from device to device. The power
consumption can be affected by various factors such as the type of instructions used in
the code, program flow, peripheral settings, measuring equipment, power supply,
temperature and frequency of the oscillator etc.
The measurements in this document were taken from four different devices, XC866-
1FR, XC866-4FR, XC886 and XC888. The XC866-4FR results can be used as a
reference for XC866-2FR.
Unless otherwise stated, all the results were measured under the following conditions:
1. Power supply of 5 V
2. Room temperature of approximately 25 oC
3. Port 2 of the devices were set to output to disable the analog driver
4. All the other port pins were configured with internal pull-down enabled
5. Peripherals were not programmed to perform any operations

AP08056
Power Saving Features
Stopping the CPU Clock (Idle Mode)
Application Note 5 V1.0, 2006-12
2 Stopping the CPU Clock (Idle Mode)
The microcontroller can reduce power consumption by stopping the CPU’s clock. This
can be achieved by putting the device in idle mode. In this mode, the oscillator continues
to run, but the CPU is stopped with its clock disabled. Peripherals whose input clocks are
not disabled are still functional.
Note: If the watchdog timer (WDT) is still active when the device goes into idle mode, it
will generate an internal reset when an overflow occurs. It is therefore necessary
to disable the WDT before entering idle mode.
The CPU status is preserved in its entirety; the stack pointer, program counter, program
status word, accumulator, and all other registers maintain their data during idle mode.
The port pins hold the logical state they had at the time the idle mode was activated.
2.1 Entering and Exiting Idle Mode
Idle mode can be entered by setting the bit PCON.IDLE.
PCON |= 0x01;
Table 1 look at the savings in current consumption between active mode and idle mode
of the different devices.
Consider a program that is constantly waiting to service a Timer interrupt. The program
can:
a) wait in an endless loop for the interrupt event to occur, or
b) wait for the interrupt event to occur while the CPU is disabled (idle mode) and then
enable the CPU to service the interrupt routine when an interrupt occurs.
Method (b) will consume less power as indicated in Table 1 and Table 15.
Table 1 Active and Idle mode current measurements
Current (mA)
Products CPU Clock Active 1)
1) Program waits in a continuos loop. i.e. while(1);.
Idle Difference
XC866-1FR 26.80 MHz 15.5 11.87 3.63
XC866-4FR 26.61 MHz 17.84 14.16 3.72
XC886 24.375 MHz 23.46 20.02 3.44
XC888 24.125 MHz 23.22 19.82 3.40

AP08056
Power Saving Features
Stopping the CPU Clock (Idle Mode)
Application Note 6 V1.0, 2006-12
The device in idle mode can be exited to active mode on the occurrence of any of the
two conditions:
1. Hardware reset. The device is put into the hardware reset state.
2. An interrupt has occurred from an enabled interrupt source. The device will service
the interrupt routine and continue its operation from the next instruction after the
instruction that sets the PCON.IDLE bit to 1.
2.2 Ineffective Idle Mode
Idle mode may not necessarily be useful in reducing power consumption. If interrupt
events keep occurring, the device will not be able to stay in idle mode and therefore is
unable to reduce power consumption. In the below example, the peripherals of the
devices were configured to operate as follows:
• Timers 0/1/2/21 in autoreload mode to overflow after 0xFFFF counts
• ADC to perform 10-bit parallel conversion in autoscan mode
• CCU to generate PWM output upon every period match
• UART0 and UART1 to transmit data at 19.2 kBaud upon each UART interrupt
• SSC to transmit at 3 MBaud upon each SSC interrupt
• CORDIC to start computation in circular rotation mode upon each CORDIC interrupt
• MDU to perform unsigned multiplication upon each MDU interrupt
• MCAN to start 8 bytes transmission in loopback mode upon each MCAN interrupt
Note: UART1, CORDIC, MDU and MCAN were configured for XC886/888 only.
The current consumption of the devices is as follow:
Looking at the amount of actives, the devices will be too busy serving the interrupt
routines that they may never be able to stay in idle mode (i.e. turn off the CPU). It can
be observed from Table 2 that idle mode has no effect on the current consumption since
the CPU is always active.
Table 2 Current consumed by devices with peripheral activities
Product CPU Clock Active
Current (mA)
Idle Current
(mA)
Difference 1)
(mA)
1) Negative value indicates that Idle mode current > Active mode current.
XC866-1FR 26.80 MHz 15.88 15.89 - 0.01 mA
XC866-4FR 26.61 MHz 18.52 18.53 - 0.01 mA
XC886 24.375 MHz 25.01 25.07 -0.06 mA
XC888 24.125 MHz 24.82 24.89 - 0.07 mA

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 7 V1.0, 2006-12
3 Reducing Clock Speed (Slow-Down Mode)
The slow-down mode is used to reduce the power consumption by dividing the CPU
clock and the peripherals clock with a programmable factor. The slow-down mode is
activated by setting the bit PMCON0.SD after the programmable factor in the bitfield
CMCON.CLKREL has been selected. The programmable factors may differ for different
XC800 products.
The slow-down mode is terminated by clearing bit PMCON0.SD, which is a protected bit.
It cannot be written directly when the protection scheme is activated. An example below
shows a software example of a XC866 device entering slow-down mode with system
clock reduced by a factor of 32.
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
CMCON &= 0xF0; //Clear CLKREL
CMCON |= 0x06; //Select clock divider = fsys/32
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 |= 0x08; //Set SD to enter slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Similarly, to exit the slow-down mode,
SYSCON0 &= 0xFE;//Access standard SFR region (RMAP = 0)
SCU_PAGE = 0x01;//Open SCU page 1
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 &= 0xF7; //Clear SD to exit slow-down mode
PASSWD = 0xA8; //Close access to writing of all protected bits
Note: Flash programming and erasing operations are not guaranteed in slow-
down mode. Users must exit this mode before carrying out such operations.

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 8 V1.0, 2006-12
3.1 Combining slow-down Mode with Idle Mode
The slow-down mode can be combined with the idle mode (slow-down-idle mode). This
can be done by performing the following sequence:
1. Select the slow-down frequency in the bitfield CMCON.CLKREL.
2. Enter the slow-down mode by setting the bit PMCON0.SD.
3. Activate idle mode by setting the PCON.IDLE mode.
The slow-down-idle mode can be terminated by first exiting from idle mode and then
followed by clearing the bit PMCON0.SD. It will also be terminated by a hardware reset.
3.2 Slow-Down Mode vs. Slow-Down-Idle Mode Current
Measurements
This section illustrates the current measurements taken from XC866-1FR, XC866-4FR,
XC886 and XC888, and shows the effect of the current consumption by the devices in
slow-down mode and slow-down-idle mode. The measurements are tabulated in
Table 3, Table 4, Table 5 and Table 6 respectively.
From the tables, it can be observed that the amount of current that can be saved in slow-
down mode reduces with the peripheral frequency. This can be seen in the graphical
representations of each table. The peripherals require less power to operate when the
peripheral clock is reduced in slow-down mode. At low frequencies, the current drawn by
the peripherals become relatively constant and therefore less current can be saved when
the peripheral clock speed is further reduced. In any case, the devices draw the least
current at the lowest possible frequency.
The slow-down-idle mode does not necessary draw the least current at the lowest
possible frequency. This can be observed in Table 3, Table 4, Table 16 (XC866) and
Table 17 (XC888). The effectiveness of the slow-down-idle mode will depend on factors
such as peripheral activities and the operating frequency. It is therefore necessary to
perform measurements manually to determine whether slow-down-idle mode is more
effective than slow-down mode in reducing current consumption.

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 9 V1.0, 2006-12
Figure 1 Graphical representation of the X and Y series in Table 3
Table 3 Current comparison between slow-down mode and slow-down-idle
mode of a XC866-1FR device
fSYS = 80.4 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 3 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference 2)
X - Y
2) Negative value indicates that slow-down-idle mode current > slow-down mode current.
26.800 0000B15.50 11.87 3.63
6.700 0010B7.12 6.41 0.71
3.350 0011B5.70 5.47 0.23
1.675 0100B4.99 5.01 0.02
0.419 0110B4.45 4.66 -0.21
0.209 0111B4.36 4.36 -0.00
0.105 1000B4.32 4.57 -0.25
0.052 1001B4.30 4.56 -0.26
0.026 1010B4.28 4.55 -0.27
0.013 1011B4.28 4.54 -0.26
0
2
4
6
8
10
12
14
16
18
26.800 6.700 3.350 1.675 0.419 0.209 0.105 0.052 0.026 0.013
Peripheral Clock Frequency (M Hz) - XC846
Current (mA)
X Y

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 10 V1.0, 2006-12
Figure 2 Graphical representation of the X and Y series in Table 4
Table 4 Current comparison between slow-down mode and slow-down-idle
mode of a XC866-4FR device
fSYS = 79.84 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 3 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference 2)
X - Y
2) Negative value indicates that slow-down-idle mode current > slow-down mode current.
26.613 0000B17.84 14.16 3.68
6.653 0010B8.62 7.70 0.92
1.663 0100B6.19 6.02 0.17
0.832 0101B5.78 5.75 0.03
0.416 0110B5.58 5.60 -0.02
0.208 0111B5.48 5.53 -0.05
0.104 1000B5.43 5.50 -0.07
0.052 1001B5.40 5.48 -0.08
0.026 1010B5.39 5.47 -0.08
0.013 1011B5.38 5.47 -0.09
0
2
4
6
8
10
12
14
16
18
20
26.613 6.653 1.663 0.832 0.416 0.208 0.104 0.052 0.026 0.013
Peripheral Clock Frequency (MHz) - XC866
Current (mA)
X Y

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 11 V1.0, 2006-12
Figure 3 Graphical representation of the X and Y series in Table 5
Table 5 Current comparison between slow-down mode and slow-down-idle
mode of a XC886 device
fSYS = 97.50 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 2 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference
X - Y
24.375 0000B23.46 20.02 3.44
12.188 0010B14.87 13.05 1.82
6.0941 0100B10.43 9.45 0.98
3.047 0110B8.19 7.65 0.54
1.523 1000B7.07 6.74 0.33
0.762 1010B6.50 6.29 0.21
0.381 1100B6.22 6.06 0.16
0.190 1110B6.08 5.95 0.13
0.127 1111B6.03 5.91 0.12
0
5
10
15
20
25
24.375 12.188 6.094 3.047 1.523 0.762 0.381 0.190 0.127
Peripheral Clock Frequency (MHz) - XC886
Current (mA)
X Y

AP08056
Power Saving Features
Reducing Clock Speed (Slow-Down Mode)
Application Note 12 V1.0, 2006-12
Figure 4 Graphical representation of the X and Y series in Table 6
Table 6 Current comparison between slow-down mode and slow-down-idle
mode of a XC888 device
fSYS = 96.50 MHz Current (mA)
Peripheral 1)
Frequency (MHz)
1) Peripheral frequency = fSYS/CLKREL/Fixed divider of 2 (refer to user’s manual on Clock System)
CLKREL Slow-Down
(X)
Slow-Down-
Idle (Y)
Difference
X - Y
24.125 0000B23.22 19.82 3.40
12.063 0010B14.78 12.91 1.87
6.031 0100B10.33 9.36 0.97
3.016 0110B8.12 7.58 0.54
1.508 1000B7.01 6.68 0.33
0.754 1010B6.45 6.24 0.21
0.377 1100B6.17 6.01 0.16
0.188 1110B6.03 5.90 0.13
0.126 1111B5.98 5.86 0.12
0
5
10
15
20
25
24.125 12.063 6.031 3.016 1.508 0.754 0.377 0.188 0.126
Peripheral Clock Frequency (MHz) - XC888
Current (mA)
X Y

AP08056
Power Saving Features
Power Down of the Entire System (Power-Down Mode)
Application Note 13 V1.0, 2006-12
4 Power Down of the Entire System (Power-Down
Mode)
Power-down of the entire system can be achieved by setting the device in power-down
mode. In this mode, all functions of the microcontroller are stopped and only the contents
of the FLASH, on-chip RAM, XRAM and the SFRs are maintained. The port pins hold the
logical state they had when the power-down mode was activated. For the digital ports,
the user should ensure that the ports are not left floating. Floating input port pins should
enable pull-down or set as output. Output pins that are pulled-up should be set to high.
For the analog Port 2, the user should disable the input driver of the port by setting the
port direction to output.
In power-down mode, the clock is turned off. Hence, it cannot be awakened by an
interrupt or by the WDT. It is awakened only when it receives an external wake-up signal
or reset signal.
4.1 Entering Power-Down Mode
Software requests power-down mode by setting the bit PMCON0.PD (protected bit) to 1.
Two NOP instructions must be inserted after the bit PMCON0.PD is set to 1. The device
will not enter power-down mode immediately after executing the instruction to set
PMCON0.PD and therefore the two NOPs is to ensure the first instruction (after two NOP
instructions) is executed correctly after wake-up from power-down mode.
If the external wake-up from power-down is used, software must select the EXINT0 pin,
the RXD pin, or either of these two pins as the wake-up source by selecting the WS bit
of the PMCON0 register. Exit from power-down mode can be achieved when a falling
edge trigger is detected at the selected source(s). Bit MODPISEL.URRIS is used to
select one of the two RXD inputs and bit MODPISEL.EXINT0IS is used to select one of
the two EXINT0 inputs. The wake-up with reset or without reset is selected by bit
PMCON0.WKSEL. The wake-up source and wake-up type must be selected before the
system enters the power-down mode.
In order for the program to resume its operation from where it was stopped after the
reset, it is necessary to save the contents of the relevant registers to the stack including
the current stack pointer. The example below shows how the power-down mode can be
entered correctly with the port status stored to stack.
//... SP was initialized as 0x41
PORT_PAGE = 0x00;//Open port page 0 to access Px_DATA
_push_(P3_DATA);//Save port 3, current SP = 0x42.
//_push_() function is defined in intrins.h

AP08056
Power Saving Features
Power Down of the Entire System (Power-Down Mode)
Application Note 14 V1.0, 2006-12
STACKSP = SP; //Save current stack pointer at an absolute memory
//location. e.g. unsigned char idata STACKSP _at_
//0xe0; iram location 0xe0 = 0x42
SCU_PAGE = 0x01;//Open SCU page 1 to access PMCON0 and PASSWD
PASSWD = 0x98; //Open access to writing of all protected bits
PMCON0 |= 0x17; //Enable power-down with wake up source RXD or
//EXINT0 selected and select wake-up with reset
_nop_(); //2 NOPs necessary for proper execution of
_nop_(); //code upon wakeup. Function is defined in
//intrins.h.
Note: Some IRAM locations will be corrupted after a reset. The stack and the constant
variable location must avoid these locations. Please refer to the respective
product’s Errata Sheet for the detailed locations.
Note: START_XC.A51 will clear IRAM locations ranging from 0 to the number defined in
the symbol IDATALEN. It is therefore necessary to redefine the data assigned to
this symbol to avoid destroying the stack and the constant variable data.
4.2 Exiting Power-Down Mode
Power-down mode can be exited in two ways:
1. Hardware reset. The device is put into the hardware reset state.
2. The EXINT0 pin, the RXD pin or either of these two pins detects a falling edge. The
wake-up source(s) must be selected prior to entering power-down mode.
When a wake up source is selected, the device will wake-up from power-down mode
upon detecting a falling edge trigger at that source. In power-down mode, EXINT0
pin/RXD pin must be held at high level. Power-down mode is exited when EXINT0
pin/RXD pin goes low for at least 100 ns.
The device can wake-up with or without reset depending on the setting of the
PMCON0.WKSEL bit. If the WKSEL bit was set to 1 prior to entering power-down mode,
the system will execute a reset sequence similar to the power-on reset sequence.
Therefore, all port pins and SFRs are put into their reset state and will remain in this state
until they are affected by program execution. The only exception is that hardware will set
the wake-up indication bit PMCON0.WKRS to indicate that the device is woken up from
power-down reset.

AP08056
Power Saving Features
Power Down of the Entire System (Power-Down Mode)
Application Note 15 V1.0, 2006-12
If bit WKSEL was cleared to 0 before entering power-down mode, a fast wake-up
sequence is used. The port pins continue to hold their state which was valid during
power-down mode until they are affected by program execution.
The example below shows how the previous example can restore the port 3 status after
exiting the power-down mode with reset.
//... after initialization
SCU_PAGE = 0x01;//Open SCU page 1 to access PMCON0
if (PMCON0 & 0x20)//Check PMCON0.WKRS for wakeup indication
{
SP = STACKSP;//Restore stack pointer, SP = 0x42
PORT_PAGE = 0x00; //Open port page 0 to access Px_DATA
_pop_(P3_DATA); //Restore P3 from stack
}
//... continue...
Table 7 illustrates the timing for a device to wake-up from power-down mode to active
mode for both wake-up with/without reset.
In power-down mode, the typical amount of current drawn by the devices will be
approximately 1 µA at 25 oC.
Table 7 Wakeup timing from power-down mode
XC866-1FR XC866-4FR and
XC886/888
Reset Sequence WKSEL = 1 WKSEL = 0 WKSEL = 1 WKSEL = 0
EVR is stable 150 µs (Typical) 150 µs (Typical)
PLL is locked 200 µs (Maximum) 200 µs (Maximum)
Flash ready to read
state
0160 µs 0160 µs
BROM execution1)
1) Timing is based on the system frequency of the devices. XC866 operates at 80 MHz while XC886/888
operates at 96 MHz.
0215 µs
(Typical)
0250 µs
(Typical)
Total wake-up time 350 µs 725 µs 350 µs 760 µs

AP08056
Power Saving Features
Stopping the Clocks of Individual System Components
Application Note 16 V1.0, 2006-12
5 Stopping the Clocks of Individual System
Components (Peripheral Management)
Peripherals which are not required for a particular functionality can be disabled by
programming the assigned register bits in PMCON1 and PMCON2 which would gate off
clock inputs. This would further reduce overall power consumption of the device.
Table 8, Table 9 and Table 10 shows the amount of current that can be saved when
each/all of the peripheral module(s) are disabled by a XC866-1FR, XC866-4FR and a
XC886 device at different peripheral clock frequency (fPCLK). It can be observed that
when the peripheral clock is reduced, the power consumed by the peripherals will also
reduce, which means that less current can be saved.
Software example to disable all peripherals on a XC886/888 device:
SCU_PAGE = 0x01; //Open SCU page 1 to access PMCON1
PMCON1 |= 0x7F; //Disable ADC, CCU, SSC, T2, MDU, CAN and
//CORDIC
SCU_PAGE = 0x03; //Open SCU page 3 to access PMCON2
PMCON2 |= 0x03; //Disable T21 and UART1
For XC866, only ADC, CCU, SSC and T2 can be disabled by setting the corresponding
bits in PMCON1.
Table 8 Current consumption by the peripherals of a XC866-1FR device at
different peripheral clock (PCLK) frequencies
Current (mA)
Peripheral Frequency
(MHz)
26.800 6.700 0.838 0.209 0.013
CLKREL 0000B0010B0101B0111B1011B
ADC 0.80 0.20 0.03 0.01 01)
1) < 10 µA
CCU 1.45 0.36 0.05 0.02 0
SSC 0.51 0.12 0.02 0.01 0
T2 0.16 0.04 0.01 0 0
All 2.95 0.73 0.10 0.03 0

AP08056
Power Saving Features
Stopping the Clocks of Individual System Components
Application Note 17 V1.0, 2006-12
Table 9 Current consumption by the peripherals of a XC866-4FR device at
different peripheral clock (PCLK) frequencies
Current (mA)
Peripheral Frequency
(MHz)
26.613 6.653 0.832 0.208 0.013
CLKREL 0000B0010B0101B0111B1011B
ADC 0.95 0.26 0.04 0.01 01)
CCU 1.44 0.39 0.05 0.02 0
SSC 0.37 0.10 0.02 0.01 0
T2 0.17 0.05 0.01 0 0
All 3.01 0.80 0.11 0.03 0
1) < 10 µA
Table 10 Current consumption by the peripherals of a XC888 device at
different peripheral clock (PCLK) frequencies
Current (mA)
Peripheral Frequency
(MHz)
24.125 12.063 3.016 0.754 0.126
CLKREL 0000B0010B0110B1010B1111B
ADC 0.65 0.35 0.09 0.03 01)
CCU 1.14 0.60 0.15 0.04 0.01
SSC 0.38 0.19 0.05 0.01 0
T2 0.13 0.07 0.02 0.01 0
T21 0.13 0.07 0.02 0.01 0
CAN 4.81 2.51 0.64 0.16 0.03
CORDIC 0.60 0.31 0.08 0.02 0
MDU 0.24 0.14 0.04 0.01 0
UART1 0.25 0.13 0.04 0.01 0
All 8.54 4.42 1.12 0.28 0.04
1) < 10 µA

AP08056
Power Saving Features
Operating on a Lower Frequency Clock Mode
Application Note 18 V1.0, 2006-12
6 Operating on a Lower Frequency Clock Mode
The normal system clock runs in PLL Mode. The system frequency (fSYS) is defined as:
The N factor is selected by the bitfield PLL_CON.NDIV. The P factor is fixed to 1. The K
factor is fixed at 2 for XC866. It can be selected by the bit CMCON.KDIV (protected bit)
for XC886/888. The internal oscillator frequency (fOSC) for XC866 is 10 MHz. The internal
oscillator frequency for XC886/888 is 9.6 MHz.
This system frequency is further divided to derive the CPU clock, peripheral clock and
flash clock. By selecting a different clock mode, the system frequency will be changed
and thus affecting all the other clocks of the entire system. The PLL Base Mode and the
Prescaler Mode are two of the other clock modes that can be used to derive the system
frequency. They will be discussed in the following sections.
Note: Flash programming and erasing operations cannot be carried out in PLL
base and prescaler mode. Such operations can only be carried out correctly
when the system clock is running in PLL mode.
fSYS
N
PK⋅
------------fOSC
⋅=

AP08056
Power Saving Features
Operating on a Lower Frequency Clock Mode
Application Note 19 V1.0, 2006-12
6.1 Device Clock in PLL Base Mode
In the PLL base mode, the oscillator is disconnected from the PLL and the system
frequency is derived from the VCO base (free running) frequency clock divided by the K
factor:
The ranges of the VCO base frequency is shown in Table 11.
The VCO base frequency of different devices will range between 10 MHz to 80 MHz
depending on the VCOSEL setting. Users will need to manually check the system
frequency of each device by outputting the device’s system clock at the CLKOUT pin.
The code example to output the system clock is as follows:
SCU_PAGE = 0x01; //open SCU page 1 to access COCON
COCON = 0x37; //select clock output frequency/10
PORT_PAGE = 0x02; //open port page 2 to access Px_ALTSELx
P0_ALTSEL0 = 0x01; //select clock out function for P0.0
P0_ALTSEL1 = 0x00;
PORT_PAGE = 0x00; //open port page 0 to access Px_DIR
P0_DIR = 0x01; //set P0.0 as output port
At the output of P0.0, the clock output frequency is half of the frequency that is chosen
by the bitfield COCON.COREL. In the above example, the system clock output at P0.0
has been divided by a factor of 10 based on the setting of the bitfield COCON.COREL.
The system frequency can hence be obtained by multiplying the measured frequency by
a factor of 20.
Users must take note that the VCO base frequency that was determined could vary
approximately up to +/- 10% depending on the stability of the power supply to the PLL
(i.e. power supply from EVR) and the temperature.
Table 11 VCO base (fVCObase) and system frequency (fSYS) ranges
Device VCOSEL fVCObase
Range (MHz)
fSYS Range
when K = 1
(MHz)
fSYS Range
when K = 2
(MHz)
XC866 010 - 80 -5 - 40
120 - 80 -10 - 40
XC886/888 020 - 80 20 - 80 10 - 40
110 - 80 10 - 80 5 - 40
fSYS
1
K
----fVCObase
⋅=

AP08056
Power Saving Features
Operating on a Lower Frequency Clock Mode
Application Note 20 V1.0, 2006-12
Table 12 are some results showing the current consumption by a XC866-1FR device, a
XC866-4FR device and a XC886 device operating in PLL base mode.
6.1.1 Software Example for PLL Base Mode
In order to disconnect the oscillator, the VCO bypass mode must be selected first by
setting the bit PLL_CON.VCOBYP. This is to prevent the system from detecting a PLL
loss of lock condition which sets the NMICON.NMIPLL bit. The internal oscillator can be
powered down in PLL base mode to save power by setting bit OSC_CON.OSCPD.
The following example shows how the PLL base mode is selected.
SCU_PAGE = 0x01;//Open SCU page 1
PLL_CON |= 0x08;//Select VCO Bypass Mode. This step is to
//prevent PLL loss of lock bit from being set
PLL_CON |= 0x04;//Disconnect the oscillator
OSC_CON |= 0x10;//Power-down the oscillator
//... device is running in PLL Base Mode
The next example will show how to restore the clock in PLL mode from PLL base mode.
//... PLL_CON.VCOBYP = 1
SCU_PAGE = 0x01;//Open SCU page 1
OSC_CON &= 0xEF;//Power up the oscillator
OSC_CON |= 0x02;//Reset and restart oscillator detection logic
while(!(OSC_CON & 0x01));//Wait for oscillator to run
PLL_CON &= 0xFB;//Connect oscillator to PLL
PLL_CON |= 0x02;//Restart PLL lock detection
while(!(PLL_CON & 0x01));//Wait for PLL lock bit to set
Table 12 Current consumption in PLL base mode
XC866-1FR XC866-4FR XC886
VCOSEL 0 1 0 1 0 1
fVCObase (MHz) 22.48 38.94 22.00 37.70 36.22 21.24
fSYS (MHz) with K = 2 11.24 19.47 11.00 18.85 18.11 10.62
PLL base mode
current
2.74 mA 4.25 mA 3.07 mA 4.75 mA 5.12 mA 3.37 mA
PLL base mode 1)
current with slow-
down mode enabled
1) CLKREL = 1011Bfor XC886 and CLKREL = 1111Bfor XC886
1.01 mA 1.35 mA 1.26 mA 1.65 mA 1.60 mA 1.23 mA