Intel D5005 User manual

Intel Acceleration Stack Quick Start
Guide
Intel FPGA Programmable Acceleration Card
D5005
Updated for Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs: 2.0
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Contents
1. Introduction to the Intel FPGA Programmable Acceleration Card D5005 ....................... 3
2. System Requirements and Release Installation.............................................................. 5
2.1. Unpacking the Intel FPGA PAC................................................................................. 5
2.2. Precautions for Hardware Installation....................................................................... 6
2.3. Hardware Installation ............................................................................................ 6
2.4. Setting Up the Host Machine Software......................................................................7
2.4.1. Installing Red Hat Enterprise Linux version 7.6 ............................................. 7
2.4.2. Installing the Intel Acceleration Stack Runtime Package on the Host Machine.....8
2.4.3. Installing the Intel Acceleration Stack Development Package on the Host
Machine................................................................................................... 9
2.4.4. Verifying the Installation.............................................................................9
3. Installing the OPAE Software Package.......................................................................... 11
3.1. Unpacking and Installing the Intel FPGA Driver and the OPAE Software
Development Kit (SDK)......................................................................................11
4. Identify the FPGA Interface Manager (FIM) and BMC Firmware Version....................... 13
4.1. Updating the FIM and BMC using the fpgaflash Tool.............................................. 14
5. Running FPGA Diagnostics ........................................................................................... 15
6. Running the OPAE in a Non-Virtualized Environment ................................................... 17
6.1. Loading the AFU Image into the FPGA.....................................................................17
6.2. Running the Hello FPGA Example........................................................................... 18
7. Running the OPAE in a Virtualized Environment ...........................................................20
7.1. Updating Settings Required for VFs........................................................................ 21
7.2. Configuring the VF Port on the Host........................................................................21
7.3. Running the Hello FPGA Example on Virtual Machine.................................................22
7.4. Disconnecting the VF from the VM and Reconnecting to the PF................................... 23
8. Document Revision History for Intel Acceleration Stack Quick Start Guide................... 24
A. Handling Graceful Thermal Shutdown...........................................................................25
B. Troubleshooting Frequently Asked Questions (FAQ)..................................................... 28
B.1. Why do I see a "No Suitable slots found" message when running fpgaconf on my
AFU image?......................................................................................................28
B.2. How do I flash the FIM or program the AFU in a multicard system?.............................28
B.3. Which environment variables are required?............................................................. 29
B.4. What actions do I take if I see the error message "Error enumerating resources:
no driver available"?.......................................................................................... 29
Contents
Intel Acceleration Stack Quick Start Guide: Intel FPGA Programmable
Acceleration Card D5005 Send Feedback
2

1. Introduction to the Intel FPGA Programmable
Acceleration Card D5005
This guide provides a brief introduction to the Intel® FPGA PAC D5005. This guide
provides the instructions for the following procedures:
• Installing the Open Programmable Acceleration Engine (OPAE) on the host Intel
Xeon® Processor to manage and access the Intel FPGA PAC.
— Configuring and flashing the FPGA image and Board Management Controller
images.
—Running the example hello_afu in a non-virtualized environment.
The Intel FPGA PAC D5005 is a collection of software, firmware, and tools that allows
both software and RTL developers to take advantage of the power of Intel FPGAs. By
offloading computationally intensive tasks to the FPGA, the acceleration platform frees
the Intel Xeon processor for other critical processing tasks.
Figure 1. Overview of the Intel FPGA PAC Platform Hardware and Software
Libraries
Application
OPAE Running on Intel Host
PCIe Accelerator Card
Xeon Processor
Intel FPGA
User Developed
PCIe Driver
Provided by Intel
FPGA Interface
Manager (FIM)
Provided by Intel
User, Intel, and
Third Party
Open Programmable
Acceleration Engine (OPAE)
Provided by Intel
Accelerator Function (AF)
User, Intel, and Third-Party
IP Plugs into AFU Slot
FIM
AFU
Drivers APIs
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Related Information
•Developing AFUs with the OPAE SDK
•Intel FPGA SDK for OpenCL Pro Edition Programming Guide
1. Introduction to the Intel FPGA Programmable Acceleration Card D5005
UG-20202 | 2019.08.05
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2. System Requirements and Release Installation
Note: Ensure that your system meets the following requirements before you proceed to
install the Intel FPGA PAC D5005. The Intel FPGA PAC will not function properly if your
system does not meet these requirements.
Table 1. System Requirements for the Intel FPGA PAC D5005
Hardware and Software Components Description
Main board PCI Express* 3.0 compliant motherboard with at least one
dual-width x16 PCIe* slot available for card installation
Server Supported Server List
System power supply Auxiliary Power (12V)(1)
Operating system Red Hat* Enterprise Linux* (RHEL) version 7.6 Kernel
3.10.0-957
Internet connection Required to install the OPAE driver and receive updates
2.1. Unpacking the Intel FPGA PAC
Box Contents
• Intel FPGA PAC D5005
• Extension mounting bracket
• Mounting screws
Intel FPGA PAC Features
• PCIe 2x4-pin auxiliary power connector
• PCIe card edge connector
• Two quad small form factor pluggable (QSFP) interfaces
• Micro-USB
• Card extender mounting bracket
• Card extender mounting screws
(1) Refer to the Supported Server List for power cable details.
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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Figure 2. Intel FPGA PAC D5005
QSFP Ports
I/O Panel with LEDs PCIe Edge Connector
Card Retention Hook Micro-USB
2x4-pin PCIe
Power Connector
I/O Panel Mounting Bracket
2.2. Precautions for Hardware Installation
You must open the server chassis to install the Intel FPGA PAC. Follow all safety
precautions and the electrostatic discharge (ESD) guidelines provided to avoid
damaging the server or the Intel FPGA PAC.
Warning: To avoid electric shock, power down your server and unplug it from the power outlet
before opening the server chassis.
ESD Guidelines
Electronics components on the Intel FPGA PAC and server are sensitive to ESD. To
avoid damaging the Intel FPGA PAC and server, follow these ESD prevention
guidelines:
• Wear a grounded ESD strap during the Intel FPGA PAC installation.
• Leave the Intel FPGA PAC in its ESD-safe packaging until you are ready to install
the card.
• During installation, handle the Intel FPGA PAC only by the edge of the board.
• Never touch any exposed circuitry, edge connectors, or printed circuits on the Intel
FPGA PAC or server.
• Do not put the Intel FPGA PAC on any metal surface during installation.
• If you must put the Intel FPGA PAC down, put the card in the ESD-safe packaging.
2.3. Hardware Installation
Follow these instructions to install the Intel FPGA PAC in your server.
2. System Requirements and Release Installation
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1. Open your server chassis.
2. Identify an available PCIe slot with enough clearance to house the Intel FPGA PAC.
For slots that can receive a full-length PCIe card, Intel recommends that you use
the provided extension mounting bracket to secure the card edge for additional
support.
3. Remove any I/O panel covers for the slot you are using.
4. Install the Intel FPGA PAC in the PCIe slot by inserting the PCIe x16 edge
connector and ensuring the card retention hook is properly engaged.
5. Use the two screws provided to secure the I/O panel bracket to the server chassis.
If you are using the extension bracket, secure the extension bracket to the server.
6. Connect the 2 x 4-pin 12 V auxiliary power cable from the server to the matching
2 x 4-pin power connector on the Intel FPGA PAC.
7. Reinstall the chassis cover.
2.4. Setting Up the Host Machine Software
2.4.1. Installing Red Hat Enterprise Linux version 7.6
1. Enable the following options in the BIOS:
• SR-IOV
• Virtualization Technology
2. Select the following options and packages during initial installation:
— Base Environment: Server with GUI
— Add ons:
— Development Tools
— Compatibility Libraries
— Virtualization Tools
— Virtualization Hypervisor
3. Buy RHEL subscription from Red Hat* store. This step is required to fetch and
install packages from RHEL repository.
4. Execute the registration steps on your server to register with RHEL.
5. To attach the license:
subscription-manager attach --auto
6. Additionally, enable the following repository:
subscription-manager repos --enable rhel-7-server-optional-rpms
At this point the installed kernel is 3.10. You can install these packages after initial
installation of the RHEL 7.6 by running:
$ sudo yum groupinstall <package_name>
To install the Acceleration Stack, select either the Acceleration Stack for Runtime
or the Acceleration Stack for Development. The following table explains the
differences between the two versions of the Acceleration Stack.
2. System Requirements and Release Installation
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Acceleration Stack for
Runtime
Acceleration Stack for Development
Purpose Software development of
runtime host application
RTL development of an AFU using the Intel Quartus® Prime
Pro Edition and the Acceleration Stack
OPAE Software
Development Kit (SDK)
OPAE SDK version 1.1.4-3 OPAE SDK version 1.1.4-3
Intel Quartus Prime Pro
Edition
Not Included or required Included: Intel Quartus Prime Pro Edition 18.1.2 with
related interface licenses (SR-IOV and Low Latency 10
Gbps Ethernet MAC/PHY).
2.4.2. Installing the Intel Acceleration Stack Runtime Package on the
Host Machine
Follow these instructions to extract the release package and upgrade the kernel:
1. Extract the archive file:
tar xvf *rte_installer.tar.gz
2. Change to install directory:
cd *rte_installer
3. Run ./setup.sh and follow the prompts:
./setup.sh
4. You are prompted with the following question: Do you wish to install the OPAE:
Option Description
Select Yes If you have admin and network access.
Select No If you do not have admin and network access. After the installation, follow the
manual steps listed in section Installing the OPAE Software Package.
5. Accept the license.
6. When you receive an installation directory prompt, you can specify an install
directory. Otherwise, the installer uses the default directory at /home/
<username>/intelrtestack.
7. Run the initialization script to set the required environment variables and
OPAE_PLATFORM_ROOT:
source /home/<username>/intelrtestack/init_env.sh
8. Run the script setup_fim_and_bmc.sh to update the fpga image and board
management controller (BMC). For detailed instructions, refer to Identify the FPGA
Interface Manager (FIM) and BMC Firmware Version on page 13.
The $OPAE_PLATFORM_ROOT is used as a relative path to executables and files
throughout the document. The following command prints the environment variable
OPAE_PLATFORM_ROOT.
echo $OPAE_PLATFORM_ROOT
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2.4.3. Installing the Intel Acceleration Stack Development Package on the
Host Machine
Use this installation for Accelerator Functional Unit (AFU) development and
compilation.
1. Extract the runtime archive file:
tar xvf *dev_installer.tar.gz
2. Change to the installation directory:
cd *dev_installer
3. Run setup.sh.
./setup.sh
4. You are prompted with the following question: Do you wish to install the OPAE?
Option Description
Select Yes If you have admin and network access.
Select No If you do not have admin and network access. After the installation, follow the
manual steps listed in section Installing the OPAE Software Package.
5. Accept the license.
6. When you receive an installation directory prompt, you can specify an install
directory. Otherwise, the installer uses the default directory at /home/
<username>/inteldevstack to install Intel Quartus Prime Pro Edition Software
and the Intel SDK for OpenCL*.
7. Run the initialization script to set the required environment variables,
QUARTUS_HOME, OPAE_PLATFORM_ROOT, and other OpenCL variables.
source /home/<username>/inteldevstack/init_env.sh
Note: To avoid having to setup the environment variables after every reboot, save
the exported environment variables to your shell initialization script.
8. Run the script setup_fim_and_bmc.sh to update the fpga image and board
management controller (BMC). For detailed instructions, refer to Identify the FPGA
Interface Manager (FIM) and BMC Firmware Version on page 13.
The $OPAE_PLATFORM_ROOT is used as a relative path to executables and files
throughout the document. The following command prints the environment variable
OPAE_PLATFORM_ROOT.
echo $OPAE_PLATFORM_ROOT
Related Information
Installing the OPAE Software Package on page 11
2.4.4. Verifying the Installation
Ensure the Intel Acceleration Stack installed correctly.
2. System Requirements and Release Installation
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1. Check the driver installation.
lsmod | grep fpga
Sample output:
intel_fpga_pac_iopll 13392 0
intel_fpga_pac_hssi 18347 0
intel_fpga_fme 54120 0
intel_fpga_afu 32062 0
intel_fpga_afu,intel_fpga_fme
intel_fpga_pci 26439 2 intel_fpga_afu,intel_fpga_fme
fpga_mgr_mod 14693 1 intel_fpga_fme
2. Verify the OPAE library installation.
rpm -qa | grep opae
Sample output:
opae-tools-extra-1.1.4-3.x86_64
opae-intel-fpga-driver-1.1.4-3.x86_64
opae-libs-1.1.4-3.x86_64
opae-tools-1.1.4-3.x86_64
opae-ase-1.1.4-3.x86_64
opae-devel-1.1.4-3.x86_64
2. System Requirements and Release Installation
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