NXP Semiconductors KS22 Series User manual

KS22/KS20 Sub-Family Reference
Manual
Supports: MKS22FN256VLL12, MKS22FN256VLH12,
MKS22FN256VFT12; MKS22FN128VLL12, MKS22FN128VLH12,
MKS22FN128VFT12; MKS20FN256VLL12, MKS20FN256VLH12,
MKS20FN256VFT12; MKS20FN128VLL12, MKS20FN128VLH12,
MKS20FN128VFT12.
Document Number: KS22P100M120SF0RM
Rev. 3, May 2016

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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 51
1.2 Organization..................................................................................................................................................................51
1.3 Module descriptions......................................................................................................................................................51
1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................52
1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 53
1.4 Register descriptions.....................................................................................................................................................54
1.5 Conventions.................................................................................................................................................................. 55
1.5.1 Numbering systems......................................................................................................................................55
1.5.2 Typographic notation................................................................................................................................... 55
1.5.3 Special terms................................................................................................................................................56
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................57
2.2 Kinetis KS Series Feature Summary.............................................................................................................................57
2.3 Block Diagram..............................................................................................................................................................61
2.4 Module Functional Categories......................................................................................................................................62
2.4.1 ARM® Cortex®-M4 Core Modules............................................................................................................62
2.4.2 System Modules...........................................................................................................................................63
2.4.3 Memories and Memory Interfaces............................................................................................................... 64
2.4.4 Clocks...........................................................................................................................................................64
2.4.5 Security and Integrity modules.................................................................................................................... 65
2.4.6 Analog modules........................................................................................................................................... 65
2.4.7 Timer modules............................................................................................................................................. 66
2.4.8 Communication interfaces........................................................................................................................... 66
2.4.9 Human-machine interfaces.......................................................................................................................... 67
2.5 Orderable part numbers.................................................................................................................................................67
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Section number Title Page
Chapter 3
Core Overview
3.1 ARM Cortex-M4 Core Configuration.......................................................................................................................... 69
3.1.1 Buses, interconnects, and interfaces............................................................................................................ 70
3.1.2 System Tick Timer.......................................................................................................................................70
3.1.3 Debug facilities............................................................................................................................................ 70
3.1.4 Core privilege levels.................................................................................................................................... 71
3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 71
3.2.1 Interrupt priority levels................................................................................................................................ 72
3.2.2 Non-maskable interrupt................................................................................................................................72
3.2.3 Interrupt channel assignments......................................................................................................................72
3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................77
3.3.1 Wake-up sources..........................................................................................................................................78
3.4 FPU Configuration........................................................................................................................................................79
3.5 JTAG Controller Configuration....................................................................................................................................79
Chapter 4
Memories and Memory Interfaces
4.1 Flash Memory Configuration........................................................................................................................................81
4.1.1 Flash memory types..................................................................................................................................... 81
4.1.2 Flash Memory Sizes.....................................................................................................................................82
4.1.3 Flash Security...............................................................................................................................................82
4.1.4 Flash Program Restrictions.......................................................................................................................... 82
4.1.5 Flash Modes................................................................................................................................................. 82
4.1.6 Erase All Flash Contents..............................................................................................................................82
4.1.7 FTF_FOPT Register.....................................................................................................................................83
4.2 Flash Memory Controller Configuration...................................................................................................................... 83
4.2.1 Number of masters.......................................................................................................................................83
4.3 SRAM Configuration....................................................................................................................................................84
4.3.1 SRAM sizes..................................................................................................................................................84
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4.3.2 SRAM retention in low power modes..........................................................................................................85
4.4 System Register File Configuration..............................................................................................................................85
4.4.1 System Register file..................................................................................................................................... 85
4.5 VBAT Register File Configuration...............................................................................................................................86
4.5.1 VBAT register file....................................................................................................................................... 86
Chapter 5
Memory Map
5.1 Introduction...................................................................................................................................................................87
5.2 System memory map.....................................................................................................................................................87
5.2.1 Aliased bit-band regions.............................................................................................................................. 88
5.2.2 Flash Access Control Introduction...............................................................................................................90
5.3 Flash Memory Map.......................................................................................................................................................90
5.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................91
5.4 SRAM memory map.....................................................................................................................................................91
5.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................91
5.5.1 Read-after-write sequence and required serialization of memory operations..............................................92
5.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 92
5.6 Private Peripheral Bus (PPB) memory map..................................................................................................................96
Chapter 6
Clock Distribution
6.1 Introduction...................................................................................................................................................................97
6.2 Programming model......................................................................................................................................................97
6.3 High-Level device clocking diagram............................................................................................................................97
6.4 Clock definitions...........................................................................................................................................................98
6.4.1 Device clock summary.................................................................................................................................99
6.5 Internal clocking requirements..................................................................................................................................... 102
6.5.1 Clock divider values after reset....................................................................................................................103
6.5.2 VLPR mode clocking...................................................................................................................................104
6.6 Clock Gating.................................................................................................................................................................104
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6.7 Module clocks...............................................................................................................................................................104
6.7.1 PMC 1-kHz LPO clock................................................................................................................................106
6.7.2 IRC 48MHz clock........................................................................................................................................ 106
6.7.3 WDOG clocking.......................................................................................................................................... 107
6.7.4 Debug trace clock.........................................................................................................................................108
6.7.5 PORT digital filter clocking.........................................................................................................................108
6.7.6 LPTMR clocking..........................................................................................................................................109
6.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................109
6.7.8 USB FS OTG Controller clocking...............................................................................................................110
6.7.9 UART clocking............................................................................................................................................111
6.7.10 LPUART0 clocking..................................................................................................................................... 111
6.7.11 I2S/SAI clocking..........................................................................................................................................112
6.7.12 FlexIO clocking............................................................................................................................................113
6.7.13 LPI2C clocking............................................................................................................................................ 113
6.7.14 TPM clocking...............................................................................................................................................114
6.7.15 FlexCAN clocking....................................................................................................................................... 114
Chapter 7
Reset and Boot
7.1 Introduction...................................................................................................................................................................117
7.2 Reset..............................................................................................................................................................................117
7.2.1 Power-on reset (POR).................................................................................................................................. 118
7.2.2 System reset sources.................................................................................................................................... 118
7.2.3 MCU Resets................................................................................................................................................. 122
7.2.4 Reset Pin ..................................................................................................................................................... 123
7.2.5 Debug resets.................................................................................................................................................123
7.3 Boot...............................................................................................................................................................................125
7.3.1 Boot sources.................................................................................................................................................125
7.3.2 Boot options................................................................................................................................................. 125
7.3.3 FOPT boot options.......................................................................................................................................125
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7.3.4 Boot sequence.............................................................................................................................................. 126
Chapter 8
Power Management
8.1 Introduction...................................................................................................................................................................129
8.2 Clocking modes............................................................................................................................................................ 129
8.2.1 Partial Stop...................................................................................................................................................129
8.2.2 DMA Wakeup..............................................................................................................................................130
8.2.3 Compute Operation......................................................................................................................................131
8.2.4 Peripheral Doze............................................................................................................................................132
8.2.5 Clock Gating................................................................................................................................................ 133
8.3 Power Modes Description.............................................................................................................................................133
8.4 Entering and exiting power modes............................................................................................................................... 135
8.5 Power mode transitions.................................................................................................................................................136
8.6 Power modes shutdown sequencing............................................................................................................................. 137
8.7 Flash Program Restrictions...........................................................................................................................................138
8.8 Module Operation in Low Power Modes......................................................................................................................138
Chapter 9
Security
9.1 Introduction...................................................................................................................................................................143
9.2 Flash Security............................................................................................................................................................... 143
9.3 Security Interactions with other Modules.....................................................................................................................144
9.3.1 Security Interactions with Debug.................................................................................................................144
Chapter 10
Debug
10.1 Introduction...................................................................................................................................................................145
10.1.1 References....................................................................................................................................................146
10.2 The Debug Port.............................................................................................................................................................146
10.2.1 JTAG-to-SWD change sequence................................................................................................................. 147
10.2.2 JTAG-to-cJTAG change sequence...............................................................................................................147
10.3 Debug Port Pin Descriptions.........................................................................................................................................148
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10.4 System TAP connection................................................................................................................................................148
10.4.1 IR Codes.......................................................................................................................................................148
10.5 JTAG status and control registers.................................................................................................................................149
10.5.1 MDM-AP Control Register..........................................................................................................................150
10.5.2 MDM-AP Status Register............................................................................................................................ 151
10.6 Debug Resets................................................................................................................................................................ 153
10.7 AHB-AP........................................................................................................................................................................154
10.8 ITM............................................................................................................................................................................... 154
10.9 Core Trace Connectivity...............................................................................................................................................155
10.10 TPIU..............................................................................................................................................................................155
10.11 DWT............................................................................................................................................................................. 155
10.12 Debug in Low Power Modes........................................................................................................................................ 156
10.12.1 Debug Module State in Low Power Modes.................................................................................................156
10.13 Debug & Security......................................................................................................................................................... 157
Chapter 11
Signal Multiplexing and Signal Descriptions
11.1 Introduction...................................................................................................................................................................159
11.2 Pinout............................................................................................................................................................................159
11.2.1 Signal Multiplexing and Pin Assignments...................................................................................................159
11.2.2 Pinouts..........................................................................................................................................................163
11.3 Module Signal Description Tables................................................................................................................................166
11.3.1 Core Modules...............................................................................................................................................166
11.3.2 System Modules...........................................................................................................................................167
11.3.3 Clock Modules............................................................................................................................................. 167
11.3.4 Analog..........................................................................................................................................................168
11.3.5 Timer Modules.............................................................................................................................................169
11.3.6 Communication Interfaces........................................................................................................................... 170
11.3.7 Human-Machine Interfaces (HMI).............................................................................................................. 174
Chapter 12
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Section number Title Page
Port Control and Interrupts (PORT)
12.1 Chip-specific Information for this Module...................................................................................................................175
12.1.1 Signal Multiplexing Integration...................................................................................................................175
12.2 Introduction...................................................................................................................................................................177
12.3 Overview.......................................................................................................................................................................177
12.3.1 Features........................................................................................................................................................ 177
12.3.2 Modes of operation...................................................................................................................................... 178
12.4 External signal description............................................................................................................................................179
12.5 Detailed signal description............................................................................................................................................179
12.6 Memory map and register definition.............................................................................................................................180
12.6.1 Pin Control Register n (PORTx_PCRn).......................................................................................................186
12.6.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................189
12.6.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................189
12.6.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 190
12.6.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................190
12.6.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................191
12.6.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 191
12.7 Functional description...................................................................................................................................................192
12.7.1 Pin control....................................................................................................................................................192
12.7.2 Global pin control........................................................................................................................................ 193
12.7.3 External interrupts........................................................................................................................................193
12.7.4 Digital filter..................................................................................................................................................194
Chapter 13
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................197
13.1.1 Features........................................................................................................................................................ 197
13.2 Memory map and register definition.............................................................................................................................198
13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 199
13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................. 200
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13.2.3 System Options Register 5 (SIM_SOPT5).................................................................................................. 202
13.2.4 System Options Register 7 (SIM_SOPT7).................................................................................................. 204
13.2.5 System Options Register 9 (SIM_SOPT9).................................................................................................. 205
13.2.6 System Device Identification Register (SIM_SDID)...................................................................................207
13.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................209
13.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................211
13.2.9 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................212
13.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................216
13.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................216
13.2.12 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................218
13.2.13 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 219
13.2.14 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 221
13.2.15 Unique Identification Register High (SIM_UIDH)..................................................................................... 221
13.2.16 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................222
13.2.17 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 222
13.2.18 Unique Identification Register Low (SIM_UIDL)...................................................................................... 223
13.2.19 System Clock Divider Register 3 (SIM_CLKDIV3)...................................................................................223
13.2.20 Miscellaneous Control Register (SIM_MISCCTL).....................................................................................224
13.3 Functional description...................................................................................................................................................225
Chapter 14
Kinetis Flashloader
14.1 Chip-specific Information for this Module...................................................................................................................227
14.1.1 Kinetis Flashloader...................................................................................................................................... 227
14.2 Introduction...................................................................................................................................................................228
14.3 Functional Description..................................................................................................................................................229
14.3.1 Memory Maps..............................................................................................................................................229
14.3.2 Start-up Process............................................................................................................................................229
14.3.3 Clock Configuration.....................................................................................................................................232
14.3.4 Flashloader Protocol.................................................................................................................................... 232
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14.3.5 Flashloader Packet Types.............................................................................................................................237
14.3.6 Flashloader Command API..........................................................................................................................244
14.4 Peripherals Supported................................................................................................................................................... 264
14.4.1 I2C Peripheral.............................................................................................................................................. 264
14.4.2 SPI Peripheral.............................................................................................................................................. 266
14.4.3 UART Peripheral......................................................................................................................................... 268
14.4.4 USB peripheral.............................................................................................................................................270
14.4.5 CAN (or FlexCAN) Peripheral.................................................................................................................... 273
14.5 Get/SetProperty Command Properties..........................................................................................................................275
14.5.1 Property Definitions.....................................................................................................................................276
14.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 278
Chapter 15
Reset Control Module (RCM)
15.1 Introduction...................................................................................................................................................................281
15.2 Reset memory map and register descriptions............................................................................................................... 281
15.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 282
15.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 283
15.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 285
15.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 286
15.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................287
15.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................289
Chapter 16
System Mode Controller (SMC)
16.1 Introduction...................................................................................................................................................................291
16.2 Modes of operation....................................................................................................................................................... 291
16.3 Memory map and register descriptions.........................................................................................................................293
16.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................294
16.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................295
16.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................297
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16.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 298
16.4 Functional description...................................................................................................................................................299
16.4.1 Power mode transitions................................................................................................................................299
16.4.2 Power mode entry/exit sequencing.............................................................................................................. 302
16.4.3 Run modes....................................................................................................................................................304
16.4.4 Wait modes.................................................................................................................................................. 306
16.4.5 Stop modes...................................................................................................................................................306
16.4.6 Debug in low power modes......................................................................................................................... 309
Chapter 17
Power Management Controller (PMC)
17.1 Introduction...................................................................................................................................................................311
17.2 Features.........................................................................................................................................................................311
17.3 Low-voltage detect (LVD) system................................................................................................................................311
17.3.1 LVD reset operation.....................................................................................................................................312
17.3.2 LVD interrupt operation...............................................................................................................................312
17.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 312
17.4 High-voltage detect (HVD) system.............................................................................................................................. 313
17.4.1 HVD reset operation.................................................................................................................................... 313
17.4.2 HVD interrupt operation.............................................................................................................................. 313
17.5 I/O retention..................................................................................................................................................................314
17.6 Memory map and register descriptions.........................................................................................................................314
17.6.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 315
17.6.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 316
17.6.3 Regulator Status And Control register (PMC_REGSC)..............................................................................317
17.6.4 High Voltage Detect Status And Control 1 register (PMC_HVDSC1).......................................................319
Chapter 18
Low-Leakage Wakeup Unit (LLWU)
18.1 Chip-specific Information for this Module...................................................................................................................321
18.1.1 Wake-up Sources......................................................................................................................................... 321
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18.2 Introduction...................................................................................................................................................................322
18.2.1 Features........................................................................................................................................................ 323
18.2.2 Modes of operation...................................................................................................................................... 323
18.2.3 Block diagram..............................................................................................................................................324
18.3 LLWU signal descriptions............................................................................................................................................ 325
18.4 Memory map/register definition................................................................................................................................... 326
18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................327
18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................328
18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................329
18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................330
18.4.5 LLWU Pin Enable 5 register (LLWU_PE5)................................................................................................331
18.4.6 LLWU Pin Enable 6 register (LLWU_PE6)................................................................................................332
18.4.7 LLWU Pin Enable 7 register (LLWU_PE7)................................................................................................334
18.4.8 LLWU Pin Enable 8 register (LLWU_PE8)................................................................................................335
18.4.9 LLWU Module Enable register (LLWU_ME)............................................................................................ 336
18.4.10 LLWU Pin Flag 1 register (LLWU_PF1)....................................................................................................337
18.4.11 LLWU Pin Flag 2 register (LLWU_PF2)....................................................................................................339
18.4.12 LLWU Pin Flag 3 register (LLWU_PF3)....................................................................................................341
18.4.13 LLWU Pin Flag 4 register (LLWU_PF4)....................................................................................................342
18.4.14 LLWU Module Flag 5 register (LLWU_MF5)............................................................................................344
18.4.15 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 346
18.4.16 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 347
18.5 Functional description...................................................................................................................................................348
18.5.1 LLS mode.....................................................................................................................................................348
18.5.2 VLLS modes................................................................................................................................................ 349
18.5.3 Initialization................................................................................................................................................. 349
Chapter 19
Miscellaneous Control Module (MCM)
19.1 Introduction...................................................................................................................................................................351
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19.1.1 Features........................................................................................................................................................ 351
19.2 Memory map/register descriptions............................................................................................................................... 351
19.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................352
19.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 352
19.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 353
19.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 353
19.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 356
19.3 Functional description...................................................................................................................................................357
19.3.1 Interrupts...................................................................................................................................................... 357
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Chip-specific Information for this Module...................................................................................................................359
20.1.1 Crossbar-Lite Switch Master Assignments..................................................................................................359
20.1.2 Crossbar-Lite Switch Slave Assignments....................................................................................................359
20.2 Introduction...................................................................................................................................................................359
20.2.1 Features........................................................................................................................................................ 360
20.3 Memory Map / Register Definition...............................................................................................................................360
20.4 Functional Description..................................................................................................................................................360
20.4.1 General operation.........................................................................................................................................360
20.4.2 Arbitration....................................................................................................................................................361
20.5 Initialization/application information........................................................................................................................... 363
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Chip-specific Information for this Module...................................................................................................................365
21.1.1 Number of peripheral bridges...................................................................................................................... 365
21.1.2 Memory maps.............................................................................................................................................. 365
21.2 Introduction...................................................................................................................................................................365
21.2.1 Features........................................................................................................................................................ 365
21.2.2 General operation.........................................................................................................................................366
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21.3 Memory map/register definition................................................................................................................................... 366
21.4 Functional description...................................................................................................................................................366
21.4.1 Access support............................................................................................................................................. 366
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Chip-specific Information for this Module...................................................................................................................367
22.1.1 DMA MUX request sources........................................................................................................................ 367
22.1.2 DMA transfers via PIT trigger.....................................................................................................................369
22.2 Introduction...................................................................................................................................................................369
22.2.1 Overview......................................................................................................................................................369
22.2.2 Features........................................................................................................................................................ 370
22.2.3 Modes of operation...................................................................................................................................... 370
22.3 External signal description............................................................................................................................................371
22.4 Memory map/register definition................................................................................................................................... 371
22.4.1 Endianness................................................................................................................................................... 371
22.4.2 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 372
22.5 Functional description...................................................................................................................................................373
22.5.1 DMA channels with periodic triggering capability......................................................................................374
22.5.2 DMA channels with no triggering capability...............................................................................................376
22.5.3 Always-enabled DMA sources.................................................................................................................... 376
22.6 Initialization/application information........................................................................................................................... 377
22.6.1 Reset.............................................................................................................................................................377
22.6.2 Enabling and configuring sources................................................................................................................377
Chapter 23
Enhanced Direct Memory Access (eDMA)
23.1 Introduction...................................................................................................................................................................381
23.1.1 eDMA system block diagram...................................................................................................................... 381
23.1.2 Block parts................................................................................................................................................... 382
23.1.3 Features........................................................................................................................................................ 383
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23.2 Modes of operation....................................................................................................................................................... 384
23.3 Memory map/register definition................................................................................................................................... 385
23.3.1 TCD memory............................................................................................................................................... 385
23.3.2 TCD initialization........................................................................................................................................ 385
23.3.3 TCD structure...............................................................................................................................................385
23.3.4 Reserved memory and bit fields...................................................................................................................386
23.3.1 Control Register (DMA_CR).......................................................................................................................397
23.3.2 Error Status Register (DMA_ES)................................................................................................................ 400
23.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 402
23.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................404
23.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 406
23.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 407
23.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................408
23.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................409
23.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................410
23.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 411
23.3.11 Clear Error Register (DMA_CERR)............................................................................................................412
23.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 413
23.3.13 Interrupt Request Register (DMA_INT)......................................................................................................414
23.3.14 Error Register (DMA_ERR)........................................................................................................................ 416
23.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 419
23.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................422
23.3.17 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 424
23.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................425
23.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................425
23.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................426
23.3.21 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 427
23.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................428
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23.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 429
23.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................430
23.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................431
23.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................431
23.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................432
23.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 433
23.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 434
23.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 435
23.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................437
23.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 438
23.4 Functional description...................................................................................................................................................439
23.4.1 eDMA basic data flow................................................................................................................................. 439
23.4.2 Fault reporting and handling........................................................................................................................442
23.4.3 Channel preemption..................................................................................................................................... 445
23.4.4 Performance................................................................................................................................................. 445
23.5 Initialization/application information........................................................................................................................... 449
23.5.1 eDMA initialization..................................................................................................................................... 449
23.5.2 Programming errors..................................................................................................................................... 451
23.5.3 Arbitration mode considerations..................................................................................................................452
23.5.4 Performing DMA transfers.......................................................................................................................... 452
23.5.5 Monitoring transfer descriptor status........................................................................................................... 456
23.5.6 Channel Linking...........................................................................................................................................458
23.5.7 Dynamic programming................................................................................................................................ 459
Chapter 24
External Watchdog Monitor (EWM)
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Section number Title Page
24.1 Chip-specific Information for this Module...................................................................................................................465
24.1.1 EWM clocks.................................................................................................................................................465
24.1.2 EWM low-power modes.............................................................................................................................. 465
24.1.3 EWM_OUT pin state in low power modes..................................................................................................465
24.2 Introduction...................................................................................................................................................................466
24.2.1 Features........................................................................................................................................................ 466
24.2.2 Modes of Operation..................................................................................................................................... 467
24.2.3 Block Diagram............................................................................................................................................. 468
24.3 EWM Signal Descriptions............................................................................................................................................ 468
24.4 Memory Map/Register Definition.................................................................................................................................469
24.4.1 Control Register (EWM_CTRL)................................................................................................................. 469
24.4.2 Service Register (EWM_SERV)..................................................................................................................470
24.4.3 Compare Low Register (EWM_CMPL)......................................................................................................470
24.4.4 Compare High Register (EWM_CMPH).....................................................................................................471
24.4.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................472
24.5 Functional Description..................................................................................................................................................472
24.5.1 The EWM_out Signal.................................................................................................................................. 472
24.5.2 The EWM_in Signal.................................................................................................................................... 473
24.5.3 EWM Counter..............................................................................................................................................474
24.5.4 EWM Compare Registers............................................................................................................................ 474
24.5.5 EWM Refresh Mechanism...........................................................................................................................474
24.5.6 EWM Interrupt.............................................................................................................................................475
24.5.7 Counter clock prescaler................................................................................................................................475
Chapter 25
Watchdog timer (WDOG)
25.1 Chip-specific Information for this Module...................................................................................................................477
25.1.1 WDOG clocks..............................................................................................................................................477
25.1.2 WDOG low-power modes........................................................................................................................... 477
25.2 Introduction...................................................................................................................................................................478
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Section number Title Page
25.3 Features.........................................................................................................................................................................478
25.4 Functional overview......................................................................................................................................................479
25.4.1 Unlocking and updating the watchdog.........................................................................................................481
25.4.2 Watchdog configuration time (WCT)..........................................................................................................482
25.4.3 Refreshing the watchdog..............................................................................................................................483
25.4.4 Windowed mode of operation......................................................................................................................483
25.4.5 Watchdog disabled mode of operation.........................................................................................................483
25.4.6 Debug modes of operation........................................................................................................................... 483
25.5 Testing the watchdog.................................................................................................................................................... 484
25.5.1 Quick test..................................................................................................................................................... 485
25.5.2 Byte test........................................................................................................................................................485
25.6 Backup reset generator..................................................................................................................................................486
25.7 Generated resets and interrupts.....................................................................................................................................487
25.8 Memory map and register definition.............................................................................................................................487
25.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 488
25.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 490
25.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................490
25.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................491
25.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 491
25.8.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 492
25.8.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 492
25.8.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................492
25.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 493
25.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 493
25.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 494
25.8.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 494
25.9 Watchdog operation with 8-bit access.......................................................................................................................... 494
25.9.1 General guideline......................................................................................................................................... 494
25.9.2 Refresh and unlock operations with 8-bit access.........................................................................................495
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Section number Title Page
25.10 Restrictions on watchdog operation..............................................................................................................................496
Chapter 26
Multipurpose Clock Generator (MCG)
26.1 Chip-specific Information for this Module...................................................................................................................499
26.1.1 MCG oscillator clock input options.............................................................................................................499
26.1.2 MCG Instantiation Information................................................................................................................... 499
26.2 Introduction...................................................................................................................................................................500
26.2.1 Features........................................................................................................................................................ 500
26.2.2 Modes of Operation..................................................................................................................................... 503
26.3 External Signal Description.......................................................................................................................................... 504
26.4 Memory Map/Register Definition.................................................................................................................................504
26.4.1 MCG Control 1 Register (MCG_C1)...........................................................................................................505
26.4.2 MCG Control 2 Register (MCG_C2)...........................................................................................................506
26.4.3 MCG Control 3 Register (MCG_C3)...........................................................................................................507
26.4.4 MCG Control 4 Register (MCG_C4)...........................................................................................................508
26.4.5 MCG Control 5 Register (MCG_C5)...........................................................................................................509
26.4.6 MCG Control 6 Register (MCG_C6)...........................................................................................................510
26.4.7 MCG Status Register (MCG_S).................................................................................................................. 512
26.4.8 MCG Status and Control Register (MCG_SC)............................................................................................513
26.4.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 515
26.4.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................515
26.4.11 MCG Control 7 Register (MCG_C7)...........................................................................................................515
26.4.12 MCG Control 8 Register (MCG_C8)...........................................................................................................516
26.4.13 MCG Control 12 Register (MCG_C12).......................................................................................................517
26.4.13 MCG Status 2 Register (MCG_S2)............................................................................................................. 517
26.4.13 MCG Test 3 Register (MCG_T3)................................................................................................................ 518
26.5 Functional description...................................................................................................................................................518
26.5.1 MCG mode state diagram............................................................................................................................ 518
26.5.2 Low-power bit usage....................................................................................................................................522
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