NXP Semiconductors KS22 Series User manual

KS22/KS20 Sub-Family Reference
Manual
Supports: MKS22FN256VLL12, MKS22FN256VLH12,
MKS22FN256VFT12; MKS22FN128VLL12, MKS22FN128VLH12,
MKS22FN128VFT12; MKS20FN256VLL12, MKS20FN256VLH12,
MKS20FN256VFT12; MKS20FN128VLL12, MKS20FN128VLH12,
MKS20FN128VFT12.
Document Number: KS22P100M120SF0RM
Rev. 3, May 2016

KS22/KS20 Sub-Family Reference Manual , Rev. 3, May 2016
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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 51
1.2 Organization..................................................................................................................................................................51
1.3 Module descriptions......................................................................................................................................................51
1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................52
1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 53
1.4 Register descriptions.....................................................................................................................................................54
1.5 Conventions.................................................................................................................................................................. 55
1.5.1 Numbering systems......................................................................................................................................55
1.5.2 Typographic notation................................................................................................................................... 55
1.5.3 Special terms................................................................................................................................................56
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................57
2.2 Kinetis KS Series Feature Summary.............................................................................................................................57
2.3 Block Diagram..............................................................................................................................................................61
2.4 Module Functional Categories......................................................................................................................................62
2.4.1 ARM® Cortex®-M4 Core Modules............................................................................................................62
2.4.2 System Modules...........................................................................................................................................63
2.4.3 Memories and Memory Interfaces............................................................................................................... 64
2.4.4 Clocks...........................................................................................................................................................64
2.4.5 Security and Integrity modules.................................................................................................................... 65
2.4.6 Analog modules........................................................................................................................................... 65
2.4.7 Timer modules............................................................................................................................................. 66
2.4.8 Communication interfaces........................................................................................................................... 66
2.4.9 Human-machine interfaces.......................................................................................................................... 67
2.5 Orderable part numbers.................................................................................................................................................67
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Section number Title Page
Chapter 3
Core Overview
3.1 ARM Cortex-M4 Core Configuration.......................................................................................................................... 69
3.1.1 Buses, interconnects, and interfaces............................................................................................................ 70
3.1.2 System Tick Timer.......................................................................................................................................70
3.1.3 Debug facilities............................................................................................................................................ 70
3.1.4 Core privilege levels.................................................................................................................................... 71
3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 71
3.2.1 Interrupt priority levels................................................................................................................................ 72
3.2.2 Non-maskable interrupt................................................................................................................................72
3.2.3 Interrupt channel assignments......................................................................................................................72
3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................77
3.3.1 Wake-up sources..........................................................................................................................................78
3.4 FPU Configuration........................................................................................................................................................79
3.5 JTAG Controller Configuration....................................................................................................................................79
Chapter 4
Memories and Memory Interfaces
4.1 Flash Memory Configuration........................................................................................................................................81
4.1.1 Flash memory types..................................................................................................................................... 81
4.1.2 Flash Memory Sizes.....................................................................................................................................82
4.1.3 Flash Security...............................................................................................................................................82
4.1.4 Flash Program Restrictions.......................................................................................................................... 82
4.1.5 Flash Modes................................................................................................................................................. 82
4.1.6 Erase All Flash Contents..............................................................................................................................82
4.1.7 FTF_FOPT Register.....................................................................................................................................83
4.2 Flash Memory Controller Configuration...................................................................................................................... 83
4.2.1 Number of masters.......................................................................................................................................83
4.3 SRAM Configuration....................................................................................................................................................84
4.3.1 SRAM sizes..................................................................................................................................................84
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Section number Title Page
4.3.2 SRAM retention in low power modes..........................................................................................................85
4.4 System Register File Configuration..............................................................................................................................85
4.4.1 System Register file..................................................................................................................................... 85
4.5 VBAT Register File Configuration...............................................................................................................................86
4.5.1 VBAT register file....................................................................................................................................... 86
Chapter 5
Memory Map
5.1 Introduction...................................................................................................................................................................87
5.2 System memory map.....................................................................................................................................................87
5.2.1 Aliased bit-band regions.............................................................................................................................. 88
5.2.2 Flash Access Control Introduction...............................................................................................................90
5.3 Flash Memory Map.......................................................................................................................................................90
5.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................91
5.4 SRAM memory map.....................................................................................................................................................91
5.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................91
5.5.1 Read-after-write sequence and required serialization of memory operations..............................................92
5.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 92
5.6 Private Peripheral Bus (PPB) memory map..................................................................................................................96
Chapter 6
Clock Distribution
6.1 Introduction...................................................................................................................................................................97
6.2 Programming model......................................................................................................................................................97
6.3 High-Level device clocking diagram............................................................................................................................97
6.4 Clock definitions...........................................................................................................................................................98
6.4.1 Device clock summary.................................................................................................................................99
6.5 Internal clocking requirements..................................................................................................................................... 102
6.5.1 Clock divider values after reset....................................................................................................................103
6.5.2 VLPR mode clocking...................................................................................................................................104
6.6 Clock Gating.................................................................................................................................................................104
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Section number Title Page
6.7 Module clocks...............................................................................................................................................................104
6.7.1 PMC 1-kHz LPO clock................................................................................................................................106
6.7.2 IRC 48MHz clock........................................................................................................................................ 106
6.7.3 WDOG clocking.......................................................................................................................................... 107
6.7.4 Debug trace clock.........................................................................................................................................108
6.7.5 PORT digital filter clocking.........................................................................................................................108
6.7.6 LPTMR clocking..........................................................................................................................................109
6.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................109
6.7.8 USB FS OTG Controller clocking...............................................................................................................110
6.7.9 UART clocking............................................................................................................................................111
6.7.10 LPUART0 clocking..................................................................................................................................... 111
6.7.11 I2S/SAI clocking..........................................................................................................................................112
6.7.12 FlexIO clocking............................................................................................................................................113
6.7.13 LPI2C clocking............................................................................................................................................ 113
6.7.14 TPM clocking...............................................................................................................................................114
6.7.15 FlexCAN clocking....................................................................................................................................... 114
Chapter 7
Reset and Boot
7.1 Introduction...................................................................................................................................................................117
7.2 Reset..............................................................................................................................................................................117
7.2.1 Power-on reset (POR).................................................................................................................................. 118
7.2.2 System reset sources.................................................................................................................................... 118
7.2.3 MCU Resets................................................................................................................................................. 122
7.2.4 Reset Pin ..................................................................................................................................................... 123
7.2.5 Debug resets.................................................................................................................................................123
7.3 Boot...............................................................................................................................................................................125
7.3.1 Boot sources.................................................................................................................................................125
7.3.2 Boot options................................................................................................................................................. 125
7.3.3 FOPT boot options.......................................................................................................................................125
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Section number Title Page
7.3.4 Boot sequence.............................................................................................................................................. 126
Chapter 8
Power Management
8.1 Introduction...................................................................................................................................................................129
8.2 Clocking modes............................................................................................................................................................ 129
8.2.1 Partial Stop...................................................................................................................................................129
8.2.2 DMA Wakeup..............................................................................................................................................130
8.2.3 Compute Operation......................................................................................................................................131
8.2.4 Peripheral Doze............................................................................................................................................132
8.2.5 Clock Gating................................................................................................................................................ 133
8.3 Power Modes Description.............................................................................................................................................133
8.4 Entering and exiting power modes............................................................................................................................... 135
8.5 Power mode transitions.................................................................................................................................................136
8.6 Power modes shutdown sequencing............................................................................................................................. 137
8.7 Flash Program Restrictions...........................................................................................................................................138
8.8 Module Operation in Low Power Modes......................................................................................................................138
Chapter 9
Security
9.1 Introduction...................................................................................................................................................................143
9.2 Flash Security............................................................................................................................................................... 143
9.3 Security Interactions with other Modules.....................................................................................................................144
9.3.1 Security Interactions with Debug.................................................................................................................144
Chapter 10
Debug
10.1 Introduction...................................................................................................................................................................145
10.1.1 References....................................................................................................................................................146
10.2 The Debug Port.............................................................................................................................................................146
10.2.1 JTAG-to-SWD change sequence................................................................................................................. 147
10.2.2 JTAG-to-cJTAG change sequence...............................................................................................................147
10.3 Debug Port Pin Descriptions.........................................................................................................................................148
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Section number Title Page
10.4 System TAP connection................................................................................................................................................148
10.4.1 IR Codes.......................................................................................................................................................148
10.5 JTAG status and control registers.................................................................................................................................149
10.5.1 MDM-AP Control Register..........................................................................................................................150
10.5.2 MDM-AP Status Register............................................................................................................................ 151
10.6 Debug Resets................................................................................................................................................................ 153
10.7 AHB-AP........................................................................................................................................................................154
10.8 ITM............................................................................................................................................................................... 154
10.9 Core Trace Connectivity...............................................................................................................................................155
10.10 TPIU..............................................................................................................................................................................155
10.11 DWT............................................................................................................................................................................. 155
10.12 Debug in Low Power Modes........................................................................................................................................ 156
10.12.1 Debug Module State in Low Power Modes.................................................................................................156
10.13 Debug & Security......................................................................................................................................................... 157
Chapter 11
Signal Multiplexing and Signal Descriptions
11.1 Introduction...................................................................................................................................................................159
11.2 Pinout............................................................................................................................................................................159
11.2.1 Signal Multiplexing and Pin Assignments...................................................................................................159
11.2.2 Pinouts..........................................................................................................................................................163
11.3 Module Signal Description Tables................................................................................................................................166
11.3.1 Core Modules...............................................................................................................................................166
11.3.2 System Modules...........................................................................................................................................167
11.3.3 Clock Modules............................................................................................................................................. 167
11.3.4 Analog..........................................................................................................................................................168
11.3.5 Timer Modules.............................................................................................................................................169
11.3.6 Communication Interfaces........................................................................................................................... 170
11.3.7 Human-Machine Interfaces (HMI).............................................................................................................. 174
Chapter 12
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Section number Title Page
Port Control and Interrupts (PORT)
12.1 Chip-specific Information for this Module...................................................................................................................175
12.1.1 Signal Multiplexing Integration...................................................................................................................175
12.2 Introduction...................................................................................................................................................................177
12.3 Overview.......................................................................................................................................................................177
12.3.1 Features........................................................................................................................................................ 177
12.3.2 Modes of operation...................................................................................................................................... 178
12.4 External signal description............................................................................................................................................179
12.5 Detailed signal description............................................................................................................................................179
12.6 Memory map and register definition.............................................................................................................................180
12.6.1 Pin Control Register n (PORTx_PCRn).......................................................................................................186
12.6.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................189
12.6.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................189
12.6.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 190
12.6.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................190
12.6.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................191
12.6.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 191
12.7 Functional description...................................................................................................................................................192
12.7.1 Pin control....................................................................................................................................................192
12.7.2 Global pin control........................................................................................................................................ 193
12.7.3 External interrupts........................................................................................................................................193
12.7.4 Digital filter..................................................................................................................................................194
Chapter 13
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................197
13.1.1 Features........................................................................................................................................................ 197
13.2 Memory map and register definition.............................................................................................................................198
13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 199
13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................. 200
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13.2.3 System Options Register 5 (SIM_SOPT5).................................................................................................. 202
13.2.4 System Options Register 7 (SIM_SOPT7).................................................................................................. 204
13.2.5 System Options Register 9 (SIM_SOPT9).................................................................................................. 205
13.2.6 System Device Identification Register (SIM_SDID)...................................................................................207
13.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................209
13.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................211
13.2.9 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................212
13.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................216
13.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................216
13.2.12 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................218
13.2.13 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 219
13.2.14 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 221
13.2.15 Unique Identification Register High (SIM_UIDH)..................................................................................... 221
13.2.16 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................222
13.2.17 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 222
13.2.18 Unique Identification Register Low (SIM_UIDL)...................................................................................... 223
13.2.19 System Clock Divider Register 3 (SIM_CLKDIV3)...................................................................................223
13.2.20 Miscellaneous Control Register (SIM_MISCCTL).....................................................................................224
13.3 Functional description...................................................................................................................................................225
Chapter 14
Kinetis Flashloader
14.1 Chip-specific Information for this Module...................................................................................................................227
14.1.1 Kinetis Flashloader...................................................................................................................................... 227
14.2 Introduction...................................................................................................................................................................228
14.3 Functional Description..................................................................................................................................................229
14.3.1 Memory Maps..............................................................................................................................................229
14.3.2 Start-up Process............................................................................................................................................229
14.3.3 Clock Configuration.....................................................................................................................................232
14.3.4 Flashloader Protocol.................................................................................................................................... 232
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