
4-4
CIRCUIT DESCRIPTION, FAULT FINDING
PM
6303A
4.8 ANALOG
TO
DIGITAL CONVERTER, ADC, Fig.
57
The
outputsignal ofthephasesensitive rectifier isconverted intodigital
data
by
a dual-slope analogto
digitalcoverter.
The
ADe
comprises Integrator N203, zerocontrol N204,comparatorN205. ADe con-
Irol
0204,
0205
and
a 19-bltcounter.
The
latteris composed
by
the
II
-bitcounter 031 0 In fig. 58 and
an
B-bit
counter within
the
microprocessor
0315
. Oscilloscope drawings In fig. 8
show
one complete
measurement cycle. fig. 9 enlightens one conversion period wtthin one of the single measurement
cycles.
Highsignal
STI
oftha
microprocessor
0315
.5preparestheconversion
attt
.
The
timet2-tl
may
vary
tromOto
1ms
(1
pulseduration).
Thestartpulseduration
is I .
Sms
.
Thetrailingedgeoftne
1kHzsignal
at
0205
.1 sets the output 5 to high
to
startthe Integration att2.
ST2
switches the zero control off and
connectstheoutputofthephasesensitiverec1ifiervta
CMOS
switch0201 to
the
inputof
the
integrator.
This is done duringthezero period
01
the measurement pulses.
For
this the 1
kHz
90-
signal Is taken.
The
integrator reference current, defined by
R221
, R222, is equal
for
integration
(12
to
14)
and de-in-
tegration (discharge slope t4 to t5).
The
difference between input current. defined by measurement
voltagepulsesand resistorR220,and theintegratorreference currenteffectstheoutput vottage ofthe
integrator to go in negative direction. At t2 flipflop
0203
and counter
0204
are aC1ivated.
The
flipflop
divides the 1 kHz frequency by 2, feeding the down counter which was preset to 10.
At
t3, counter
stage 7, high signal MR,
0204
.
6,
resets the
It-bit
counterto
zero.
Low
signal
0204
.7 resets flipflop
0203
ofthecomparatorenabledagain att4.
At
t4 thecounterstageiszero. Atthe trailing edgeofthe t
kHz signal the output
0204.13
generates a short low pulse resetting
0205
and
so
terminating the in-
tegration and starting the de-Integration. The integration period
T1
_
20
ms
comprises
20
pulses; so
zero- and time--symmetrtcal50HznoiseandIts odd harmonicshavenoinfluenceon themeasurement
result.
When
0205
isreset att4,all 3enableinputs at NANDgate
0309,
fig. 58,arehigh;so the 16
MHz
count
pulsescan pass tothe
"-bit
counter031 O.
The
carry
ofthecountertoggles the8-bltcounterwtthinthe
mocroprocessor, input 15.
At t5 the output voltage ofthe integratorcrosses thezero level causing
the
comparator
an
the
flipflop
0203
.9to
tum
overto low.This signal EOI. 'endofintegration', disables
gate
0309
tostopthe 16
MHz
count pulses.
The
counter state at t5 is proportional tothe integrator output voltage at t4 and conse-
quently to the measurement value. For reference measurement the integrator output is
ca
. 5 V att4
resulting in
12.
ca
. 15ms, corresponding to 240.000count pulses.
The
maxlmuncounterstate is
ca
.
475.000 -
T2
-
29
.7 ms, the minimum is ca. 5000 _
T2
_ 0.3 ms.
So
tor
the
measurement range
ca
.
±23S
.ooo count pulses are available.
As thetilt ofthede-integrationIs independentofthe measurementvalue, the delay time betweenzero
crossing and comparator tum-over and
so
the counter state for every single measurement is equal;
hence the dtfference
of
the counter states is not affected.
The
output
0203
.9 ofthe comparatorIs sensed by the CPU.
Low
signal EOI at
tS
causes
the
CPU to
storethe 19-bltcountercontents into the memory.
The
CPU sends a reset pulse RST at IS preparing
the
circuitrytorthe
nextsinglemeasurement
cyde
:thezero controlisactivateddecreasing
the
integra-
tor
output voltageto zero. In the rest position the zero control has
to
compensate theintegrator refe
r-
ence current.