Philips PM 6303 User manual

RCL meter
PM 6303
9452 063 03001
Service manual
9499 525 00911
8403 01/1
PHILIPS

Please note
In correspondence concerning this instrument, please quote the type number and serial number as given on the
type plate.
Bitte beachten
Bei Schriftwechsel iiber dieses Gerat wird gebeten, die Typennummer und die Geratenummer anzugeben. Diese
befinden sich auf dem Typenschild an der Riickseite des Gerates.
Noter s. v. p.
Dans votre correspondance et dans vos réclamations se rapportant 4 cet appareil, veuillez toujours indiquer le
numéro de type et le numéro de série qui sont marqués sur la plaquette de caractéristiques.
Important
As
the
instrument
is
an
electrical
apparatus,
it
may
be
operated
only
by
trained
personnel.
Maintenance
and
repairs
may
also
be
carried
out
only
by
qualified
personnel.
Wichtig
Da
das
Gerat
ein
elektrisches
Betriebsmittel
ist,
darf
die
Bedienung
nur
durch
eingewiesenes
Personal
erfolgen.
Wartung
und
Reparatur
diirfen
nur
von
geschultem,
fach-
und
sachkundigem
Personal
durchgefiihrt
werden.
important
Comme
I'instrument
est
un
équipement
électrique,
le
service
doit
@tre
assuré
par
du
personnel
qualifié.
De
méme,
I’entretien
et
les
réparations
sont
A
confier
aux
personnes
suffisement
qualifiées.
(c)
Philips
GmbH
—
Hamburg
—
Germany
—
1984
All rights are strictly reserved.
Reproduction
or
divulgation
in
any
form
whatsoever
is
not
permitted
without
written
authority
from
the
copyright
owner.
Issued by Philips GmbH -Unternehmensbereich Elektronik fiir Wissenschaft und Industrie- Werk fir MeBtechnik
Printed in Germany

0-3
CONTENTS
1. SAFETY INSTRUCTIONS
1.1. Safety precautions
1.2. Caution and warning statements
1.3. Symbols
1.4. Impaired safety-protection
1.5. General clauses
2. OPERATING PRINCIPLE
2.1. Description of the block diagram
2.2. Measuring principle
Fig. 1 One single measurement
Fig. 2 One measurement cycle
Fig. 3 Block diagram
Fig. 4 Front view
3. CIRCUIT DESCRIPTION, FAULT FINDING, with figs. 5 -13
3.1. Crystal clock, frequency divider,phase selector
3.2. Component connection, buffer, inverting amplifier
3.3. Current to voltage converter
3.4. Programmable amplifier
3.5. Band-pass filter 2
3.6. Level detector
3.7. Phase sensitive rectifier
3.8. Analog to digital converter, ADC
3.9. Central processing unit, CPU
3.10. Parameter selection
3.11. Liquid-crystal display, LCD
3.12. Power supply
3.13. Self-test program, Error messages
3.14. Diagnostic program
4. ACCESS TO PARTS
4.1. Dismantling the cabinet
4.2. Unit 2: display unit
4.3. Pushbuttons
4.4. Carrying handle
5. PERFORMANCE CHECK
5.1. General information
5.2. General functional test
6. CHECKING AND ADJUSTING
6.1. General information
6.2. Recommended test equipment
6.3. Table of checks and adjustments
1-1
1-1
1-1
1-1
1-1
2-1
2-2
2-3
2-3
2-4
2-4
4-1
4-1
4-1
4-1
5-1
5-1
6-1
6-1
6-2

7.1.
7.2.
7.3.
7.4.
8.1.
8.2.
8.3.
8.4.
Fig.
Fig.
Fig
10.
11.
15
16
.17
Fig.
18
0-4
SAFETY INSPECTION AND TESTS AFTER REPAIR AND MAINTENANCE
IN THE PRIMARY CIRCUIT
General directives
Safety components
Checking the protective earth connection
Checking the insulation resistance
SPARE PARTS
General
Static sensitive components
Handling MOS devices
Parts list
FIGURES 15 - 18
Handle: spare parts
Mains cable: spare parts
Unit 1, Unit 2: component lay-outs
Unit 1, Unit 2: circuit diagrams
CODING SYSTEM OF FAILURE REPORTING FOR QUALITY
ADDRESSES FOR SALES AND SERVICE
7-1
7-1
7-1
7-1
8-1
8-1
8-1
8-2

1.1.
1.2.
1.3.
1.4,
1.5.
1.5.1.
1.5.2.
1.5.3.
1.5.4.
1.5.5.
1.5.6.
SAFETY INSTRUCTIONS
WARNING:
These servicing instructions are of use by qualified personnel only. To reduce the risk of electric shock,
do not perform any servicing other then that specified in the Operating Instructions unless you are fully
qualified to do so.
Read these pages carefully before installation and use of the instrument.
‘The following clauses contain information, cautions and warnings which must be followed to ensure
safe operation and to retain the instrument in a safe condition.
Adjustment, maintenance and repair of the instrument shall be carried out only by qualified personnel.
SAFETY PRECAUTIONS
For the correct and safe use of this instrument it is essential that both operating and servicing personnel
follow generally-accepted safety procedures in addition to the safety precautions specified in this manual.
Specific warning and caution statements, where they apply, will be found throughout the manual.
Where necessary, the warning and caution statements and/or symbols are marked on the apparatus.
CAUTION AND WARNING STATEMENTS
CAUTION:
Is used to indicate correct operating or maintenance procedures in order to prevent damage to or de-
struction of the equipment or other property.
WARNING:
Calls attention to a potential danger that requires correct procedures or practices in order to prevent
personal injury.
SYMBOLS
C) Protective earth (black)
(grounding) terminal
IMPAIRED SAFETY—PROTECTION
Whenever it is likely that safety-protection has been impaired, the instrument must be made inoperative
and be secured against any unintended operation. The matter should then be referred to qualified
technicians.
Safety protection is likely to be impaired if, for example, the instrument fails to perform the intenced
measurements or shows visible damage.
GENERAL CLAUSES
WARNING:
The opening of covers or removal of parts, except those to which access can be gained by hand, is likey
to expose live parts and accessible terminals which can be dangerous to live.
The instrument shall be disconnected from all voltage sources before it is opened.
Bear in mind that capacitors inside the instrument can hold their charge even if the instrument has bein
separated from all voltage sources.
WARNING:
Any interruption of the protective earth conductor inside or outside the instrument, or disconnection
of the protective earth terminal, is likely to make the instrument dangerous.
Intentional interruption is prohibited.
Components
which
are
important
for
the
safety
of
the
instrument
may
only
be
renewed
by
componerts
obtained
through
your
local
Philips
organisation
(see
also
chapter
8).
After repair and maintenance in the primary circuit, safety inspection and tests, as mentioned in chapier”
8, have to be performed.

2.1.
2-1
OPERATING PRINCIPLE
DESCRIPTION OF THE BLOCK DIAGRAM, Fig. 3
The 16 MHz crystal clock generates the basic frequency for all signals, so the count pulses for the
analog to digital converter ADC.
The frequency divider generates the 8 MHz clock pulse for the microprocessor and the 1 kHz test fre-
quency in 3 reference phases, namely 0°, 90° and 180°.
In the phase selector the CPU selects the appropriate reference phase 0°, 90° or 180° for the phase
sensitive rectifier and the ADC.
The band-pass filter 1 converts the TTL signal into a 1 kHz sine wave signal.
The test voltage amplifier _amplifies i the 1 kHz sine wave signal to a 2 Veff open circuit voltage at the
component under test (CUT) connection. In the ‘Cs biased’ mode 2 Vdc are added to the 1 kHz signal.
‘ The isolating buffer senses the voitage at the CUT.
The inverting amplifier feeds a compensating current via capacitor C (90° phase shift) into the current
to voltage converter input for equalizing the stray capacitances. The amplitude of the compensating
current is set by Co TRIM.
The current to voltage converter converts the current through the CUT into a proportional voltage.
The conversion factor can be switched by a factor of 10.
For current or voltage measurement the input of the subsequent differential amplifier is switched
over by the voltage/current (V/l) selector controlled by the CPU.
In the programmable amplifier gain factors x0.1, x1 or x10 are selected by the CPU depending on the
impedance of the CUT. For the reference measurement the input is short-circuited.
The 1 kHz band-pass filter 2 suppresses hum interference and reduces the harmonic components of the
1 kHz measurement signal.
The level detector compares the output voltage of band filter 2 with a preset reference value. If this
value is exceeded, the CPU switches the programmable amplifier to a lower gain factor.
The phase sensitive rectifier generates dc voltages which are proportional to that component of the
measuring voltage being in-phase with the reference voltage.
The analog to digital converter ADC converts the output signal of the rectifier into a binary number
which can be processed by the CPU.
The central processing unit CPU with the inherent microprocessor controls and monitores the measu-
rement process, computates and stores the measurement values and transfers the result to the display.
The LCD control transforms the serial data transmitted by the CPU into parallel data and contrds
the liquid-crystal display which operates in duplex mode.
In the LED control the parameter key actuations are verified and processed. The selected parametr
is indicated by a LED. Simultaneously the information is BCD-coded and sent to the CPU, whereby
the
most
significant
bit
directly
switches
on
the
2
Vdc
voltage,
when
the
parameter
Cs
(2
V
Bias)
is
set.
The
power
supply
generates
the
required
stabilized
de
voltages
+15
V,
-15
V
and
+5
V
for
the
circuitrie.

2.2.
2-2
MEASURING PRINCIPLE, Figs. 1, 2, 3
The
measurement
principle
is
based
on
the
so-called
current
and
voltage
measurement
technique:
the
component
voltage
and
after
that
the
component
current
are
measured.
The
measured
values
are
con-
verted
to
binary
numbers.
From
these
numbers
the
CPU
computes
the
CUT
parameter
of
interest.
According
to
the
front
panel
parameter
selection,
either
the
dominating
component
—resistance,
capa-
citance
or
inductance—
or
one
of
the
other
selectable
parameters
is
displayed.
Each
measurement
cycle
lasts
approx.
0.5
s.
it
comprises
5
single
measurements,
the
results
of
which
are
stored
in
the
microprocessor
data
memory,
a
subsequent
arithmetic
evaluation
and
a
final
transfer
of
the
result
to
the
display.
The
5
single
measurements
are
as
follows:
1. Reference measurement:
At
the
beginning
of
each
measurement
cycle
a
reference
measurement
is
performed,
with
the
input
of
the
programmable
amplifier
short-circuited,
caused
by
low
signal
at
pins
27,
28
of
the
microprocessor
309.
The
programmable
amplifier
is
set
to
gain
x.1.
After
a
delay
time
of
50
ms
for
each
of
the
5
single
measurements,
necessary
for
settling
of
the
zero
control
and
the
band-pass
filter
2,
a
measurement
without
1
kHz
signal
is
performed,
comprehending
all
failures
within
the
signal
path
from
FET
switch
328
to
the
A/D
converter.
The
counter
contents
of
the
A/D
conversion
at
the
end
of
this
measurement
serves
as
reference
for
the
subsequent
4
measurements.
2. 0° voltage measurement:
The voltage at the CUT is measured.
The switching phase of the phase sensitive rectifier is O°.
For
voltage
sensing
at
the
CUT
the
inputs
of
the
differential
amplifier
are
connected
via
the
V/\
selector,
FET
switch
324,
to
the
measurement
input.
This
is
achieved
by
low
signal
of
the
microprocessor
309.30.
The
0°
switching
phase
is
activated
by
low
signal
309.33.
The
gain
of
the
programmable
amplifier
is
set
to
x.1.
After
5
ms
settling
time
for
the
1
kHz
signal
amplitude
the
output
of
the
level
detector
is
sensed,
INT,
309.6.
If
no
overrange
is
detected
—correct
for
the
100
kQ
resistor
in
our
example—
the
gain
is
set
to
x1;
the
level
detector
is
sensed
again.
As
now
overrange
is
detected
the
gain
is
set
back
to
x.land
anA/D
conversion
is
started,
309.31.
For
low-ohmic
CUTs
the
gain
is
set
to
maximum
gain
x10
and,
if
no
overrange
is
detected,
the
measurement
is
performed.
3. 90° voltage measurement:
The voltage at the CUT is measured.
The switching phase of the phase sensitive rectifier is 90°.
The
gain
of
the
programmable
amplifier
is
not
altered
with
respect
to
the
0°
voltage
measurement.
An
A/D
conversion
is
performed.
4. 0° current measurement:
The
inputs
of
the
differential
amplifier
are
switched
over
to
the
output
of
the
current
to
voltage
conver-
ter.
;
The current through the CUT is measured.
The switching phase of the phase sensitive rectifier is 0°.
The gain of the programmable amplifier is set to.x.1 and, as for voltage measurement, increased to x1
with regard to the level detector. Next, if necessary, the conversion coefficient of the I/V converter
is increased from x1 to x10 (high at 309.30) and —as valid for our example with a 100 k& resistor—
the gain of the programmable amplifier is increased to x10 and set back to x1 after overrange detection.
An A/D conversion is performed.
For low-ohmic components a slightly different sequence is performed: If for voltage measurement
the gain was set to x1 or x10, the impedance is in any case very low, resulting in maximum current to
flow. The current measurement is performed at gain x.1 without trial for gain changing.

5. 90° current measurement:
The current through the CUT is measured.
The switching phase of the phase sensitive rectifier is 90°.
The
gain
of
the
programmable
amplifier
is
not
altered.
A
final
A/D
conversion
is
performed.
At
the
end
of
the
5
single
measurements
the
5
corresponding
binary
numbers
of
the
A/D
conversions
and
the
assigned
gain
factors
are
stored
in
the
microprocessor
data
memory.
From
this
the
micropro-
cessor
first
calculates
the
equivalent
series
resistance
Rs,
the
equivalent
series
reactance
Xs
and
the
quality
factor
Q
=
Xs/Rs
of
the
CUT.
In
the
RCL
AUTO
mode
the
microprocessor
determines
the
dominant
component,
either
Rs
resp.
Rp,
Cp
or
Ls,
calculates
its
value,
dimension
and
equivalent-
circuit
symbol
by
arithmetic
routines
and
transfers
the
result
to
the
display.
If
one
of
the
8
other
para-
meters
is
selected
by
the
step
keys
this
parameter
is
calculated
and
displayed.
After
that
the
micropro-
cessor
starts
the
next
measurement
cycle
with
the
single
measurement
routines.
For
fault
finding
the
5
single
measurements
can
statically
be
controlled,
performed
by
the
diagnostic
program,
see
chapter
3.14.
= 0°/90° VII gain delay time A/D con- storage in
selection setting 50 ms version data memory
Fig. 1 One single measurement
Xs, Rs, Q data for-
computation parameter value matting
& averaging verification computation & transfer to
displa
Fig. 2 One measurement cycle (ca. 0.5 s)

phase
selector
90°
416 MHz frequency band-pass
crystal divider filter 1
clock TkHz 1 kHz
GUARD
8 MHz 1/select ¥ 17 DC bias
to CPU on /off
+15V -15V +5V
power
supply
6) Cs (2V BIAS)
4 LED
control
1 U2 parameter
selection
CPU
central processing unit
L___-4 @ RcLauTo
-
t
| a display
curr. to volt. band-pass 33] csbay
converter
fitter
2
sensitive
pie
&
=U
pF
\
ei,
ee
x1
/x1/x10
1kHz
rectifier
U2
83
u2
|
|
|
843
34
clock,
load,
-~@
RCL
AUTO
a
—
level
QQ
|
1
gain,
detector
11—~
data
from
®
0
4
1
inhibit
for
counter
=
SENSE
|
—
+
SENSE
&
Rp
;
;
BIAS
ref.
meas.
-
overrange
5
|
carry
from
QRs
i!
|
counter,
end
S
jit
'
2
of
integr.
OZ
L—-
asc
;
©
Cp
or
Lp
|
integration
®Cs
ork
component
under
test
start
/reset
S
rks
{
|
t
t
{
1
POWER} - -/-- = 4 A step up
Sane @ TRIM hee Sa -\ v step down
Fig. 3 Block diagram
Le
PM 6303 REL m BHILIPS
Fig. 4 Front view

3.1.
CIRCUIT DESCRIPTION, FAULT FINDING
CRYSTAL
CLOCK,
FREQUENCY
DIVIDER,
PHASE
SELECTOR
The
accuracy
of
the
16
MHz
clock
frequency
is
moderate,
+5-
10°75.
So
fixed
load
capacitances
506,
504
are
inserted;
they
nevertheless
may
be
altered
in
test,
if
necessary.
The
output
of
the
oscillator
is
decoup-
led
by
inverter
307/2.
307/1
feeds
the
16
MHz
count
pulses
for
the
analog
to
digital
converter
ADC.
The
first
divider
stage
of
the
4-bit
binary
counter
308
generates
the
8
MHz
clock
pulse
for
the
micro-
processor.
Its
last stage
feeds
1 MHz
to
the
frequency
divider
chain.
1C
306
comprises
two
4-bit
BCD
counters,
the
5
:
1
division
of
which
is
used
for
dividing
the
frequency
down
to
40
kHz.
Further
division
by
10
results
in
a
4
kHz
signal
at
output
304.9,
the
basic
frequency
for
generation
of
the
1
kHz
signals
with
different
phase
relations,
see
fig.
5
.
The
trailing
(high
to
low)
edges
trigger
the
J—K
flipflops
303,
302.
The
1
kHz
signal,
phase
0°,
is
fed
to
the
band-pass
filter
1.
At
the
output
4
of
the
multiplexer
301
a
0°
or
90°
signal
is
available,
selected
(‘select
y’)
by
the
microprocessor.
At
output
7
a
signal
shifted
by
90°
with
relation
to
pin
4
is
available
for
synchronisation
of
the
analog
to
digital
converter
ADC.
eV
ee
ee
ae
fr
|
!
| | |
SOG
tee
ee
ee
| { |
| | |
G2
aes
el
ee
|
|
302/15
Sima
sete
re
i
eer
1
kHz
{
|
{
|
|
302/1.6
a
he
i
|
Ce
ee
ereearaa
(Se
Sane
——w}
250s
|
ego
Ims
Fig.5 Generation of the 1 kHz signals

3.2.
3-2
COMPONENT CONNECTION, BUFFER, INVERTING AMPLIFIER
The recommandations in the operating manual, chapter 3.4, are valid for service operations too. For
understanding the measurement of various types of components with respect to possibile faults of the
instrument and its accuracy, APPENDIX 1 of the operating manual —Algorithms in PM 6303, Phasor ©
Diagrams of Various CUT Types— can be helpful. In general influences by: series or parallel resistances
implemented in the input/output circuitries of the CUT connections with respect to 2-wire or 4-wire
system must be taken into account. Fig. 6 shows the network for 4-wire connection of a pure ohmic
component.
buffer V/ I
selector
test voltage differential
amplifier
amplifier
component under test
Fig. 6 Detailed circuitry for 4-wire CUT connection
Depending on measuring either high-ohmic or low-ohmic components this figure can be simplified. The
contact resistance at the sockets may approx. be 50 mQ2.
The 2 V measurement voltage is fed to the ‘’"—’’ socket, sensed at the appropriate SENSE socket. The
current flows through the CUT to socket ’’+”’ and its voltage at the low end is sensed. For 2-wire measu-
rement of high-ohmic components the appropriate sense and drive sockets are interconnected by resi-
stors 643 and 647.
The Guard socket is internally connected to measurement earth. The impedances between the 4 other
sockets and Guard are of minor importance: currents leaking off at the driving side are not measured.
At the current sink the voltage is virtual zero; so no current is leaking off.
In a 2-wire system the impedance at the “sense—’’ socket with respect to Guard must be taken
into account, but it is of no importance, if it is > 100 kQ, so not acting as voltage divider with the
100 {2 resistor R643.
The buffer amplifier 321 serves for impedance conversion from high-ohmic sensing the measurement
voltage to further signal processing. The signal is ac coupled (C531) in order to suppress the de voltage
in Cs Bias mode.
The inverting amplifier 322 shifts the phase of the buffer output voltage by 180°. So the current through
C532 is able to compensate a capacitive portion of the measurement current. The output amplitude
of the amplifier is adjustable by potmeter 638, in order to compensate the zero capacitance (no compo-
nent connected) of the CUT connections or of different adapters and cables.

3.3.
3.4,
3.5.
3.6.
3.7.
3-3
CURRENT TO VOLTAGE CONVERTER
The
I/V
converter,
1C
323,
converts
the
CUT
current
into
a
proportional
output
voltage.
Differential
sensing
the
current
at
the
feed-back
resistor
651
or
652
allows
measurement
of
low
impedances
down
to
1
m&.
FET
switch
319/1
switches
the
conversion
coefficient
(gain),
x1
or
x10,
by
selecting
feed-back
resistor
651
or
652.
The
tolerance
of
these
resistors
must
be
0.05
%,
as
it
directly
influences
the
measu-
rement
accuracy
of
the
instrument.
By
separate
switching
the
current
path
and
the
voltage
sensing
at
the
resistors
the
on-resistances
of
the
FET
switches
are
eliminated.
Resistor
653
and
Z-diodes
406,
407
limit
the
amplitude
at
input
4
of
the
FET
switch
to
+5
V.
Voltages
above
+5.5
V
will
destroy
the
switch!
PROGRAMMABLE AMPLIFIER
In the inverting amplifier 327 feed-back resistors are switched. FET switch 328 selects the resistors 661,
662 or 663 for gain setting x0.1, x1 or x10 depending on the impedance of the CUT. As voltage and
current measurements as well are performed by the programmable amplifier, the absolute gain accuracy
is of no importance; only the accuracy of the gain factors x10 between the 3 gain settings are important;
so the resistors mentioned have accuracies of 0.05 %.
Capacitors
539,
540,
541
are
paralied
to
the
resistors
in
order
to
achieve
equal
bandwidths
and
so
equal
phase
errors
for the 3
gain
settings.
2-pole
switching
of
the
feed-back
resistors
eliminates
the
on-resistances
of
the
FET
switch.
Via
the
upper
switch
contacts
the
high-ohmic
input
of IC
329
senses
the
voltage
at
the
feed-back
resistors.
Selecting
the
different
gains
is
done
at
inputs
9
an
10
of
IC
328,
binary
coded,
controlled
by
ports
P10,
P11
of
the
microprocessor.
For
the
reference
measurement
within
the
measurement
cycle,
code
00,
the
input
of
329
is
set
to
ground. Codes
01
to
11
correspond
to
the
gains
x0.1 to
x10.
The
BAND—PASS
FILTER
2
suppresses
hum
interference
coupled
into
the
CUT
and
reduces
the
harmo-
nic
components
of
the
1
kHz
signal.
The
gain
at
1
kHz
is
0.98.
The
damping
is
about
29
dB
at
100
Hz
and 17 dB
at
3
kHz.
The
LEVEL
DETECTOR
comprises
the
comparator
332
and
the
retriggerable
monostable
multivibrator
(flip-flop)
333.
if
the
positive
peak
value
of
the
measurement
signal
exceeds
the
reference
value
of
2.8
V,
preset
by
voltage
divider
674,
676,
the
output
of
the
comparator
generates
pulses
with
1
kHz
repetition
frequency,
which
trigger
the
flip-flop.
As
the
duration
of
the
output
pulse
is
determined
by
the
timing
components
R678
and
C546
to
ca.
2
ms,
the
output
9
is
set
to
low,
as
long
as
the
comparator
detects
overrange
(retrigger
function
of
the
flip-flop).
The
microprocessor
309
detects
the
overrange
signal
at
the
INT
input
—used
as
normal
input
port—
and
switches
the
programmable
amplifier
to
a
lower
gain
factor,
ports
P10,
P11.
The PHASE SENSITIVE RECTIFIER resolves the CUT voitages into components along the two referen-
ce phases and converts them to dc voltages. It is essentially an on/off switch for the CUT voltage Vm.
Without input voltage Vm, i.e. during the reference measurement, 1 kHz pulses of about 4.4 Vop are
available at the output of buffer 335.6. The pulse amplitude and rise and fal! times must be stable for
at least one measurement cycle, achieved by differential switch 364/365 and reference diode 414. The
phase of the switching pulses in relation to the test voltage is selectable to 0° and 90° by ‘select y’,
IC 301.1. The measurement voltage Vm at the input of the rectifier (330.6) is superimposed on the pul-
ses mentioned above only during the half cycle:
rf L_ 335.6 without Vm
Fo NS Vm only, e.g. in phase
| 335.6 with Vm
The maximum portion of Vm is +30 % with respect to the dc pulse amplitude, achieved by Vm = ca.
2 Veff being in-phase or anti-phase related to the switching signal.

ANALOG TO DIGITAL CONVERTER, ADC
The output from the phase sensitive rectifier is converted into digital data by a dual-slope analog to digi-
tal converter. The ADC comprises integrator 336, zero control 337, comparator 341, ADC control 338,
339 and a 19-bit counter. The latter is composed by the 11-bit counter 344, 345 and an 8-bit counter
within the microprocessor 309.
Oscilloscope drawings in Fig. 7 show one complete measurement cycle. Fig. 8 enlightens one conversion
period of the ADC within one of the single measurement cycles.
High signal of the microprocessor 309.31 prepares the conversion at t1. The time t2 - t1 may vary from
0 to 1 ms (1 pulse duration). The start pulse duration is 1.5 ms. The trailing edge of the 1 kHz signal
301.7 sets the output 338/1.5 high to start the integration at t2: the zero control is switched off and the
output of the phase sensitive rectifier is connected via FET switch 334/1 to the input of the integrator.
This is done during the zero period of the measurement pulses..For this the 1 kHz signal shifted by
90° with reference to the switching phase of the phase sensitive rectifier is taken.
The integrator reference current, defined by resistors 702, 703, is equal! for integration (t2 to t4) and
de-integration (discharge slope, t4 to t5). The difference between input current, defined by measurement
voltage pulses and resistor 701, and the integrator reference current effects the output voltage of the
integrator to go in negative direction during integration. At t2 flip-flop 340 and counter 339 are activa-
ted. The flip-flop' divides the 1 kHz frequency by 2 feeding the down counter 339 which was preset
to 10. At t3, counter state 7, high signal 339.6 resets the 11-bit counter to zero. Low signal 339.7 resets
flip-flop 303/2 of the comparator enabled again at t4. At t4 the counter state is zero. At the trailing
edge of the 1 kHz signal the output 339.13 generates a short low pulse resetting 338/2 and so termina-
ting the integration and starting the de-integration. The integration period T1 = 20 ms comprises 20
1 kHz pulses; so zero- and time-symmetrica!l 50 Hz noise and its odd harmonics have no influence on
the measurement result.
When 338/2 is reset at t4, all 3 enable inputs at NAND gate 343 are high; so the 16 MHz count pulses
can pass to the 11- bit counter. The carry of the 11-bit counter toggles the 8-bit counter within the micro -~
processor, input 39.
At t5 the output voltage of the integrator crosses the zero level causing the comparator and the flip:
flop 303/2.9 to turn over to low. This signal ‘end of integration’ disables gate 343 to stop the 16 MHz
count pulses. The counter state at t5 is proportional to the integrator output voltage at t4 and conse.
quently to the measurement value. For reference measurement the integrator output is ca. 5 V at t4
resulting in T2 = ca. 15 ms, corresponding to 240.000 count pulses. The maximum counter state is ca.
475.000 * T2 = 29.7 ms, the minimum is ca. 5000 @ T2 = 0.3 ms. So for the measurement range ca.
+235.000 count pulses are available.
As the tilt of the de-integration is independent of the measurement value, the delay time between zero
crossing and comparator turn-over and so the increase of the counter state for every single measure
ment cycle is equal. So the difference of the counter states is not effected.
The output 303/2.9 of the comparator is sensed by the CPU at input 1. Low signal at t5, ‘end of integr a-
tion’, causes the CPU to store the 19-bit counter contents into the data memory. The CPU sends a
reset pulse at t6 preparing the circuitry for the next single measurement cycle: the zero control is
activated decreasing the integrator output voltage to zero. In the rest position the zero control has to
compensate the integrator reference curfent.

309.29
309.33
309, 27
309.28
309.30
309.6
TNT
308.3}
309, 32
330.6
335.6
336.6
3-5
reference
ae
hi
0°
voltage
reo
eee
meas
——»}«—
0°
current
meas:
90°
current
meas.—»|
ape
RUT,
i
Vv P| 4.4Vpp 5 .4Vppl
mo "| i EE us TE : ) a AA
Fig. 7 One complete measurement cycle (CUT = 100 k{2)
I
309.31 | stort
— 1
'
301.7 SU.
1 i 10 20 |
1.8
338/1
338/2,7 |
\
340.7 | | £ | J | | 1 |
1 | t
339.3
ikHz/90°
-L---
Qo nc.
| 1
339.2 ee am eee emmy eee eee ae: nec.
|
339.6
+
339.7 j
|
Moe
|
vse UNNI... ---
12.34 5|67
336.6
output r output
integrator | integrator
4
| po
|
|
I
|
303/2.9
343.6 |
309,32 reset
T1=20ms
ty tz t3 te 's t6
Fig. 8 One conversion period of the ADC

3.9.
3.10.
3-6
CENTRAL PROCESSING UNIT, CPU
In the circuit diagram you will notize a well-known standard circuitry with 8-bit microprocessor 8039,
address latch 74363 and 32 K program memory 2732. The 16 MHz clock frequency is divided by 2,
308.9, and anti-phase fed to the clock inputs of the microprocessor. via inverters 307. Ports P10 - 16
deliver the different control signals. Ports P24, 25 in combination with the read signal RD select the
tri-state input buffer for data transfer from the 11-bit counter and from the parameter selection on
unit 2. Port P26, DLEN, data latch enable, controls the display driver on unit 2; port P27, CLB, clock
burst, delivers the clock pulses for the serial data transmitted via P17. For the sequence of data transfer
from the microprocessor to the display driver and display see chapter 3.11.
PARAMETER SELECTION
The selected parameter is defined by the state of the 4-bit binary up/down counter 355 on unit 2.
The state is sensed by the microprocessor on unit 1 and evaluated for correct parameter display. The
most significant bit — at high level only at counter state 8, parameter Cs (2 V BIAS) — directly actuates
the FET switch 319/2 which switches on the 2 Vdc bias voltage. The appropriate LED is switched on by
the 1-of-10 active HIGH decoder 352 and the open-collector drivers 353, 354.
The 3 keys “RCL AUTO”, “A” (up) and ‘’w’’ (down) are setting the state of the bi-directional counter
355:
The RCL AUTO key sends high to the reset input thus resetting the counter. After POWER ON the RC
combination 753/593 resets the counter so defining the default mode RCL AUTO of the instrument.
Shortly pushing either the Aor W key effects changing the counter state by 1. Continuous stepping
at a rate of 2 steps per second in the marked direction is effected, when the keys are kept pushed.
The retriggerable monostable multivibrators (monoflops) 358/1 and /2 serve for debouncing the key
contacts. The keys connect the output of the astable multivibrator comprising 1C 357/1, 357/2, R760
and C798 to the inputs of the monoflops. The output pulse duration of the monoflop (ca. 60 ms) is
longer than the period of the multivibrator signal. Because of the retrigger function of the monoflops
the outputs 7 resp. 9 remain low as long as one key is kept pushed. Max. one pulse duration (ca. 60 ms)
after release of the key the output of the monoflop returns to its initial state.
IC 358/1 switches over, when one of the two keys A, Wis pushed; it generates count pulses via the
intermediate counter 356 for the up/down counter 355. The second monoflop 358/2 only switches
over, when the Akey is pushed; it defines the count direction of 355.
As long as the ‘pushed’ output 7 of 358/1 shows high level (initial state), the intermediate counter is
reset to zero. When one of the keys is pushed, the counter 356 starts counting, clocked by the astable
multivibrator. On leaving the counter state zero the carry output 7 (TC) turns high. This leading edge
triggers the counter 355. As long as the ‘pushed’ output is kept low, at every zero passage of the counter,
i.e. after every 16 clock periods of the multivibrator, the leading edge of the carry output TC changes
the state of the counter 355 by 1. If the signal ‘pushed’ is reset to high, the counter 356 is reset.
The up/down counter 355, a 4 bit binary counter as 356, selects 9 parameters. Limiting the courter
length is done by connecting the binary outputs 1 (pin 6) and 8 (pin 2) —high at transitions 8 to 9 and
0 to 15— via gate 357 to the load input 1. A short load pulse sets the counter to 0 or 8, dependingon
the ‘down’ signal at input 3. So the counter is continuously counting the 9 states in both directiorss.
The RC combinations R752/C595 and R751/C594 suppress unwanted load pulses during transiton
from 7 to 8 resp. 8 to 7, caused by counter 355.

3.11.
3-7
Liquid-crystal display, LCD
A
three-line
bus
structure
(CLB
(Clock
Burst),
DLEN,
DATA)
enables
serial
data
transfer
from
the
microprocessor
to
the
display
unit.
In
this
case
the
data
are
serially
transmitted
to
the
memory
of
the
LCD
duplex
driver
351/U2.
The
data
are
transmitted
to
the
driver
memory
351,
unit
2,
which
performs
a
word
format
check
for
2
correct
data
words.
After
that
they
are
transferred
to
the
display.
The
53
display
segments
operate
in
duplex
mode,
i.e.
two
groups
of
seqments
are
assigned
to
one
back-
plane
each.
A
segment
is
activated
by
HIGH
of
the
relevant
data
bit.
The
relation
of
the
data
bits
to
the
outputs
and
pins
of
the
driver
and
the
display
are
shown
in
figs.
9,
11,
DLEN
ie
Sone
a
ee
tpusy * [_
ne
CLB.
L
Poe
ee
ee
ee
ae
32
33
34
$35
test
leading
zero
at
pulse
DATA
_
bitno.
0
1
2
3
4
5
6
7
31
32
33
|
output
4
s1
$2
$83
S4 S5
S6
S7
$31
$32
}
|
leading
zero
load
bit
H
$1...
$32
old
information
x
new
inform.
L
|
Fig.
9
Data
format
microprocessor
(unit
1)/display
driver
(351,
unit
2)
The
clock
oscillator
with
the
RC
combination
R761/C599
and
frequency
divider
generate
the
duplex
signals
BP1/BP2,
f.cb
~
80
Hz.
The
single
segments
are
connected
between
the
outputs
$1
...
$32
and
backplane
BP1
or
BP2
resp.
For
a
segment
output
Sx
fig.
10
shows
the
possibie
control
states.
Because
of
the
slow
data
transfer
a
storage
oscilloscope
is
recommended
for
checking
the
display.
Fig. 10 Timing diagram display

38
Indication
LCD
driver
Display
iC
351
Mae
a
kee
$32
5
31
6
=
d1
‘
LSD
——Digit1
{|
=~
30
7
53
«|
ft
al
29
8
27
e1
gl
28
9
56
|
DPI
b2
—
Digit2}
27
10
24
|
d2
c2
f
|
|
b
26
1
59
|
f2
a2
ae
25
12
21.
|
e2
g2
‘
|
[:
S24
13
62
|
pp2
b3
DPe
=
23
14
18
|
d3
c3
Si
inat
RMU
toe
15
65
«(|
43
a3
Segment
designatio
31
16
15
23
33
20
17
67
|
DP3
b4
oe
19
18 13
|d4
c4
MSD
Digit4]
4g
19
70
«1
#4
a4
7
20
10
|e4
g4
Equivalent
circuit
S16
21
78(2)
|
BAR7
Lee
=
15
22
3
BAR6
=
=
soe
14
23
4
BARS
Sm
=
13
24
76(5)
|
BAR1+2|
—4R—
-
7
12
25
74(6)
|
BAR3
asl
-
pe
11
26
73(7)
|
BAR8
eS
eg
=
10
27
72(8)
|
BAR4
=a
=
9
28
9
DP4*
oe
Dimension
$8
29
33
Sym
F
2
sym.
G
n
7
30 48
Sym
E
r
sym.
A
M
i
6
31
35
Sym
H
I"
sym.
J
Pe
D
Mk
(2
5
32
47
|SymL
L,
sym.B)
4
33
37
Sym
N
f
sym.
R
F
3
34
38
=|
SymP
4
sym.
D
Q
ris
Fy
2
35
45
Sym
M
<
sym.
C
<a
1
36
cs
BP2
37
40/41
BP1
38
1/80
“used only during initial test
Fig.11 Details of the display circuitry

Checking the data flow
By means of the signature analysis (CRC: Cyclical Redundancy Code) applying the
PHILIPS PM 2544 logic multimeter or HP 5005A/5004A signature multimeter the serial data flow
from microprocessor to display unit, but for backplane 1 only. The timing diagram of the transfer
process is shown in fig. 12.
The following settings are required:
- PM 6303: select parameter Q
- PM 6303: connect metal! film resistor 1 kQ ... 2 kQ to the test fixture
- PM 6303: correct display must show ~7—_} 0.000
- set logic (signature) multimeter to SIGNATURE NORMAL, trigger level: L *08V H220V
— connect logic multimeter to uP 8039/unit 1
logic multimeter PM 6303/U1
Timing POD
CLOCK ~*®_ _ CLOCK clock burst 38 (P27)
START _#/— =. “START DLEN 37 (P26)
STOP ~*®_ _ STOP DLEN 37 (P26)
GROUND LL Vss 20
Data probe
34 (P17)
Logic Multimeter displays: 5 C 93
Data assigned to the 2 nd backplane of the display cannot be checked by this procedure.
|
int. 64 bit data 30 bit 23 bit
|
|
DLEN
309.37
:
<_—
BP1 BP2
| DATA 309.34
CLOCK BURST 309.38
| DLEN 309,37
(delayed time base)
CLOCK BURST 309.38
Pee een a ms (delayed time base}
: | 8us
hes 108 us =
Fig.12 Data transfer microprocessor /display unit

3.12.
3.13.
Power supply
Five voltages are generated by the power supply section:
+15 V and -15 V are stabilized by the four-terminal voltage regulators 346/347 and adjusted by pot-
meters 723/727. Z-diodes 403/404 provide +5 V and -5 V for the zero-symmetrical operation of the
FET analog switches 319, 324 and 328. The fixed +5 V supply voltage for the digital circuitries is
outputted by the three-terminal voltage regulator 348.
The measuring earth for the analog and the digital circuitries have separate paths on the p.c.b. They are
interconnected at the electrolytic capacitors 570, 573 and 579.
SELF-TEST PROGRAM, ERROR MESSAGES
For simple fault finding several test programs are realized in this instrument.
Moreover faults may be detected by other or conventional methods.
Generally the voltages of the power supply should be checked at first (see table checks and adjustments).
While the self-test routine is part of the normal program, the diagnostic program must be especially
activated by closing solder link D (see Fig. 17, Unit 1).
The self-test routine is performed immediately after POWER ON. It confirms correct operation of the
basic functions. For check of the display all segments of the decimal and dimension indications, decimal
points and the equivalent-circuit symbols are shown for 3 seconds.
If a malfunction is detected an error code EO ... E3 is shown in the display field for the numerical value.
In this case equivalent-circuit symbols are not shown.
malfunction
error code check position
RAM test uP 8039 HL (IC 309)
E1 measuring ranges programmable amplifier, level detector
E2 overflow counter of ADC ADC control, e.g. 1C338/1C339
E3 reference measurement analog signal path, 1C328 to 1C336

3.14. DIAGNOSTIC PROGRAM
The diagnostic program is activated by closing the solder bridge D (see Fig. 17, Unit 1).
After switching on the instrument all segments of the display are shown for about 3 seconds followed
by program 1, which is a display test in the default mode RCL AUTO. For selection of program 2-9
use
one
of
the
step
buttons.
test
program
parameter
display test
3.14.1.
Survey
of
diagnostic
program
O
RCL
AUTO
preselect range a
Details of the program are explained in chapter 3.14.2.
Z — Ref D
test
parameter
function
execution
:
Z—Vv,0°
program
|
setting
Z—Vv,90°
RCL
AUTO
|
display-test
display:
639
(7
3
°
equivalent-circuit
symbols
and
dimensions
are
controlled
Z—1,0
automatically
step-by-step
Z—1.90°
preselection
indication
of
the
measuring
ranges:
A,
b1
...
b6
preselect
range
measuring
range
FO/FI
Rp
Rs
z
CporLp
Cs orls
O
O
O
©
O
O
O
O
oa,
: é
Cs
(2V
BIAS)
the
last
indicated
measuring
range
is
selected
when
program 2 is left.
the
counter
contents
(16
MSB,
hexadecimal)
is
repeti-
tively
displayed
_
Note:
I,
=b,
i
=6
1.
measuring
range
A:
complete
measuring
cycle
and
display
of
the
selected
value
2.
measuring
range
b1
...
b6:
repetitive
single
measurement
of
the
selected
voltage
or
current
and
display
of
counter
contents
Fig.
13
Relation
test
program
—
parameter
indication
©
3
reference,
display
shows
6FO0
...
8500
measurement
4 voltage measure-
ment, phase 0°
5
voltage measure-
ment, phase 90°
displayed value depends on the CUT
6 current measure-
ment, phase 0°
7 Cp or Lp current measure-
te)
ment, phase 90 3.14.2. The single test programs
8
Cs
or
Ls
preselection
display
indication:
A,
b1
...
b6
.
:
mcasieine
lidentical
to:
test
orapran
2}
3.14.2.1
Program
1:
display
test;
parameter
selection:
RCL
AUTO.
ranges
The display field for the numerical value shows permanently 6303. Additionally 7 equivalent-circuit sym-
9
Cs
(2V
BIAS)
|
switch-over
display
shows
intermittent:
FO,
F1
bols
and
11
dimensions
are
displayed
one
after
another:
function
FO:
switch
over
to
program
1-8
—~y
F1:
switch
over
to
parameter
measuring
modes
except
Tt
{|
te
/
oom
/
Es
i
gow
/
aay
/
Ee)
/
Cs
(2V
BIAS),
values
are
displayed
decimal
Note:
the
last
indicated
measuring
range
A,
bi
-
b6
Q
/
kQ
/
MQ
/
pF
/
oF
/
BF
/
ome
/
wH
/
mH
/
H
/
&kH
selected
during
program
2 or
8
continuous
in
the
other
testprograms
and
parameter
measuring
modes.
:
Test
program
1
stops
when
one
of
the
step
buttons
is
pressed.