Phytec phycore i.mx7 User manual

A product of a PHYTEC Technology Holding company

PCM-061/phyCORE-i.MX7 System on Module
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© PHYTEC America L.L.C. 2017 2
In this manual are descriptions for copyrighted products that are not explicitly indicated as such. The absence of the
trademark (™) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents
and trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be entirely reliable. However, PHYTEC
America L.L.C. assumes no responsibility for any inaccuracies. PHYTEC America L.L.C. neither gives any guarantee nor
accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product.
PHYTEC America L.L.C. reserves the right to alter the information contained herein without prior notification and accepts
no responsibility for any damages which might result.
Additionally, PHYTEC America L.L.C. offers no guarantee nor accepts any liability for damages arising from the improper
usage or improper installation of the hardware or software. PHYTEC America L.L.C. further reserves the right to alter the
layout and/or design of the hardware without prior notification and accepts no liability for doing so.
© Copyright 2017 PHYTEC America L.L.C., Bainbridge Island, WA.
Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or
processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC America L.L.C.

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Table of Contents
Table of Contents................................................................................................................................................................ 3
List of Figures ...................................................................................................................................................................... 5
List of Tables ....................................................................................................................................................................... 6
Conventions, Abbreviations and Acronyms........................................................................................................................ 7
Preface ................................................................................................................................................................................ 9
1 Introduction .............................................................................................................................................................. 12
1.1 Block Diagram ................................................................................................................................................... 14
1.2 Component Placement Diagram....................................................................................................................... 15
2 Pin Description .......................................................................................................................................................... 17
3 Jumpers..................................................................................................................................................................... 25
4 Power ........................................................................................................................................................................ 27
4.1 Primary System Power (VCC_SOM) .................................................................................................................. 27
4.2 Power Mode Management ............................................................................................................................... 27
4.3 Power Management IC (U2).............................................................................................................................. 28
5 Real-Time Clock (RTC) ............................................................................................................................................... 31
5.1 i.MX7 RTC .......................................................................................................................................................... 31
5.2 External RTC ...................................................................................................................................................... 31
6 System Configuration and Booting ........................................................................................................................... 32
6.1 Boot Mode Pin Settings..................................................................................................................................... 32
6.2 Boot Device Selection ....................................................................................................................................... 32
6.3 Boot Device Configuration ................................................................................................................................ 33
7 System Memory ........................................................................................................................................................ 34
7.1 DDR3 SDRAM (U3, U4) ...................................................................................................................................... 34
7.2 eMMC (U5) and NAND Flash (U6) Memory ...................................................................................................... 34
7.3 I2C EEPROM (U11) ............................................................................................................................................. 34
7.4 QSPI NOR Flash Memory (U9)........................................................................................................................... 35
7.5 Memory Model ................................................................................................................................................. 35
8 SD/MMC Card Interfaces .......................................................................................................................................... 36
9 Serial Interfaces......................................................................................................................................................... 37
9.1 USB .................................................................................................................................................................... 37
9.2 Ethernet ............................................................................................................................................................ 37
9.3 I2C ...................................................................................................................................................................... 38
9.4 PCI Express ........................................................................................................................................................ 38
10 Debug Interface..................................................................................................................................................... 39

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11 Technical Specifications ........................................................................................................................................ 40
12 Hints for Integrating and Handling the phyCORE-i.MX7....................................................................................... 42
12.1 Integrating the phyCORE-i.MX7 ........................................................................................................................ 42
12.2 Handling the phyCORE-i.MX7 ........................................................................................................................... 42
13 Revision History..................................................................................................................................................... 43

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List of Figures
Figure 1. phyCORE-i.MX7 Block Diagram ............................................................................................................................. 14
Figure 2. phyCORE-i.MX7 Component Placement (top view).............................................................................................. 15
Figure 3. phyCORE-i.MX7 Component Placement (bottom view) ........................................................................................ 16
Figure 4. Pinout of the phyCORE-Connector (top view, with cross section insert) ............................................................. 18
Figure 5. Jumper Numbering Schemes ................................................................................................................................ 25
Figure 6. Power Supply Diagram.......................................................................................................................................... 28
Figure 7. phyCORE-i.MX7 Mechanical Dimensions (profile view)........................................................................................ 40

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List of Tables
Table 1. Abbreviations and Acronyms used in this Manual................................................................................................... 8
Table 2. Types of Signals ........................................................................................................................................................ 8
Table 3. phyCORE-Connector (X1, X2) Pin-Out Description.................................................................................................. 19
Table 4. Jumper Descriptions and Settings ........................................................................................................................... 26
Table 5. External Supply Voltages ........................................................................................................................................ 29
Table 6. Internal Voltage Rails.............................................................................................................................................. 29
Table 7. Typical VBAT Power Consumption ......................................................................................................................... 31
Table 8. Boot Mode Configuration....................................................................................................................................... 32
Table 9. Boot Device Selection............................................................................................................................................. 32
Table 10. SD/MMC Boot Configuration Description ............................................................................................................ 33
Table 11. I2C1 Reserved Addresses ..................................................................................................................................... 38
Table 12. Technical Specifications........................................................................................................................................ 41
Table 13. Recommended Operating Conditions for the Input and Output Power Domains............................................... 41
Table 14. Revision History.................................................................................................................................................... 43

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Conventions, Abbreviations and Acronyms
This hardware manual describes the PCM-061 System on Module, also referred to as phyCORE-i.MX7. The manual
specifies the phyCORE-i.MX7's design and function. Precise specifications for the NXP i.MX7 microcontrollers can be found
in NXP's i.MX7 Data Sheet and Technical Reference Manual.
NOTE:
The BSP delivered with the phyCORE-i.MX7 usually includes drivers and/or software for controlling all components
such as interfaces, memory, etc.. Therefore programming close to hardware at register level is not necessary in most
cases. For this reason, this manual contains no detailed description of the controller's registers, or information relevant
for software development. Please refer to the i.MX7 Reference Manual if such information is required.
Conventions
The conventions used in this manual are as follows:
•Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of
the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven
low, or are driving low.
•A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
•The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct
value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete
address byte. E.g. given address in this manual 0x41 => complete address byte = 0x83 to read from the device and
0x82 to write to the device.
•Tables which describe jumper settings show the default position in bold text
•Text in blue italic indicates a hyperlink within, or external to the document. Click these links to quickly jump to the
applicable URL, part, chapter, table, or figure.
•References made to the phyCORE-Connector always refer to the high density Samtec connectors on the
undersides of the phyCORE-i.MX7

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Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms
used in this document.
Table 1. Abbreviations and Acronyms used in this Manual
Abbreviation
Definition
BSP
Board Support Package - Software delivered with the Development Kit including an operating system
(Linux) preinstalled on the module and Development Tools.
CB
Carrier Board - Used in reference to the phyCORE-i.MX7 Development Kit Carrier Board.
EMI
Electromagnetic interference
GPIO
General purpose input and output
J
Solder jumper - These types of jumpers require solder equipment to remove and place
PCB
Printed circuit board
PMIC
Power management IC
POR
Power-on reset
RTC
Real-time clock
SMT
Surface mount technology
SOM
System on Module - Used in reference to the PCM-061 / phyCORE-i.MX7 System on Module
VBAT
SOM standby voltage input
Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to
specify each type of signal.
Table 2. Types of Signals
Type of Signal
Description
Abbr.
Power
Supply voltage
PWR
Ref-Voltage
Reference voltage
REF
USB-Power
USB voltage
USB
Input
Digital input
IN
Output
Digital output
OUT
Input with pull up
Input with pull-up, must only be connected to GND (jumper or open-collector
output).
IPU
Input / output
Bidirectional input / output
IO
5V Input with pulldown
5V tolerant input with pull-down
5V_PD
5V Input with pull-up
5V tolerant input with pull-up
5V_PU
3.3V Input with
Pull-up
3.3V tolerant input with pull-up
3V3_PU
3.3V Input with pull-down
3.3V tolerant input with pull-down
3V3_PD
LVDS
Differential line pairs 100 Ohm LVDS
LVDS
Differential 90 Ohm
Differential line pairs 90 Ohm
DIFF90
Differential 100 Ohm
Differential line pairs 100 Ohm
DIFF100
Analog
Analog input or output
Analog

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Preface
This phyCORE-i.MX7 Hardware Manual describes the System on Module's design and functions. Precise specifications for
the NXP i.MX7 processor can be found in the processor datasheet and/or technical reference manual (TRM).
Ordering Information
The part numbering of the phyCORE-i.MX7 has the following structure
1
:
1
This structure shows the ordering options available as of the printing of this manual. Additional ordering options may have been
added. Please contact our sales team to check current availability, inventory, and lead-time.

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Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE-i.MX7 System On Module
PHYTEC System on Modules (SOMs) are designed for installation in electrical appliances or, combined with the PHYTEC
Carrier Board, can be used as dedicated Evaluation Boards (for use as a test and prototype platform for hardware/software
development) in laboratory environments.
CAUTION:
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only be unpacked,
handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD-
dangers. It is also necessary that only appropriately trained personnel (such as electricians, technicians and engineers)
handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3m.
PHYTEC products fulfill the norms of the European Union's Directive for Electro Magnetic Conformity only in accordance
to the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row
connectors, power connector and serial interface to a host-PC).
NOTE:
Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC
products, is subject to renewed establishment of conformity to, and certification of, Electro Magnetic Directives. Users
should ensure conformance following any modifications to the products as well as implementation of the products into
target systems.
The phyCORE-i.MX7 is one of a series of PHYTEC System on Modules that can be populated with different controllers and,
hence, offers various functions and configurations. PHYTEC supports a variety of 8-/16- and 32-bit controllers in two ways:
1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform.
2. As insert-ready, fully functional phyCORE OEM modules, which can be embedded directly into the user's
peripheral hardware design.
Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows you to focus on
hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore,
much of the value of the phyCORE module lies in its layout and test.
Production-ready Board Support Packages (BSPs) and Design Services for our hardware further reduce development time
and expenses. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid
substantial design issues and risks. For more information go to: http://phytec.com/contact/

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Product Change Management
In addition to our HW and SW offerings, the buyer will receive a free obsolescence maintenance service for the HW
provided when purchasing a PHYTEC SOM.
Our Product Change Management Team of developers is continuously processing all incoming PCN's (Product Change
Notifications) from vendors and distributors concerning parts which are being used in our products. Possible impacts to
the functionality of our products, due to changes of functionality or obsolesce of a certain part, are evaluated in order to
take the right measures in purchasing or within our HW/SW design.
Our general philosophy here is: We never discontinue a product as long as there is demand for it. Therefore, a set of
methods has been established to fulfill our philosophy:
Avoidance Strategies
•Avoid changes by evaluating longevity of a parts during design-in phase.
•Ensure availability of equivalent second source parts.
•Maintain close contact with part vendors for awareness of roadmap strategies.
Change Management in Case of Functional Changes
•Avoid impacts on Product functionality by choosing equivalent replacement parts.
•Avoid impacts on Product functionality by compensating changes through HW redesign or backward compatibility
SW Maintenance
•Provide early change notifications concerning functional relevant changes of our Products.
Change Management in Rare Event of an Obsolete and Non-Replaceable Part
•Ensure long term availability by stocking parts through last time buy management, according to product forecasts.
•Offer long term frame contract to customers.
We refrain from providing detailed, part-specific information within this manual, which is subject to changes, due to
ongoing part maintenance for our products.

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1Introduction
The phyCORE-i.MX7 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the
continuous development of PHYTEC System on Module technology. Like its mini-, micro- and nanoMODULE predecessors,
the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in
a manner that ensures their easy expansion and embedding in peripheral hardware development.
Independent research indicates that approximately 70% of all EMI (Electro Magnetic Interference) problems stem from
insufficient supply voltage grounding of electronic components in high frequency environments. The phyCORE board
design features an increased pin package that allows dedication of approximately 20% of all connector pins on the
phyCORE boards to ground. This improves EMI and EMC characteristics, making it easier to design complex applications
meeting EMI and EMC guidelines using phyCORE boards in high noise environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the
complexity of the module, 0402-packaged SMD components and laser-drilled microvias are implemented, providing
phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.
The phyCORE-i.MX7 is a subminiature (41 mm x 50 mm) insert-ready System on Module populated with the NXP i.MX7
microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals
and ports extend from the controller to high-density pitch (0.5 mm) connectors aligning two sides of the board, allowing
it to be inserted like a "big chip" into a target application.
Precise specifications for the controller populating the board can be found in the applicable controller Technical Reference
Manual or datasheet. The descriptions in this manual are based on the NXP i.MX7. A description of compatible
microcontroller derivative functions is not included, as such functions are not relevant for the basic functioning of the
phyCORE-i.MX7.
The phyCORE-i.MX7 offers the following features:
•Insert-ready, sub-miniature (41 mm x 50 mm) System on Module (SOM) subassembly in low EMI design, achieved
through advanced SMD technology
•Populated with the NXP i.MX7 microcontroller (12 x 12 mm, 0.4 mm Pitch BGA)
•Single or Dual ARM® Cortex™-A7 at max. 1 GHz clock frequency
•ARM® Cortex™-M4 at max. 266MHz
•On-board power management IC with integrated RTC
•Ultra-low power off-chip RTC
•Boot from SD, eMMC, NAND Flash, or QSPI Flash
•Up to 2 GB DDR3/3L
•Up to 8 GB NAND or 128 GB eMMC
•4 KB EEPROM
•16 MB QSPI NOR
•2x HighSpeed USB 2.0 OTG with integrated HS USB PHY
•High-Speed USB 2.0 host with integrated HSIC (High-Speed Inter-Chip USB PHY)
•1x gigabit Ethernet interface with on SOM Ethernet PHY allowing for direct connection to an Ethernet network
•1x gigabit Ethernet interface at TTL-level; available at the phyCORE connector
•4x I2C
•24-bit parallel LCD Display

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•6x UART
2
•2x eCSPI2
•3x SDIO/SD/MMC
•2x CAN
•PCI Express 2.0 (1 Lane)
•MIPI CSI (2 Lane)
•MIPI DSI (2 Lane)
•4x ADC
•3x Tamper
•3x PWM2
•1x SAI2
•1x QSPI
•Keypad (3x3)2
•JTAG
•GPIO
2
Highly multiplexed. All ports may not be available at once depending on use case.

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1.1 Block Diagram
Figure 1. phyCORE-i.MX7 Block Diagram

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1.2 Component Placement Diagram
Figure 2. phyCORE-i.MX7 Component Placement (top view)
3
3
Detailed component placement diagrams with all reference designators are available through our website

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Figure 3. phyCORE-i.MX7 Component Placement (bottom view)3

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2Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or current. Maximum signal
input values are indicated in the corresponding controller manuals/data sheets. As damage from improper connections
varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that
the module connections are protected from overloading through connected peripherals.
All controller signals extend to surface mount technology (SMT) connectors (0.5 mm) lining two sides of the module
(referred to as the phyCORE-Connector). This allows the phyCORE-i.MX7 to be inserted into any target application like a
"big chip".
The numbering scheme for the phyCORE-Connector is based on a two-dimensional matrix in which column positions are
identified by a letter and row position by a number. Pin A1, for example, is located in the lower right hand corner of the
matrix looking down through the top of the SOM. The pin numbering values decrease moving down on the board. Lettering
of the pin connector columns progresses alphabetically from right to left for each connector (refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-i.MX7 (viewed from above; phyCORE-Connector pointing down)
or with the socket of the corresponding phyCORE Carrier Board/user target circuitry. The lower right-hand corner of the
numbered matrix (pin A1) is thus covered with the corner of the phyCORE-i.MX7 marked with a triangle. The numbering
scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the
module.
The following figure illustrates the numbered matrix system. It shows a phyCORE-i.MX7 with SMT phyCORE Connectors
on its underside (defined with dotted lines) as it would be mounted on a Carrier Board. In order to facilitate understanding
of the pin assignment scheme, the diagram presents a cross-view of the phyCORE-module showing these phyCORE-
Connectors mounted on the underside of the module’s PCB.

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Figure 4. Pinout of the phyCORE-Connector (top view, with cross section insert)
Table 3 provides an overview of the pinout of the phyCORE-Connector with signal names and descriptions specific to the
phyCORE-i.MX7. It also provides the appropriate signal level interface voltages listed in the Level column, along with the
signal direction.
CAUTION:
Most of the controller pins have multiple multiplexed functions. Because most of these pins are connected directly to
the phyCORE-Connector the functions are also available at the connector. Signal names and descriptions in Table 3,
however, are in regard to the specification of the phyCORE-i.MX7 and the functions defined therein. Please refer to the
i.MX7 datasheet, or the schematic to learn about alternative functions. In order to utilize a specific pin's alternative
function the corresponding registers must be configured within the appropriate driver of the BSP. To support all
features of the phyCORE-i.MX7 Carrier Board a few changes have been made in the BSP delivered with the module.
The NXP i.MX7 is a multi-voltage operated microcontroller and as such special attention should be paid to the interface
voltage levels to avoid unintentional damage to the microcontroller and other on-board components. Please refer to the
NXP i.MX7 Reference Manual for details on the functions and features of controller signals and port pins.

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Table 3. phyCORE-Connector (X1, X2) Pin-Out Description
X1, Column A
Pin #
Signal
Type
Level
Description
A1
X_I2C1_SCL
IO
3.3V
I²C bus 1 clock
A2
X_I2C1_SDA
IO
3.3V
I²C bus 1 data
A3
X_I2C2_SCL
IO
3.3V
I²C bus 2 clock
A4
X_I2C2_SDA
IO
3.3V
I²C bus 2 data
A5
X_I2C3_SCL
IO
3.3V
I²C bus 3 clock
A6
X_I2C3_SDA
IO
3.3V
I²C bus 3 data
A7
GND
-
-
Ground
A8
X_JTAG_TMS
IN
3.3V
JTAG Test Mode Select
A9
X_JTAG_TDO
OUT
3.3V
JTAG Test Data Out
A10
X_JTAG_TDI
IN
3.3V
JTAG Test Data In
A11
X_JTAG_TCK
IN
3.3V
JTAG Test Clock
A12
X_JTAG_TRST_B
IN
3.3V
JTAG Test Reset
A13
X_SNVS_TAMPER0
IN
1.8V
Tamper Detection Pin 0
A14
X_SNVS_TAMPER1
IN
1.8V
Tamper Detection Pin 1
A15
GND
-
-
Ground
A16
X_CAN1_RX
IN
3.3V
CAN1 Receive
A17
X_CAN1_TX
OUT
3.3V
CAN1 Transmit
A18
X_CAN2_RX
IN
3.3V
CAN2 Receive
A19
X_CAN2_TX
OUT
3.3V
CAN2 Transmit
A20
GND
-
-
Ground
A21
X_UART6_RX
IN
3.3V
UART6 Receive
A22
X_UART6_TX
OUT
3.3V
UART6 Transmit
A23
X_UART5_RX
IN
3.3V
UART5 Receive
A24
X_UART5_TX
OUT
3.3V
UART5 Transmit
A25
GND
-
-
Ground
A26
X_NAND_CE1_B
OUT
3.3V
NAND Chip Enable 1
A27
X_NAND_CE0_B
OUT
3.3V
NAND Chip Enable 0
A28
X_NAND_DQS
IO
3.3V
NAND DQS Signal
A29
X_NAND_READY_B
IO
3.3V
NAND Ready Signal
A30
X_NAND_CE2_B
OUT
3.3V
NAND Chip Enable 2
A31
X_NAND_CE3_B
OUT
3.3V
NAND Chip Enable 3
A32
GND
-
-
Ground
A33
X_ADC_IN0
Analog
1.8V
Analog to Digital Converter Input Bit 0
A34
X_ADC_IN1
Analog
1.8V
Analog to Digital Converter Input Bit 1
A35
X_ADC_IN2
Analog
1.8V
Analog to Digital Converter Input Bit 2
A36
X_ADC_IN3
Analog
1.8V
Analog to Digital Converter Input Bit 3
A37
GND
-
-
Ground
A38
X_GPIO2_30
IO
3.3V
i.MX7 GPIO2_30
A39
X_GPIO2_10
IO
3.3V
i.MX7 GPIO2_10
A40
X_I2C4_SCL
IO
3.3V
I²C bus 4 clock
A41
X_I2C4_SDA
IO
3.3V
I²C bus 4 data
A42
X_GPIO2_11
IO
3.3V
i.MX7 GPIO2_11
A43
X_PWM3
OUT
3.3V
Pulse Width Modulation 3
A44
GND
-
-
Ground
A45
X_SD1_RESET_B
IO
3.3V
SD/MMC1 Reset

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X1, Column A
Pin #
Signal
Type
Level
Description
A46
X_SD1_CD_B
IN
3.3V
SD/MMC1 Card Detect
A47
X_SD1_WP
IN
3.3V
SD/MMC1 Write Protect
A48
X_SD1_CLK
IO
3.3V
SD/MMC1 Clock
A49
X_SD1_CMD
IO
3.3V
SD/MMC1 Command
A50
GND
-
-
Ground
A51
X_SD1_DATA0
IO
3.3V
SD/MMC1 Data 0
A52
X_SD1_DATA1
IO
3.3V
SD/MMC1 Data 1
A53
X_SD1_DATA2
IO
3.3V
SD/MMC1 Data 2
A54
X_SD1_DATA3
IO
3.3V
SD/MMC1 Data 3
A55
GND
-
-
Ground
A56
VCC_SOM
PWR
3.3V
3.3V Input Power
A57
VCC_SOM
PWR
3.3V
3.3V Input Power
A58
VCC_SOM
PWR
3.3V
3.3V Input Power
A59
VCC_SOM
PWR
3.3V
3.3V Input Power
A60
GND
-
-
Ground
X1, Column B
Pin #
Signal
Type
Level
Description
B1
X_GPIO2_12
IO
3.3V
i.MX7 GPIO2_12
B2
X_GPIO2_13
IO
3.3V
i.MX7 GPIO2_13
B3
X_GPIO2_14
IO
3.3V
i.MX7 GPIO2_14
B4
X_GPIO2_15
IO
3.3V
i.MX7 GPIO2_15
B5
GND
-
-
Ground
B6
X_MX7_ONOFF
IN
3V
i.MX7 ON/OFF Input (Drive using an open drain output)
B7
X_3V3MEM_EN
OUT
3.3V
External 3.3V Sequencing Output
B8
X_PMIC_PWRON
IN
3V
PMIC PWRON Input
B9
X_POR_B
OUT
3.3V
Power On Reset
B10
GND
-
-
Ground
B11
X_GPIO1_09
IO
3.3V
i.MX7 GPI1_09
B12
X_SNVS_TAMPER2
IN
1.8V
Tamper Detection Pin 2
B13
SW2_1V8
PWR
1.8V
1.8V Output
B14
GND
-
-
Ground
B15
X_UART1_RX
IN
3.3V
UART1 Receive
B16
X_UART1_TX
OUT
3.3V
UART1 Transmit
B17
X_UART2_RX
IN
3.3V
UART2 Receive
B18
X_UART2_TX
OUT
3.3V
UART2 Transmit
B19
X_UART3_RX
IN
3.3V
UART3 Receive
B20
X_UART3_TX
OUT
3.3V
UART3 Transmit
B21
GND
-
-
Ground
B22
X_PCIE_RX_N
DIFF100
-
PCIe Differential Negative Receive
B23
X_PCIE_RX_P
DIFF100
-
PCIe Differential Positive Receive
B24
GND
-
-
Ground
B25
X_PCIE_TX_P
DIFF100
-
PCIe Differential Positive Transmit
B26
X_PCIE_TX_N
DIFF100
-
PCIe Differential Negative Transmit
B27
GND
-
-
Ground
B28
X_PCIE_REFCLK_P
DIFF100
-
PCIe Differential Positive Reference Clock