Phytec phyCORE-XC161 User manual

A product of a PHYTEC Technology Holding company
phyCORE-XC161
Hardware Manual
Edition February 2004

phyCORE-XC161
PHYTEC Meßtechnik GmbH 2004 L-622e_4
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Meßtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Meßtechnik GmbH neither gives any
guarantee nor accepts any liability whatsoever for consequential damages resulting
from the use of this manual or its associated product. PHYTEC Meßtechnik
GmbH reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Meßtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Meßtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2004 PHYTEC Meßtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or in
part - are reserved. No reproduction may occur without the express written consent
from PHYTEC Meßtechnik GmbH.
EUROPA NORTH AMERICA
Adresse: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Angebots
Hotline: [phone] [e-mail] 1 [phone] [e-mail]
Technische
Hotline: [phone] [email protected] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Seite: http://www.phytec.de http://www.phytec.com
4th Edition February 2004

Table of Contents
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Preface ......................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................6
1.2 View of the phyCORE-XC161.....................................................7
2 Pin Description.....................................................................................9
3 Jumpers..............................................................................................17
3.1 J1, J2 A/D Reference Voltage ...................................................23
3.2 J3 Internal or External Program Memory..................................23
3.3 J4 SRAM U6/U7 Chip Select....................................................24
3.4 J5 SRAM Memory Size.............................................................24
3.5 J6 E²PROM/FRAM Supply Voltage .........................................25
3.6 J7 Write Protection of E²PROM /FRAM ..................................25
3.7 J8, J9 Address of the Serial E²PROM/ FRAM..........................26
3.8 J10 RS-232 Transceiver R1O TTL Output................................26
3.9 J11, J12, J15, J16 CAN Interfaces.............................................27
3.10 J13, J14, J17, J18 CAN Transceiver..........................................28
3.11 J19 RTC Interrupt Output..........................................................29
3.12 J20, J21 Configuration of P9.4 and P9.5 for I²C Bus................29
3.13 J22 RTC (U13) Clock Output....................................................30
3.14 J23, J24 First Serial Interface ....................................................30
3.15 J25, J26 Second Serial Interface................................................31
3.16 J27 Ethernet Controller Chip Select..........................................32
3.17 J28 Ethernet Controller /SBHE Configuration..........................32
3.18 J29 Ethernet Controller Sleep Mode..........................................33
3.19 J30 Ethernet Controller IRQ Signal...........................................33
3.20 J32 Write Protection of Flash....................................................34
4 System Configuration........................................................................35
4.1 System Startup Configuration.....................................................35
5 Memory Models.................................................................................39
5.1 Bus Cycle Phases........................................................................42
6 Serial Interfaces.................................................................................45
6.1 RS-232 Interface.........................................................................45
6.2 CAN Interface.............................................................................46
7 Real-Time Clock RTC-8564 (U13)...................................................47
8Serial E²PROM/FRAM (U8) ............................................................49
9 Flash Memory (U4)............................................................................51

phyCORE-XC161
PHYTEC Meßtechnik GmbH 2004 L-622e_4
10 Battery Buffer and Voltage Supervisor Chip (U9).........................52
11 CS8900A Ethernet Controller..........................................................53
11.1 Fundamentals..............................................................................53
11.2 Memory Mode............................................................................53
12 Debug Interface.................................................................................55
13 Technical Specifications....................................................................57
14 Hints for Handling the phyCORE-XC161......................................59
15 The phyCORE-XC161 on the phyCORE Development
Board HD200 XC ..............................................................................61
15.1 Concept of the phyCORE Development Board HD200.............61
15.2 Development Board HD200 XC Connectors and Jumpers........63
15.2.1 Connectors.....................................................................63
15.2.2 Jumpers on the phyCORE Development Board
HD200 XC.....................................................................65
15.2.3 Unsupported Features and Improper
Jumper Settings .............................................................67
15.3 Functional Components on the phyCORE Development
Board HD200 XC.......................................................................68
15.3.1 Power Supply at X1.......................................................69
15.3.2 Activating the Bootstrap Loader ...................................71
15.3.3 First Serial Interface at Socket P1A..............................73
15.3.4 Power Supply to External Devices via Socket P1A......75
15.3.5 Second Serial Interface at Socket P1B..........................77
15.3.6 First CAN Interface at Plug P2A...................................80
15.3.7 Second CAN Interface at Plug P2B ..............................86
15.3.8 Programmable LED D3.................................................91
15.3.9 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field...............................91
15.3.10 Battery Connector BAT1.............................................100
15.3.11 Releasing the /NMI Interrupt ......................................100
15.3.12 DS2401 Silicon Serial Number...................................100
15.3.13 Pin Header Connector X4 ...........................................101
15.3.14 JP40, S3 Multi-Purpose Push Button Configuration...102
16 Ethernet Port...................................................................................103
17 Revision History..............................................................................105
Index ..................................................................................................107

Table of Contents
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Index of Figures
Figure 1: Block Diagram phyCORE-XC161 ...............................................6
Figure 2: View of the phyCORE-XC161 (Top View).................................7
Figure 3: View of the phyCORE-XC161 (Bottom View)............................8
Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross
Section Insert).............................................................................11
Figure 5: Numbering of the Jumper Pads...................................................17
Figure 6: Location of the Jumpers (Controller Side) .................................17
Figure 7: Location of the Jumpers (Connector Side).................................18
Figure 8: Timing Phases for Multiplexed Bus Mode.................................40
Figure 9: Timing Phases for Demultiplexed Bus Mode.............................40
Figure 10: JTAG Interface (Top View) .......................................................55
Figure 11: JTAG Interface (Bottom View)..................................................56
Figure 12: Physical Dimensions...................................................................57
Figure 13: Modular Development and Expansion Board Concept with
the phyCORE-XC161.................................................................62
Figure 14: Location of Connectors on the phyCORE Development
Board HD200 XC.......................................................................63
Figure 15: Numbering of Jumper Pads ........................................................65
Figure 16: Location of the Jumpers (View of the Component Side)...........65
Figure 17: Default Jumper Settings of the phyCORE Development
Board HD200 XC with phyCORE-XC161.................................66
Figure 18: Connecting the Supply Voltage at X1 ........................................69
Figure 19: Pin Assignment of the DB-9 Socket P1A as First RS-232
(Front View) ...............................................................................73
Figure 20: Location of Components at U12 and U13 for Power Supply
to External Subassemblies..........................................................75
Figure 21: Pin Assignment of the DB-9 Socket P1B as Second
RS-232 (Front View).................................................................77
Figure 22: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on phyCORE-XC161, Front View) ............................................80

phyCORE-XC161
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Figure 23: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Development Board) .............................................................82
Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Development Board with Galvanic Separation)....................84
Figure 25: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on phyCORE-XC161) ................................................................86
Figure 26: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on phyCORE-XC161) ................................................................87
Figure 27: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Development Board with Galvanic Separation)....................90
Figure 28: Pin Assignment Scheme of the Expansion Bus..........................92
Figure 29: Pin Assignment Scheme of the Patch Field................................92
Figure 30: Pin Assignment Control Signals for the phyCORE-XC161 /
Development Board / Expansion Board.....................................97
Figure 31: Pin Assignment Power Supply for the phyCORE-XC161 /
Development Board / Expansion Board.....................................98
Figure 32: Unused Pins on the phyCORE-XC161 /
Development Board / Expansion Board.....................................99
Figure 33: JP28 Releasing the /NMI Interrupt..........................................100
Figure 34: JP19 Jumper Configuration for Silicon Serial
Number Chip............................................................................100
Figure 35: Connecting the DS2401 Silicon Serial Number.......................101
Figure 36: Pin Assignment of the DS2401 Silicon Serial Number............101
Figure 37: JP40 Multi-Purpose Push Button S3 Configuration................102
Figure 38: Ethernet Transformer Module Connector ................................103
Figure 39: Ethernet Transformer Connector Pinout ..................................103
Figure 40: Jumper for Ethernet Transformer Port .....................................104

Table of Contents
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Index of Tables
Table 1 Pinout of the phyCORE-Connector X1......................................15
Table 2: Jumper Settings...........................................................................22
Table 3: J1, J2 A/D Converter Reference Voltage ..................................23
Table 4: J3 Code Fetch Selection.............................................................23
Table 5: J4 SRAM U6/U7 Chip Select Configuration ............................24
Table 6: J5 SRAM U6/U7 Size Configuration........................................24
Table 7: J6 E²PROM Supply Voltage Configuration ..............................25
Table 8: J7 Write Protection of E²PROM/FRAM ...................................25
Table 9: J8, J9 E²PROM/FRAM Address Configuration ........................26
Table 10: J10 RS-232 Transceiver R1O TTL Output................................26
Table 11: J11, J12, J15, J16 CAN Interface Configuration.......................28
Table 12: J19 P2.11 / RTC Interrupt Configuration..................................29
Table 13: J20, J21 P9.4, P9.5 / I2C Bus Configuration..............................29
Table 14: J22 RTC Clock Output Configuration.......................................30
Table 15: J23, J24 First Serial Interface Configuration.............................31
Table 16: J25, J26 Second Serial Interface Configuration ........................31
Table 17: J27 Ethernet Controller Chip Select Configuration...................32
Table 18: J28 Ethernet Controller /SBHE Configuration..........................32
Table 19: J29 Ethernet Controller Sleep Mode Configuration..................33
Table 20: J30 Ethernet Controller IRQ Signal Configuration...................33
Table 21: J32 Write Protection of Flash....................................................34
Table 22: Functional Settings on Port P0 for System Startup
Configuration..............................................................................36
Table 23: System Startup Configuration Registers.....................................38
Table 24: Bus Timing Calculation Examples.............................................41
Table 25: Memory Device Options for U8.................................................49
Table 26: E²PROM/FRAM Write Protection .............................................49
Table 27: E²PROM/FRAM Address...........................................................50

phyCORE-XC161
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Table 28: Improper Jumper Setting for JP16 on the
Development Board....................................................................67
Table 29: Improper Jumper Setting for JP30/33 on the
Development Board....................................................................67
Table 30: JP9, JP16 Configuration of the Supply Voltages
VCC/VCC2 ................................................................................69
Table 31: JP9, JP16 Improper Jumper Settings for the Supply
Voltages......................................................................................70
Table 32: JP28 Configuration of the Boot Button.....................................71
Table 33: JP28 Configuration of a Permanent Bootstrap Loader Start.....72
Table 34: JP22, JP23, JP10 Configuration of Boot via RS-232................72
Table 35: Improper Jumper Settings for Boot via RS-232.........................72
Table 36: Jumper Configuration for the First RS-232 Interface ................73
Table 37: Improper Jumper Settings for DB-9 Socket P1A as
First RS-232 ...............................................................................74
Table 38: JP24 Power Supply to External Devices Connected to
P1A on the Development Board.................................................76
Table 39: Jumper Configuration for the Second RS-232 Interface............77
Table 40: Improper Jumper Settings for DB-9 Socket P1B
(2nd RS-232)................................................................................78
Table 41: Jumper Configuration of the DB-9 Socket P1B (no Second
RS-232) ......................................................................................78
Table 42: Improper Jumper Settings for DB-9 Socket P1B (no Second
RS-232) ......................................................................................79
Table 43: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the phyCORE-XC161........................................80
Table 44: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board.....................................81
Table 45: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on the Development Board)....................................82

Table of Contents
PHYTEC Meßtechnik GmbH 2004 L-622e_4
Table 46: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board with
Galvanic Separation....................................................................83
Table 47: JP39 CAN Bus Voltage Supply Reduction................................84
Table 48: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on Development Board with
Galvanic Separation) ..................................................................85
Table 49: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the phyCORE-XC161........................................86
Table 50: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Development Board.....................................87
Table 51: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on the Development Board)..................................88
Table 52: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Development Board with
Galvanic Separation....................................................................89
Table 53: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on Development Board with
Galvanic Separation) ..................................................................90
Table 54: JP17 Configuration of the Programmable LED D3...................91
Table 55: Pin Assignment Data/Address Bus for the
phyCORE-XC161 / Development Board /
Expansion Board.........................................................................93
Table 56: Pin Assignment Port P2, P3, P4 for the
phyCORE-XC161 / Development Board /
Expansion Board.........................................................................94
Table 57: Pin Assignment Port P5, P6, P7, P9 for the
phyCORE-XC161 / Development Board /
Expansion Board.........................................................................95
Table 58: Pin Assignment Interface Signals for the
phyCORE-XC161 / Development Board /
Expansion Board.........................................................................96

phyCORE-XC161
PHYTEC Meßtechnik GmbH 2004 L-622e_4

Preface
PHYTEC Meßtechnik GmbH 2004 L-622e_4 1
Preface
This phyCORE-XC161 Hardware Manual describes the board’s
design and functions. Precise specifications for Infineon’s XC161CJ
microcontroller series controller can be found in the enclosed
microcontroller Data Sheet/User's Manual. If software is included
please also refer to additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformity of the
PHYTEC phyCORE-XC161
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows or connectors are
longer than 3 meters.

phyCORE-XC161
2PHYTEC Meßtechnik GmbH 2004 L-622e_4
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header rows or connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-XC161 is one of a series of PHYTEC Single Board
Computers that can be populated with different controllers and,
hence, offers various functions and configurations. PHYTEC supports
all common 8- and 16-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
PHYTEC Meßtechnik GmbH 2004 L-622e_4 3
1Introduction
The phyCORE-XC161 belongs to PHYTEC’s phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and
EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.

phyCORE-XC161
4PHYTEC Meßtechnik GmbH 2004 L-622e_4
The phyCORE-XC161 is a subminiature (60 x 53 mm) insert-ready
Single Board Computer populated with Infineon’s XC161CJ
microcontroller. Its universal design enables its insertion in a wide
range of embedded applications. All controller signals and ports
extend from the controller to high-density pitch (0.635 mm)
connectors aligning two sides of the board, allowing it to be plugged
like a “big chip” into a target application.
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the Infineon XC161CJ. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-XC161.

Introduction
PHYTEC Meßtechnik GmbH 2004 L-622e_4 5
The phyCORE-XC161 offers the following features:
•subminiature Single Board Computer (60 x 53 mm) achieved
through modern SMD technology
•populated with the Infineon XC161CJ microcontroller (TQFP-144
packaging) featuring two on-chip 2.0B CAN modules
•improved interference safety achieved through multi-layer PCB
technology and dedicated Ground pins
•controller signals and ports extend to two 100-pin high-density
(0.635 mm) Molex connectors aligning two sides of the board,
enabling it to be plugged like a “big chip” into target application
•16-bit, demultiplexed bus mode
•20 – 40 MHz clock frequency (50 ns – 25 ns instruction cycle)
•16 MByte address space
•256 kByte to 2 MByte external Flash on-board1
•on-board Flash programming, no dedicated Flash programming
voltage required through use of 5 V Flash devices
•256 kByte to 1 MByte RAM on-board1
•512 kByte fast SRAM (15 ns access time) on-board1
•up to 21CAN interfaces with Philips 82C251 CAN transceiver, or
Infineon TLE6250
•I²C Real-Time Clock with internal quartz
•4 to 32 kByte I2C E²PROM1, or 512 Byte to 8 kByte FRAM1
•Voltage Supervisory Chip for Reset logic and power supervision
•free Chip Select signals for easy connection of peripheral devices2
•operates with two supply voltages, 5 V and 2.5 V / <220 mA
•RS-232 transceiver for two serial interfaces
•optional CS8900A 10Base-T Ethernet controller
1: Please contact PHYTEC for more information about additional modul configurations.
2: Number of available /CS signals depends on configuration of the phyCORE module.

phyCORE-XC161
6PHYTEC Meßtechnik GmbH 2004 L-622e_4
1.1 Block Diagram
INFINEON
XC161CJ
FLASH
256kB-2MB SRAM 15ns
512kB RAM 256kB-1MB ETHERNET CS8900A
RS-232
Transceiver
CAN
Transceiver
CAN
Transceiver
Reset
MAX690A E2PROM FRAM RTC8564 JTAG
Connector
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
I/O Ports
I²C Bus
JTAG Port
CAN1H/CAN1L
CAN0H/CAN0L
RxD0/TxD0
RxD1/TxD1
Data
Address
Reset
CAN1
CAN0
RxD1/TxD1
P0
RxD0/TxD0
I²C
Ports
opt.
JTAG Port
P1
Figure 1: Block Diagram phyCORE-XC161

Introduction
PHYTEC Meßtechnik GmbH 2004 L-622e_4 7
1.2 View of the phyCORE-XC161
Figure 2: View of the phyCORE-XC161 (Top View)

phyCORE-XC161
8PHYTEC Meßtechnik GmbH 2004 L-622e_4
Figure 3: View of the phyCORE-XC161 (Bottom View)

Pin Description
PHYTEC Meßtechnik GmbH 2004 L-622e_4 9
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user’s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector). This allows the
phyCORE-XC161 to be plugged into any target application like a "big
chip".
A new numbering scheme for the pins on the phyCORE-connector
has been introduced with the phyCORE specifications. This enables
quick and easy identification of desired pins and minimizes errors
when matching pins on the phyCORE module with the phyCORE-
connector on the appropriate PHYTEC Development Board or in user
target circuitry.
The numbering scheme for the phyCORE-connector is based on a two
dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin
connector rows progresses alphabetically from left to right
(refer to Figure 4).

phyCORE-XC161
10 PHYTEC Meßtechnik GmbH 2004 L-622e_4
The numbered matrix can be aligned with the
phyCORE-XC161 (viewed from above; phyCORE-connector pointing
down) or with the socket of the corresponding phyCORE
Development Board/user target circuitry. The upper left-hand corner
of the numbered matrix (pin 1A) is thus covered with the corner of the
phyCORE-XC161 marked with a white triangle. The numbering
scheme is always in relation to the PCB as viewed from above, even if
all connector contacts extend to the bottom of the module.
The numbering scheme is thus consistent for both the module’s
phyCORE-connector as well as mating connectors on the phyCORE
Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCORE-connector is usually assigned a
single designator for its position (X1 for example). In this manner the
phyCORE-connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socketed
connector. The location of row 1 on the board is marked by a white
triangle on the PCB to allow easy identification.