Phytec phyCORE-LPC2292/94 User manual

A product of a PHYTEC Technology Holding company
phyCORE-LPC2292/94
Hardware Manual
Edition July 2006

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark (™) and copyright (©) symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
©Copyright 2006 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
[email protected] 1 [phone] [email protected]
Technical
Support: [phone]
[email protected] 1 [phone] [email protected]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
5th Edition July 2006

Contents
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Preface...........................................................................................................1
1Introduction.........................................................................................3
1.1 Block Diagram .............................................................................6
1.2 View of the phyCORE-LPC2292/94 ...........................................7
2Pin Description....................................................................................9
3Jumpers..............................................................................................17
3.1 J200, J202 Second Serial Interface ...........................................24
3.2 J201, J203 First Serial Interface................................................25
3.3 J204 A/D Converter ..................................................................26
3.4 J205, J206 Chip Select Configuration.......................................26
3.5 J207 MCKO Signal...................................................................27
3.6 J208, J209 Flash Size Configuration.........................................28
3.7 J210, J211 RAM Size Configuration........................................29
3.8 J300 Flash Ready/Busy Configuration .....................................30
3.9 J301, J302 Flash Write Protection Configuration.....................31
3.10 J400, J401 SRAM Configuration..............................................32
3.11 J402 SRAM Supply Voltage.....................................................32
3.12 J500 through J509 Ethernet Controller SMSC
LAN91C111Configuration ........................................................33
3.13 J600, J601, J616 CAN Transceiver Configuration...................36
3.14 J602, J603, J604, J605 CAN Interfaces ....................................37
3.15 J606 Write Protection of SPI EEPROM ...................................38
3.16 J607 Watchdog Configuration ..................................................39
3.17 J608, J609, J610 I2C Interface...................................................40
3.18 J611, J612, J613, J614 SPI0 Interface ......................................40
3.19 J615 CAN Bus Level Configuration.........................................41
3.20 J616, J617 CAN Transceiver VCC, Pin 5.................................42
3.21 J618 VDD_V3V3 Supply Control............................................43
3.22 J619, J620 SPI Master/Slave Selection.....................................43
3.23 J621 WDI Signal Source...........................................................44
3.24 J622 RESET Signal Source.......................................................44
3.25 J800, J801 ETM/OCDS Connector Configuration
(Only with debugCORE-LPC2292/94)......................................45
3.26 C210 CLKIN Configuration ......................................................46
4System Configuration.......................................................................47
4.1 System Startup Configuration....................................................47
4.2 Starting the LPC2292/94 ISP Mode...........................................48
5Memory Models.................................................................................49

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5
6Serial Interfaces ................................................................................ 55
6.1 RS-232 Interfaces....................................................................... 55
6.2 CAN Interface............................................................................ 56
7Serial EEPROM (U607)...................................................................57
8On-Board Flash Memory (U300-U303)..........................................58
9LAN91C111 Ethernet Controller (U501)....................................... 59
9.1 MAC Address ............................................................................ 60
9.2 Ethernet EEPROM (U500)........................................................ 61
9.3 10/100Base-T Interface.............................................................. 61
10 Real-Time Clock RTC-8564 (U604)................................................62
11 Battery Buffer ................................................................................... 63
12 Debug Interface X701....................................................................... 65
13 debugCORE-LPC2292/94................................................................ 69
14 Technical Specifications...................................................................73
15 Hints for Handling the phyCORE-LPC2292/94............................75
16 The phyCORE-LPC2292/94 on the phyCORE Carrier
Board HD200....................................................................................77
16.1 Concept of the phyCORE Carrier Board HD200......................77
16.2 Carrier Board HD200 Connectors and Jumpers........................ 79
16.2.1 Connectors .................................................................... 79
16.2.2 Jumpers on the phyCORE Carrier Board HD200 ........81
16.2.3 Unsupported Features and Improper Jumper Settings..83
16.3 Functional Components on the phyCORE Carrier
Board HD200............................................................................. 84
16.3.1 Power Supply at X1...................................................... 84
16.3.2 Starting the ISP Command Handler .............................86
16.3.3 phyCROE-LPC2292/4 Boot Memory Configuration... 88
16.3.4 First Serial Interface at Socket P1A.............................. 89
16.3.5 Power Supply to External Devices via Socket P1A.....91
16.3.6 Second Serial Interface at Socket P1B ......................... 93
16.3.7 First CAN Interface at Plug P2A.................................. 95
16.3.8 Second CAN Interface at Plug P2B............................101
16.3.9 Programmable LED D3 ..............................................107
16.3.10 User Push Button S3...................................................107
16.3.11 Pin Assignment Summary of the phyCORE,
the Expansion Bus and the Patch Field....................... 108
16.3.12 Battery Connector BAT1............................................118
16.3.13 DS2401 Silicon Serial Number ..................................118
16.3.14 Pin Header Connector X4...........................................119

Contents
©PHYTEC Messtechnik GmbH 2006 L-658e_5
17 Ethernet Port...................................................................................121
18 Revision History..............................................................................123
19 Component Placement Diagram....................................................125
Index..........................................................................................................127

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Index of Figures
Figure 1: Block Diagram phyCORE-LPC2292/94................................... 6
Figure 2: Top View of the phyCORE-LPC2292/94 ................................. 7
Figure 3: Bottom View of the phyCORE-LPC2292................................. 8
Figure 4: Pinout of the phyCORE-Connector (Top View, with Cross
Section Insert).......................................................................... 11
Figure 5: Numbering of the Jumper Pads................................................ 17
Figure 6: Location of the Jumpers (Top View)....................................... 17
Figure 7: Location of the Jumpers (Bottom View)................................. 18
Figure 8: phyCORE-LPC2292/94 Memory Model ................................ 51
Figure 9: Ethernet Connection to LPC2292/94 Controller..................... 59
Figure 10: JTAG Interface (Top View)..................................................... 65
Figure 11: JTAG Interface (Bottom View)............................................... 66
Figure 12: debugCORE-LPC2292/94 (Top View)................................... 69
Figure 13: debugCORE-LPC2292/94 (Bottom View).............................. 70
Figure 14: Physical Dimensions................................................................ 73
Figure 15: Modular Development and Expansion Board Concept
with the phyCORE-LPC2292/94............................................. 78
Figure 16: Location of Connectors on the phyCORE Development
Board HD200........................................................................... 79
Figure 17: Numbering of Jumper Pads ..................................................... 81
Figure 18: Location of the Jumpers (View of the Component Side)........ 81
Figure 19: Default Jumper Settings of the phyCORE
Development Board HD200 with phyCORE-LPC2292/94 .... 82
Figure 20: Connecting the Supply Voltage at X1..................................... 85
Figure 21: Pin Assignment of the DB-9 Socket P1A as First RS-232
(Front View) ............................................................................ 89
Figure 22: Location of Components at U12 and U13 for Power
Supply to External Subassemblies........................................... 91

Contents
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Figure 23: Pin Assignment of the DB-9 Socket P1B as
Second RS-232 (Front View)...................................................93
Figure 24: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on phyCORE-LPC2292/94, Front View) ................................95
Figure 25: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Carrier Board) .....................................................................96
Figure 26: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Carrier Board with Galvanic Separation) ...........................99
Figure 27: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on phyCORE-LPC2292/94, Front View) ..............................101
Figure 28: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Carrier Board) ...................................................................102
Figure 29: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Carrier Board with Galvanic Separation) .........................105
Figure 30: Pin Assignment Scheme of the Expansion Bus.....................109
Figure 31: Pin Assignment Scheme of the Patch Field...........................109
Figure 32: Connecting the DS2401 Silicon Serial Number....................119
Figure 33: Pin Assignment of the DS2401 Silicon Serial Number.........119
Figure 34: Ethernet Transformer Module Connector..............................121
Figure 35: Location of Solder Jumpers J1 – J4 and Ethernet Interface
Connector X7.........................................................................122
Figure 36: phyCORE-LPC2292/94 Component Placement,
Top View................................................................................125
Figure 37: phyCORE-LPC2292/94 Component Placement,
Bottom View..........................................................................126
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1 .....................................16
Table 2: Jumper Settings ..........................................................................24
Table 3: J200, J202 Second Serial Interface Configuration....................25
Table 4: J201, J203 First Serial Interface Configuration ........................25

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Table 5: J204 A/D Converter Reference Voltage................................. 26
Table 6: J205, J206 Chip Select Configuration.................................... 27
Table 7: J207 MCKO Signal Configuration......................................... 27
Table 8: J208, J209 Flash Memory Size Configuration ....................... 28
Table 9: J210, J211 RAM Memory Size Configuration....................... 29
Table 10: J300 Flash Ready/Busy Configuration................................... 30
Table 11: J301, J302 Flash Write Protection Configuration .................. 31
Table 12: J400, J401 SRAM Access Configuration............................... 32
Table 13 J402 SRAM Supply Voltage Configuration........................... 32
Table 14: J503 Ethernet Chip Select Signal Configuration.................... 33
Table 15: J501 Ethernet Interrupt Signal Configuration ........................ 33
Table 16: J503 Ethernet Ready Signal Configuration............................ 34
Table 17: J504 Ethernet LAN_IRQ Pull-up Configuration................... 34
Table 18: J505, J506, J507 Ethernet EEPROM Configuration............. 34
Table 19: J508 Ethernet EEPROM Enable Configuration ..................... 35
Table 20: J509 Ethernet nLNK Pin Configuration................................. 35
Table 21: J600, J601 CAN Transceiver Activation................................ 36
Table 22: J616 CAN Transceiver Supply Configuration........................ 37
Table 23: J602, J603, J604 and J605 CAN Interface Configuration...... 38
Table 24: J606 EEPROM Write Protection............................................ 38
Table 25: J607 Watchdog Configuration................................................ 39
Table 26: J608, J609, J610 I2C Interface Configuration......................... 40
Table 27: J611, J612, J613, J614 SPI Interface Signal Configuration ... 40
Table 28: J615 CAN Level Configuration.............................................. 41
Table 29: J616, J617 CAN Transceiver VCC at Pin #5 ......................... 42
Table 30: J618 VDD_V3V3 Supply Control.......................................... 43
Table 31: J619, J620 SPI Master/Slave Selection .................................. 43
Table 32: J621 WDI Signal Source ........................................................ 44
Table 33: J622 RESET Signal Source .................................................... 45

Contents
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Table 34: J800, J801 ETM/OCDS Connector Configuration
(DCM-023 only) ......................................................................45
Table 35: C210 CLKIN Configuration...................................................46
Table 36: System Startup Configuration – Boot Device Selection..........47
Table 37: System Startup Configuration – Debug/Trace Port.................48
Table 38: /CS Signal (Bank) Address Ranges and
Configuration Registers ...........................................................50
Table 39: Memory Device Options for U607 ..........................................57
Table 40: Memory Area Ethernet Controller...........................................60
Table 41: JTAG and TRACE Modes.......................................................67
Table 42: debugCORE-LPC2292/94 DIP Switch S800 ..........................70
Table 43: ETM/OCDS Connector at X800..............................................71
Table 44: LAN MII Connector at X500...................................................72
Table 45: Improper Jumper Setting for JP30/33 on the Carrier Board....83
Table 46: JP9, JP16 Configuration of the Main Supply
Voltages VCC / VCC2.............................................................84
Table 47: JP9, JP16 Improper Jumper Settings for the Main
Supply Voltages.......................................................................85
Table 48: JP28 Configuration of the Boot Button ...................................86
Table 49: JP28 Configuration of a Permanent ISP Mode Start ..............87
Table 50: JP41 phyCROE-LPC2292/94 Boot Memory
Configuration ...........................................................................88
Table 51: Jumper Configuration for the First RS-232 Interface..............89
Table 52: Improper Jumper Settings for DB-9 Socket P1A as
First RS-232.............................................................................90
Table 53: JP24 Power Supply to External Devices Connected to
P1A on the Carrier Board.........................................................92
Table 54: Jumper Configuration of the DB-9 Socket P1B
(Second RS-232)......................................................................93
Table 55: Improper Jumper Settings for DB-9 Socket P1B
(Second RS-232)......................................................................94

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Table 56: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the phyCORE-LPC2292/94............................ 95
Table 57: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Carrier Board HD200................................ 96
Table 58: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on the Carrier Board)........................................... 97
Table 59: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Carrier Board with Galvanic Separation... 98
Table 60: JP39 CAN Bus Voltage Supply Reduction ............................ 99
Table 61: Improper Jumper Settings for the CAN Plug P2A (CAN
Transceiver on Carrier Board with Galvanic Separation)..... 100
Table 62: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the phyCORE-LPC2292/94.......................... 101
Table 63: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Carrier Board HD200.............................. 102
Table 64: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on the Carrier Board)......................................... 103
Table 65: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the Carrier Board with
Galvanic Separation............................................................... 104
Table 66: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on Carrier Board with Galvanic Separation)..... 106
Table 67: JP17 Configuration of the Programmable LED D3.............. 107
Table 68: JP40 Configuration of User Button S3................................. 107
Table 69: Pin Assignment Data Bus for the phyCORE-LPC2292/94 /
Carrier Board / Expansion Board .......................................... 110
Table 70: Pin Assignment Address Bus for the
phyCORE-LPC2292/94 / Carrier Board /
Expansion Board.................................................................... 111
Table 71: Pin Assignment Address/Control Bust for the
phyCORE-LPC2292/94 / Carrier Board /
Expansion Board.................................................................... 112
Table 72: Pin Assignment Port P0 for the phyCORE-LPC2292/94 /
Carrier Board / Expansion Board .......................................... 113

Contents
©PHYTEC Messtechnik GmbH 2006 L-658e_5
Table 73: Pin Assignment Port P1 for the phyCORE-LPC2292/94 /
Carrier Board / Expansion Board...........................................114
Table 74: Pin Assignment Interface Signals for the
phyCORE-LPC2292/94 / Carrier Board /
Expansion Board....................................................................115
Table 75: Pin Assignment Power Supply for the
phyCORE-LPC2292/94 / Carrier Board /
Expansion Board....................................................................116
Table 76: Unused Pins on the phyCORE-LPC2292/94 /
Carrier Board / Expansion Board...........................................117
Table 77: JP19 Jumper Configuration for Silicon Serial
Number Chip..........................................................................118
Table 78: Ethernet Transformer Connector Pinout................................121
Table 79: Solder Jumpers J1 - J4 Configuration Ethernet Interface.....122

phyCORE-LPC2292/94
©PHYTEC Messtechnik GmbH 2006 L-658e_5

Preface
©PHYTEC Messtechnik GmbH 2006 L-658e_5 1
Preface
This phyCORE-LPC2292/94 Hardware Manual describes the board's
design and functions. Precise specifications for the Philips
LPC2292/94 microcontroller can be found in the enclosed
microcontroller Data Sheet/User's Manual. If software is included
please also refer to additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformity of the
PHYTEC phyCORE-LPC2292/94
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.

phyCORE-LPC2292/94
2©PHYTEC Messtechnik GmbH 2006 L-658e_5
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-LPC2292/94 is one of a series of PHYTEC Single
Board Computers that can be populated with different controllers and,
hence, offers various functions and configurations. PHYTEC supports
all common 8- and 16-bit as well as selected 32-bit controllers in two
ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
©PHYTEC Messtechnik GmbH 2006 L-658e_5 3
1Introduction
The phyCORE-LPC2292/94 belongs to PHYTEC's phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCORE-LPC2292/94 is a subminiature (60 x 53 mm) insert-
ready Single Board Computer populated with the Philips LPC2292/94
microcontroller. Its universal design enables its insertion in a wide
range of embedded applications. All controller signals and ports
extend from the controller to high-density pitch (0.635 mm)
connectors aligning two sides of the board, allowing it to be plugged
like a "big chip" into a target application.

phyCORE-LPC2292/94
4©PHYTEC Messtechnik GmbH 2006 L-658e_5
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the Philips LPC2292/94. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-LPC2292/94.
The phyCORE-LPC2292/94 offers the following features:
•subminiature Single Board Computer (60 x 53 mm) achieved
through modern SMD technology
•populated with the Philips LPC2292/94 microcontroller
(TQPF-144 packaging)
•improved interference safety achieved through multi-layer PCB
technology and dedicated Ground pins
•controller signals and ports extend to two 100-pin high-density
(0.635 mm) Molex connectors aligning two sides of the board,
enabling it to be plugged like a "big chip" into target application
•32-bit, demultiplexed bus mode
•max. 60 MHz clock frequency (ca. 50 ns instruction cycle, extern;
ca. 10 ns internal Flash)
•1.5 Gbyte external address space
•2 MByte (up to 16 MByte) on-board Flash1
•on-board Flash programming, no dedicated Flash programming
voltage required through use of 3.3 V Flash devices
•1 MByte (up to 8 MByte) RAM on-board, max. 1 MByte at 0 wait
states1
•up to two CAN transceivers (Infineon TLE6250V33)
•RS-232 transceiver for two serial interfaces
•optional SMSC 91C111 Ethernet controller with EEPROM
•2 kByte (up to 8 kByte) SPI-EEPROM1
•I2C Real-Time Clock with internal quartz (can be battery buffered)
•up to two free microcontroller Chip Select signals (if optional
Ethernet controller is not populated)
1: Please contact PHYTEC for more information about additional module configurations.

Introduction
©PHYTEC Messtechnik GmbH 2006 L-658e_5 5
•up to 6 freely programmable Chip Select signals from on-board
CPLD device (requires changing the default CPLD code1)
•one operating voltage for core & peripherals, 3.3 V, typ. < 280 mA
(with maximum circuitry installed at 60 MHz CPU frequency)
•controller 1.8 V core voltage generated on-board
•additional 5 V operating voltage for CAN transceivers,
typ. <12 mA
•support of LPC2292/2294 single chip mode
•support of ETM debug interface (only on debugCORE version)
1: Please contact PHYTEC if you have questions about changing the CPLD code.

phyCORE-LPC2292/94
6©PHYTEC Messtechnik GmbH 2006 L-658e_5
1.1 Block Diagram
Figure 1: Block Diagram phyCORE-LPC2292/94
R e s e t
di
g
ital I / O ports
P H I L I P S
LPC2292/94
A
0-A23
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
R S - 2 3 2
A
d d r
F L A S H
2MB - 16MB
R A M
1MB – 8MB
D0-31 D a t a
C A N
RxD1 / TxD1
RxD0 / TxD0
CAN2H /CAN2L
SPI bus
RxD0/TxD0
Reset
E E P R O M
CAN2
CAN1 CAN1H /CAN1L
SPI
CAN
Interface C A N
Transceiver
Transceiver
Transceiver
I2C
I/O
RxD1/TxD1
JTAG/ETM
Connector
JTAG JTAG bus
Ethernet opt
opt
opt
RTC

Introduction
©PHYTEC Messtechnik GmbH 2006 L-658e_5 7
1.2 View of the phyCORE-LPC2292/94
PCM-023
L600
X701
RN200
U403
U301
U401
XT500
U303
U302
U606
X200
Q200
U605
XT200
U402
U201
U400
U600
U300
PL1231.1
PHYTEC
220
Figure 2: Top View of the phyCORE-LPC2292/94

phyCORE-LPC2292/94
8©PHYTEC Messtechnik GmbH 2006 L-658e_5
1
RN500
U200
Q600
RN504
U601
U604
RN201
RN503
U501
U603
RN502
U607
RN700
U608
U602
U203
U500
RN501
U202
X700 RN600
19
RN601
D603
Figure 3: Bottom View of the phyCORE-LPC2292