Phytec phyCORE-PXA255 User manual

A product of a PHYTEC Technology Holding company
Development Board for
phyCORE-PXA255
Hardware Manual
PCB# 1220.1 and 1220.2
Edition November 2004

Development Board for phyCORE-PXA255
PHYTEC Meßtechnik GmbH 2004 L-657e_0
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Meßtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Meßtechnik GmbH neither gives any
guarantee nor accepts any liability whatsoever for consequential damages resulting
from the use of this manual or its associated product. PHYTEC Meßtechnik
GmbH reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Meßtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Meßtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2004 PHYTEC Meßtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or in
part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Meßtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [e-mail] 1 [phone] [e-mail]
Technical
Support: [phone] [email protected] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Preliminary Edition November 2004

Contents / Table of Figures
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Preface...........................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................6
1.2 Overview.......................................................................................7
2 Port Pin Initialization..........................................................................9
3 Jumpers..............................................................................................13
4 Power Supply System........................................................................15
5 Memory Configuration.....................................................................19
5.1 Interrupts.....................................................................................20
5.2 Control PLD (U6).......................................................................21
5.2.1 Control PLD (U6) Registers..........................................21
5.2.2 External Data and Address Bus.....................................29
5.3 IDE Interface and CF Card PLD (U7)........................................30
5.3.1 IDE Interface .................................................................31
5.3.2 Compact Flash Interface................................................36
6 Ethernet Interface .............................................................................41
7 USB Host ............................................................................................43
8 USB Client..........................................................................................45
9 LCD Interface....................................................................................47
10 RS-232 Interface................................................................................49
10.1 FF-UART....................................................................................51
10.2 BT-UART...................................................................................52
10.3 IR-UART....................................................................................53
11 CAN Interface....................................................................................55
12 AC97 Interface and Touch Controller ............................................57
13 MultiMedia Card...............................................................................60
14 Expansion Board ...............................................................................61
15 Push Buttons and LEDs....................................................................65
16 Matrix Keyboard...............................................................................67
17 GPIO Expansion Board Interface....................................................69
18 JTAG Interface (X29) .......................................................................85
19 Technical Specifications....................................................................87
20 Hints for Handling the Module........................................................89
21 Component Placement Diagram......................................................91
22 Revision History ................................................................................92
Appendices A..............................................................................................93
AI Hardware Revision .....................................................................93
Index............................................................................................................95

Development Board for phyCORE-PXA255
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Index of Figures
Figure 1: Block Diagram of the Development Board...................................6
Figure 2: Development Board Overview (Top View)..................................7
Figure 3: Development Board Overview (Connector Side View)................7
Figure 4: Expansion Board Overview (Top View).......................................8
Figure 5: Expansion Board Overview (Side View)......................................8
Figure 6: Numbering of the Jumper Pads...................................................13
Figure 7: Location of the Jumpers (Development Board)..........................13
Figure 8: Location of the Jumpers (Expansion Board)...............................14
Figure 9: Power Supply Block Diagram.....................................................16
Figure 10:Battery Charger Circuitry............................................................17
Figure 11:Control PLD U6 ..........................................................................21
Figure 12:Decoupling the Data and Address Bus........................................29
Figure 13:CF Card and IDE PLD U7 ..........................................................30
Figure 14:IDE Hard Drive Mounting Location...........................................31
Figure 15:IDE Circuitry...............................................................................32
Figure 16:Compact Flash Interface on the Expansion Board......................36
Figure 17:Compact Flash Circuitry .............................................................36
Figure 18:Ethernet Circuitry........................................................................41
Figure 19:Location of the Ethernet Socket..................................................41
Figure 20:USB Host Connector...................................................................43
Figure 21:Location of the USB OTG Socket...............................................43
Figure 22:USB Client Connector.................................................................45
Figure 23:Active TFT LCD Connection......................................................47
Figure 24:LCD Inverter Circuitry................................................................48
Figure 25:RS-232 Connectors (FF-UART, BT-UART)..............................49
Figure 26:IR-UART Connector...................................................................50
Figure 27:P1 Pin Assignment, FF-UART....................................................51

Contents / Table of Figures
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Figure 28:P2 Pin Assignment, BT-UART...................................................52
Figure 29:CAN Connector...........................................................................55
Figure 30:CAN Connector P3 Pinout ..........................................................56
Figure 31:Sound and Touch Controller Interfaces.......................................57
Figure 32:AC97 with WM9712L.................................................................58
Figure 33:MultiMedia Card .........................................................................60
Figure 34:Expansion Board, Top View .......................................................61
Figure 35:Expansion Board, Side View.......................................................61
Figure 36:Location of Push Buttons and LEDs (Side View).......................65
Figure 37:Location of Push Buttons and LEDs (Top View) .......................66
Figure 38:Matric Keyboard Connection ......................................................67
Figure 39:GPIO Expansion Bus Numbering Scheme..................................69
Figure 40:Physical Dimensions (Development Board)................................87
Figure 41:Physical Dimensions (Expansion Board) ....................................88
Figure 42:Component Placement Diagram Development Board
(PCB Revision 1220.1)................................................................91
Figure 43:Component Placement Diagram Expansion Board .....................91
Index of Tables
Table 1: Port Configuration GPIO0-39 .....................................................10
Table 2: Port Configuration GPIO40-84 ...................................................11
Table 3: Jumper Functions and Section Reference....................................14
Table 4: Interrupt Assignment phyCORE-PXA255..................................20
Table 5: Interrupt Assignment Development Board..................................20
Table 6: Control PLD U6 Reset Values ....................................................22
Table 7: PLD U6 Control Register 0.........................................................22
Table 8: PLD U6 Control Register 1.........................................................23
Table 9: PLD U6 Control Register 2.........................................................23
Table 10: PLD U6 Control Register 3.........................................................24
Table 11: PLD U6 Control Register 4.........................................................24

Development Board for phyCORE-PXA255
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Table 12: PLD U6 Control Register 5.........................................................25
Table 13: PLD U6 Control Registers 6 and 7..............................................25
Table 14: PLD U6 Control Register 8.........................................................26
Table 15: PLD U6 Control Register 9.........................................................27
Table 16: PLD U6 Control Register 10.......................................................27
Table 17: PLD U6 Control Register 11.......................................................28
Table 18: IDE Control Register with Reset Values.....................................32
Table 19: IDE Control Register 0................................................................32
Table 20: IDE Control Register 1................................................................33
Table 21: IDE Register 2.............................................................................33
Table 22: IDE Control Register 3................................................................34
Table 23: IDE Control Register 4................................................................34
Table 24: TrueIDE Memory Area Assignment...........................................35
Table 25: Physical Address Range of the IDE Interface.............................35
Table 26: CF Card Control Register with Reset Values..............................37
Table 27: CF Card Control Register 0.........................................................37
Table 28: CF Card Control Register 1.........................................................38
Table 29: CF Card Control Register 2.........................................................38
Table 30: CF Card Control Register 3.........................................................39
Table 31: CF Card Control Register 4.........................................................39
Table 32: CF Card Control Register 5.........................................................40
Table 33: CF Card Control Register 6.........................................................40
Table 34: Address Space for Ethernet Controller........................................42
Table 35: USB Host Jumpers......................................................................44
Table 36: LCD Connector at X33 ...............................................................48
Table 37: BT-UART Jumper Configuration ...............................................52
Table 38: IR-UART Connector at X19.......................................................53
Table 39: IR-UART Jumper Configuration ................................................53
Table 40: CAN Interface Jumper Configuration.........................................56

Contents / Table of Figures
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Table 41: AC97 Expansion Socket at X24..................................................57
Table 42: Voltage Supervision with WM9712L..........................................59
Table 43: Sound Jacks .................................................................................59
Table 44: Expansion Board Connector X30 Pinout ....................................62
Table 45: Expansion Board Connector X31 Pinout ....................................63
Table 46: GPIO Expansion Bus X17 Pin Assignment ................................77
Table 47: Signal Pin Assignment for the phyCORE-PXA255
Development Board / Expansion Board......................................84
Table 48: JTAG Connector X29 Pinout ......................................................85

Development Board for phyCORE-PXA255
PHYTEC Meßtechnik GmbH 2004 L-657e_0

Preface
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Preface
This manual describes only the functions of the PHYTEC
phyCORE-PXA255 Development Board. The controllers and relevant
Single Board Computers for use with the Development Board are not
described herein. Additional controller- and board-level information
and technical descriptions can be found in appropriate Hardware
Manual or User’s Manual support documentation. If software is
included please also refer to additional documentation for this
software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration regarding Electro Magnetic Conformity
of the phyCORE-PXA255 Development Board
PHYTEC Development Boards (henceforth products) are designed for
installation in electrical appliances or as dedicated Evaluation Boards
(i.e.: for use as a test and prototype platform for hardware/software
development) in laboratory environments.
Note:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product’s pin header rows are longer than 3 m.

Development Board for phyCORE-PXA255
2PHYTEC Meßtechnik GmbH 2004 L-657e_0
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header rows or connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-PXA255 Development Board is one of a series of
PHYTEC Development Boards supporting the phyCORE-PXA255
Single Board Computer module. PHYTEC supports common 8-, 16-
and selected 32-bit controllers on two types of Single Boards
Computers:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC’s microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.