Phytec phyCORE-i.MX27 User manual

A product of a PHYTEC Technology Holding company
phyCORE-i.MX27
HARDWARE MANUAL
EDITION FEBRUARY 2011

phyCOREi.MX27
©PHYTEC Messtechnik GmbH 2011 L-710e_5
In this manual are descriptions for copyrighted products that are not explicitly indicated
as such. The absence of the trademark (™) and copyright (©) symbols does not imply
that a product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for
any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts
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information contained herein without prior notification and accepts no responsibility for
any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability
for damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout
and/or design of the hardware without prior notification and accepts no liability for doing
so.
©Copyright 2011 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from PHYTEC
Messtechnik GmbH.
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Address: PHYTEC Technologie Holding AG
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D-55129 Mainz
GERMANY
PHYTEC America LLC
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Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [email protected] 1 [phone]
[email protected]
Technical
Support: [phone] [email protected] 1 [phone]
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Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Edition February 2011

Contents
©PHYTEC Messtechnik GmbH 2011 L-710e_5
1Preface.................................................................................................1
1.1 Introduction...................................................................................2
1.2 Block Diagram..............................................................................4
1.3 View of the phyCORE-i.MX27......................................................5
2Pin Description...................................................................................7
3Jumpers.............................................................................................21
4Power Requirements........................................................................27
5Real Time Clock U11 / SRAM U19 Backup-Voltage.......................29
6System Configuration......................................................................31
6.1 System Startup Configuration.....................................................31
6.1.1 Power-Up-Mode-Select (PUMS).....................................31
6.1.2 Boot Mode Select ...........................................................32
7System Memory................................................................................33
7.1 Memory Model............................................................................33
7.2 LP-DDR-SDRAM (U3-U4)..........................................................33
7.3 NOR-Flash (U17)........................................................................34
7.4 NAND Flash Memory (U16)........................................................34
7.4.1 8/16-Bit NAND Flash Usage (JN1,JN2,RN31,RN32).....35
7.5 I²C EEPROM (U12)....................................................................35
7.5.1 Setting the EEPROM Lower Address Bits
(J13, J15, J16)................................................................36
7.5.2 EEPROM Write Protection Control (J1)..........................36
8Serial Interface..................................................................................37
8.1 RS-232 Transceiver (U18)..........................................................37
8.1.1 UART1 Routing (RN30)..................................................37
9USB-OTG Transceiver (U20)............................................................39
10 Ethernet Controller / Ethernet-Phy (U9) .........................................40
11 JTAG Interface (U15)........................................................................41
12 Technical Specifications .................................................................45
13 Hints for Handling the phyCORE-i.MX27 .......................................47
14 The phyCORE i.MX27 on the i.MX Carrier Board ..........................49

phyCOREi.MX27
©PHYTEC Messtechnik GmbH 2011 L-710e_5
14.1 Concept of the phyCORE-i.MX Development Kits.....................50
14.2 phyMAP-i.MX27..........................................................................51
14.2.1 phyMAP-i.MX27 Jumper Settings...................................53
14.2.2 phyMAP-i.MX27 Signal Mapping....................................54
14.2.3 phyMAP-i.MX27 Mapper Physical Dimensions ..............62
14.3 Cooperation of phyCORE-i.MX27 and phyCORE-i.MX
Carrier Board..............................................................................63
14.3.1 Power Supply..................................................................63
14.3.2 CAN Interface.................................................................67
14.3.3 Push Buttons and LEDs..................................................69
14.3.4 Compact Flash Card.......................................................71
14.3.5 Security Digital Card/ MultiMedia Card...........................73
14.3.6 Audio and Touchscreen..................................................74
14.3.7 USB Host........................................................................76
14.3.8 LCD Connectors.............................................................78
14.3.9 Camera Interface............................................................79
14.3.10 JTAG Interface..............................................................81
14.3.11 Complete jumper setting list for phyCORE-i.MX27
on the i.MX Carrier Board.............................................82
15 Revision History...............................................................................85
16 Component Placement Diagram.....................................................87
Index..........................................................................................................89

Contents
©PHYTEC Messtechnik GmbH 2011 L-710e_5
Index of Figures
Figure 1: Block Diagram of the phyCore-i.MX27.............................4
Figure 2: Top view of the phyCORE-i.MX27 (controller side)..........5
Figure 3: Bottom view of the phyCORE-i.MX27 (connector side)....6
Figure 4: Pin-out of the phyCORE-Connector
(top view, with cross section insert)..................................8
Figure 5: Typical jumper pad numbering scheme..........................21
Figure 6: Jumper locations (top view)............................................22
Figure 7: Jumper locations (bottom side in top view) ....................23
Figure 8: minimum circuit...............................................................27
Figure 9: JTAG interface at U15 (top view) ...................................41
Figure 10: JTAG interface at U15 (bottom view) .............................42
Figure 11: Physical dimensions.......................................................45
Figure 12: phyCORE-i.MX27 Carrier Board connection using the
phyMAP-i.MX27..............................................................50
Figure 13: Modular development and Expansion Board concept
with phyCORE-i.MX27....................................................50
Figure 14: phyMAP-i.MX27 top view ...............................................51
Figure 15: phyMAP-i.MX27 bottom view .........................................52
Figure 16: Jumper location on PMA-005.........................................53
Figure 17: Physical dimensions of phyMAP-i.MX27 mapper...........62
Figure 18: pyhCORE-i.MX Carrier Board and phyCORE-i.MX27
Power Supply..................................................................63
Figure 19: phyCORE-i.MX Carrier Board CAN Interface.................67
Figure 20: phyCORE-i.MX Carrier Board Buttons and LEDs ..........69
Figure 21: Compact Flash Card Interface........................................71
Figure 22: SD Card interface...........................................................73
Figure 23: phyCORE-i.MX Carrier Board Audio/Touch Interface....74
Figure 24: phyCORE-iMX Carrier Board USB-Host Interface .........76
Figure 25: phyCORE-i.MX Carrier Board LCD Interfaces ...............78

phyCOREi.MX27
©PHYTEC Messtechnik GmbH 2011 L-710e_5
Figure 26: phyCORE-i.MX Carrier Board Camera Interface............79
Figure 27: phyCORE-iMX Carrier Board JTAG Interface................81
Figure 28: phyCORE-i.MX27 component placement (top view) ......87
Figure 29: phyCORE-i.MX27 component placement
(bottom view)..................................................................88

Contents
©PHYTEC Messtechnik GmbH 2011 L-710e_5
Index of Tables
Table 1: Pin-out of the phyCORE-Connector X1............................9
Table 2: Jumper settings ..............................................................24
Table 3: Power supply for the minimum circuit.............................28
Table 4: i.MX27 default power input voltages...............................28
Table 5: VBKUP2 Voltage Settings..............................................29
Table 6: Default PUMS for i.MX27 module...................................31
Table 7: Boot Modes of i.MX27 module .......................................32
Table 8: i.MX27 memory map ......................................................33
Table 9: Compatible NOR Flash devices .....................................34
Table 10: Compatible NAND Flash devices...................................34
Table 11: JN1/2,RN31/32 NAND Flash bit width selection.............35
Table 12: U12 EEPROM I²C address via J13, J15, and J16..........36
Table 13: EEPROM write protection states via J1..........................36
Table 14: RN30 UART1 signal routing...........................................38
Table 15: Fast Ethernet controller memory map............................40
Table 16: JTAG connector U15 signal assignment........................43
Table 17: Jumper settings of PMA-002..........................................53
Table 18: PMA-002 mapping list ....................................................54
Table 19: Jumper settings for i.MX27 power supply via
power plug......................................................................64
Table 20: Jumper settings for i.MX27 power supply via POE ........65
Table 21: Jumper settings for i.MX27 power supply via battery.....66
Table 22: CAN interface jumper settings........................................68
Table 23: x_BOOT_MODE0 selection............................................70
Table 24: x_BOOT_MODE1 selection............................................70
Table 25: x_switch..........................................................................70
Table 26: CF interface jumper settings...........................................72
Table 27: SD/MMC interface jumper settings for i.MX27 module ..73

phyCOREi.MX27
©PHYTEC Messtechnik GmbH 2011 L-710e_5
Table 28: Audio/Touchscreen interface jumper settings ................75
Table 29: UBS Host interface jumper settings for i.MX27 module .77
Table 30: Camera interface jumper settings for i.MX27 module ....80
Table 31: JTAG jumper settings for phyCORE-i.MX27 module .....81
Table 32: Jumper settings for i.MX27 module on
i.MX Carrier Board..........................................................82

Preface
©PHYTEC Messtechnik GmbH 2011 L-710e_5 1
1Preface
This hardware manual describes the phyCORE-i.MX27 Single Board Computer’s design and function.
Precise specifications for the Freescale i.MX27 microcontrollers can be found in the enclosed
microcontroller Data Sheet/User's Manual.
In this hardware manual and in the attached schematics, active low signals are denoted by a "/" or “#”
preceding the signal name (e.g.: /RD or #RD). A "0" indicates a logic zero or low-level signal, while a
"1" represents a logic one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE-I.MX27
PHYTEC Single Board Computers (henceforth products) are designed for installation
in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype
platform for hardware/software development) in laboratory environments.
Caution!
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only
be unpacked, handled or operated in environments in which sufficient precautionary measures have
been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel
(such as electricians, technicians and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry if connections to the product's
pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity
only in accordance to the descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power connector and serial interface to a
host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions
of PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any modifications to the products as
well as implementation of the products into target systems.
The phyCORE-i.MX27 is one of a series of PHYTEC Single Board Computers that can be populated
with different controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly into
the user’s peripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design
costs and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html

phyCOREi.MX27
2 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
1.1 Introduction
The phyCORE-i.MX27 belongs to PHYTEC’s phyCORE Single Board Computer module family. The
phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all
core elements of a microcontroller system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin
package allows dedication of approximately 20 % of all pin header connectors on the phyCORE
boards to ground. This improves EMI and EMC characteristics and makes it easier to design complex
applications meeting EMI and EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-i.MX27 is a subminiature (84 x 60 mm) insert-ready Single Board Computer populated
with the Freescale i.MX27 microcontroller. Its universal design enables its insertion in a wide range of
embedded applications. All controller signals and ports extend from the controller to high-density pitch
(0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a
target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the Freescale i.MX27. No
description of compatible microcontroller derivative functions is included, as such functions are not
relevant for the basic functioning of the phyCORE-i.MX27.

Introduction
©PHYTEC Messtechnik GmbH 2011 L-710e_5 3
The phyCORE-I.MX27 offers the following features:
•Subminiature Single Board Computer (84 x 60 mm) achieved through modern SMD technology
•Populated with the Freescale i.MX27 microcontroller (BGA404 packaging)
•Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
•Controller signals and ports extend to two 200-pin high-density (0.635 mm) Molex connectors
aligning two sides of the board, enabling it to be plugged like a "big chip" into target application
•Max. 400 MHz core clock frequency
•Boot from NOR or NAND Flash
•32 MByte (up to 64MByte) Intel Strata NOR Flash
•64 MByte (up to 1 GByte) on-board NAND Flash1
•128 MByte (up to 256 MByte) Mobile DDR SDRAM on-board
•RS-232 transceiver supporting one UART at data rates of up to 460kbps
•Full featured UART Interfaces without transceiver
•32 KB I2C EEPROM
•Separate I²C RTC with backup function
•512 Kbyte (up to 2MByte SRAM) with backup function
•Battery buffered controller based RTC with automatic battery switchover
•High-Speed USB OTG transceiver
•Auto FDX/MDX 100 MBit Ethernet Controller
•All controller required supplies generated on board by PMIC
•Synchronous 18Bit LCD-Interface
•PCMCIA/CF card Interface
•ATA-Interface DMA-Mode 3 (up to DMA-mode 5 without level-shifter) / CMOS Camera Interface
•Support of standard 20 pin debug interface through JTAG connector
•Keyboard support for up to 64 keys in a 8 * 8 matrix
•Two I2C interfaces
•SD/MMC card interface with DMA
•Special Power-Management IC which includes:
oStereo line-in
oStereo line-out / pre-amplified mono-out
oStereo mic-in
o4-Wire touch interface
oRTC
oLCD-Backlight control
oBattery charger
o6 AD-Inputs
1Please contact PHYTEC for more information about additional module configurations.

phyCOREi.MX27
4 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
1.2 Block Diagram
Figure 1: Block Diagram of the phyCore-i.MX27

Introduction
©PHYTEC Messtechnik GmbH 2011 L-710e_5 5
1.3 View of the phyCORE-i.MX27
C96
TP15
C10
RN28
R92
C149
R1
RN21
C11
RN18
R81
C152
C17
U18
Q6 C81
R11
R54
TP5
TP6
TP9
R61
RN23
L4
C144
RN20
C172
R25
C91
C28
TP10
R3
R35
R41
C167
TP14
C171
R13
RN2
R17
C26
C24
C134
TP13
C141
C108
R65
L3
C175
C161
C164
J21
RN4
C115
C163
Q4
R72
RN24
TP16
RN8
R10
R37
RN29
C162
C146
C118
J16
R24
J9
C27
R7
R62
C145
C173
RN19
C135
R63
C143
R78
RN25
C112
R4
D7
R90
C21
C102
D6
L5
C117
R53
U5
J15
TP1
R14
C85
TP7
C97
U3
TP12
R19
R12
R66
C99
RN17
R21
XT3
U4
D5
TP8
RN30
C151
RN22
Q7
C16
RN16
TP11
TP17
R48
C111
J1
R64
C109
C110 C140
R60
R9
J13
RN26
C20
TP2
C105
R55
C94
XT2
C150
C116
C29
C107
C104
R71
C114
U12
R8
C23
R6
Q2
RN5
RN7
RN1
RN6
U15
JN2 JN1
RN27 RN15
RN13 RN31
RN32 RN12
RN14
RN3
U24
C174
U17
D2
U16
U19
R89
QO1
C142
U14
Figure 2: Top view of the phyCORE-i.MX27 (controller side)

phyCOREi.MX27
6 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
R26
TP25
C159
R43
C46
C103
C128
D3
C77
TP23
J12
C61
C153
U11
J20
TP19
C92
C139
TP20
R20
R79
C42
C154
J14
C120
C53
XT1
R42
C119
C84
R39
C72
J11
U22
C93
TP3
C155
R56
U6
C14
C15
C54
J5
R58
C73
R91
R36
J22
C52
R57
R45
C3
J18
Q1
J4
C38
R69
C157
C60
C122
R80
C62
C50
C35
C59
C31
C131
C57
C13
U21
J7
C22
R49
C32
C129
R18
R23
U23
C100
C67
R46
C55
TP18
C87
C1
C133
RN9
C89
C74
J19
C2
D8
TP24
TP21
R44
C126
C68
R59
C158
L1
C156
C106
R27
J3
C25
R88
C51
TP4
C80
C125
R40
C41
J8
C75
C47
C66
Q3
R82
J6
R84
C45
R28
C79
TP26
C113
C137
C170
C69
C34
R85
C101
C86
C168
J2
U9
R38
C33
C130
R83
C63
C98
C19
C9
R34
R32
C36
R33
D4
C166
U10
C147
C165
C76
L2
R29
R16
C40
C148
C49
RN10
C30
C8
C65
Q5
R30
RN11
C64
R67
C71
C90
C169
D1
R50
C123
C78
J17
R22
C124
C82
TP22
C5
C56
C39
R87
R86
D9
C132
C7
R68
C70
C48
C58
R15
C37
C95
R31
C136
C83
C43
J10
C88
C121
C4
C138
R47
C6
R70
X1
C12
C18
C127
C44
R5
X1
U1
U20
U2
Figure 3: Bottom view of the phyCORE-i.MX27 (connector side)

Pin Description
©PHYTEC Messtechnik GmbH 2011 L-710e_5 7
2Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller manuals/data
sheets. As damage from improper connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the module connections are
protected from overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors
(0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the
phyCORE-i.MX27 to be plugged into any target application like a "big chip".
A new numbering scheme for the pins on the phyCORE-connector has been introduced with the
phyCORE specifications. This enables quick and easy identification of desired pins and minimizes
errors when matching pins on the phyCORE-module with the phyCORE-connector on the appropriate
PHYTEC Development Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which
column positions are identified by a letter and row position by a number. Pin 1A, for example, is
always located in the upper left hand corner of the matrix. The pin numbering values increase moving
down on the board. Lettering of the pin connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-i.MX27 (viewed from above;
phyCORE-connector pointing down) or with the socket of the corresponding phyCORE Development
Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCORE-i.MX27 marked with a triangle. The numbering scheme is
always in relation to the PCB as viewed from above, even if all connector contacts extend to the
bottom of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-connector as well as
mating connectors on the phyCORE Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the
phyCORE-connector is usually assigned a single designator for its position (X1 for example). In this
manner the phyCORE-connector comprises a single, logical unit regardless of the fact that it could
consist of more than one physical socketed connector. The location of row 1 on the board is marked
by a triangle on the PCB to allow easy identification.
The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-i.MX27
with SMT phyCORE-connectors on its underside (defined as dotted lines) mounted on a Development
Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a
cross-view of the phyCORE-module showing these phyCORE-connectors mounted on the underside
of the module’s PCB.

phyCOREi.MX27
8 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
Figure 4: Pin-out of the phyCORE-Connector (top view, with cross section insert)
Table 1 provides an overview of the pin-out of the phyCORE-connector, as well as descriptions of
possible alternative functions. Table 1 also provides the appropriate signal level interface voltages
listed in the SL (Signal Level) column. The Freescale i.MX27 is a multi-voltage operated
microcontroller and as such special attention should be paid to the interface voltage levels to avoid
unintentional damage to the microcontroller and other on-board components. Please refer to the
Freescale i.MX27 User’s Manual/Data Sheet for details on the functions and features of controller
signals and port pins.

Pin Description
©PHYTEC Messtechnik GmbH 2011 L-710e_5 9
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin.
Those pins marked as “N/A” have a range of applicable values that constitute proper operation.
Table 1: Pin-out of the phyCORE-Connector X1
PIN ROW X1A
PIN # SIGNAL I/O SL DESCRIPTION
1A NVDD7_12_14 O NVDD7_12_14 LCD reference voltage (1.75 V - 2.8 V)
2A GND - 0 Ground 0 V
3A not connected - - Pin left unconnected
4A not connected - - Pin left unconnected
5A X_VSYNC I/O NVDD7_12_14 Display vertical synchronization pulse
6A X_OE_ACD O NVDD7_12_14 Alternate crystal direction/output enable
7A GND - 0 Ground 0 V
8A X_REV O NVDD7_12_14 REV signal for display
9A X_SPL_SPR O NVDD7_12_14 SPL/SPR signal for display
10A X_PS O NVDD7_12_14 Control signal output for source driver
11A Not connected - - Pin left unconnected
12A GND - 0 Ground 0 V
13A X_LD0 I/O NVDD7_12_14 Input/Output data to display
14A X_LD2 I/O NVDD7_12_14 Input/Output data to display
15A X_LD3 I/O NVDD7_12_14 Input/Output data to display
16A X_LD5 I/O NVDD7_12_14 Input/Output data to display
17A GND - 0 Ground 0V
18A X_LD8 I/O NVDD7_12_14 Input/Output data to display
19A X_LD10 I/O NVDD7_12_14 Input/Output data to display
20A X_LD11 I/O NVDD7_12_14 Input/Output data to display
21A X_LD13 I/O NVDD7_12_14 Input/Output data to display
22A GND - 0 Ground 0 V
23A X_LD17 I/O NVDD7_12_14 Input/Output data to display
24A X_#CS0 O NVDD1_2_3_4_5 Chip Select 0 output
25A X_#CS1 O NVDD1_2_3_4_5 Chip Select 1 output
26A X_#CS4 O NVDD1_2_3_4_5 Chip Select 4 output
27A GND - 0 Ground 0 V
28A X_#PC_IORD/#EB1 O NVDD1_2_3_4_5 Active low external enable byte signal that
controls
D [7:0]
29A X_#PC_IOWR/#OE O NVDD1_2_3_4_5 Memory Output Enable
30A X_#LBA O NVDD1_2_3_4_5 Load Burst Address
31A X_BCLK O NVDD1_2_3_4_5 Burst Clock
32A GND - 0 Ground 0 V
33A X_A2 O NVDD1_2_3_4_5 Address-Line A2

phyCOREi.MX27
10 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
34A X_A4 O NVDD1_2_3_4_5 Address-Line A4
35A X_A5 O NVDD1_2_3_4_5 Address-Line A5
36A X_A7 O NVDD1_2_3_4_5 Address-Line A7
37A GND - 0 Ground 0 V
38A X_A10 O NVDD1_2_3_4_5 Address-Line A10
39A X_A12 O NVDD1_2_3_4_5 Address-Line A12
40A X_A13 O NVDD1_2_3_4_5 Address-Line A13
41A X_A15 O NVDD1_2_3_4_5 Address-Line A15
42A GND - 0 Ground 0 V
43A X_A18 O NVDD1_2_3_4_5 Address-Line A18
44A X_A20 O NVDD1_2_3_4_5 Address-Line A20
45A X_A21 O NVDD1_2_3_4_5 Address-Line A21
46A X_A23 O NVDD1_2_3_4_5 Address-Line A23
47A GND - 0 Ground 0 V
48A X_D0 I/O NVDD1_2_3_4_5 Data_Bus D0
49A X_D2 I/O NVDD1_2_3_4_5 Data_Bus D2
50A X_D3 I/O NVDD1_2_3_4_5 Data_Bus D3
51A X_D5 I/O NVDD1_2_3_4_5 Data_Bus D5
52A GND - 0 Ground 0 V
53A X_D8 I/O NVDD1_2_3_4_5 Data_Bus D8
54A X_D10 I/O NVDD1_2_3_4_5 Data_Bus D10
55A X_D11 I/O NVDD1_2_3_4_5 Data_Bus D11
56A X_D13 I/O NVDD1_2_3_4_5 Data_Bus D13
57A GND - 0 Ground 0 V
58A X_PC_BVD1 I NVDD1_2_3_4_5 PCMCIA Battery Voltage Detect Input 1
59A X_PC_BVD2 I NVDD1_2_3_4_5 PCMCIA Battery Voltage Detect Input 2
60A X_#PC_CD1 I NVDD1_2_3_4_5 PCMCIA Card Detect Input 1
61A X_PC_PWRON I NVDD1_2_3_4_5 PCMCIA Power is ON Signal
62A GND - 0 Ground 0 V
63A X_#PC_RW O NVDD1_2_3_4_5 PCMCIA External Transceiver Direction Signal
64A X_PC_VS1 I NVDD1_2_3_4_5 PCMCIA Voltage sense Input 1
65A X_PC_VS2 I NVDD1_2_3_4_5 PCMCIA Voltage sense Input 2
66A X_CE0 O NVDD1_2_3_4_5 PCMCIA Card Enable 0 Signal
67A GND - 0 Ground 0 V
68A X_IOIS16 I NVDD1_2_3_4_5 PCMCIA I/O port is 16-bits
69A X_FEC_TXD3 O NVDD6_8_9_10 Fast Ethernet Transmit Data 3
70A X_FEC_RX_ER I NVDD6_8_9_10 Fast Ethernet Receive Data Error
71A X_FEC_RXD2 I NVDD6_8_9_10 Fast Ethernet Receive Data 2
72A GND - 0 Ground 0 V
73A X_FEC_MDC O NVDD6_8_9_10 Fast Ethernet Management Data Clock
74A X_FEC_TX_CLK O NVDD6_8_9_10 Fast Ethernet Transmit Clock signal

Pin Description
©PHYTEC Messtechnik GmbH 2011 L-710e_5 11
75A X_FEC_RXD0 I NVDD6_8_9_10 Fast Ethernet Receive Data 0
76A X_FEC_RX_CLK I NVDD6_8_9_10 Fast Ethernet Receive Clock signal
77A GND - 0 Ground 0 V
78A X_CSI_D0 I NVDD11 Camera Sensor D0
79A X_CSI_D2 I NVDD11 Camera Sensor D2
80A X_CSI_D3 I NVDD11 Camera Sensor D3
81A X_CSI_D5 I NVDD11 Camera Sensor D5
82A GND - 0 Ground 0 V
83A NVDD11 O NVDD11 Camera reference voltage (2.8 V)
84A X_CSI_MCLK O NVDD11 Camera Sensor Master Clock
85A X_CSI_VSYNC I NVDD11 Camera Sensor vertical sync
86A X_CSI_PIXCLK I NVDD11 Camera Sensor data latch clock
87A GND - 0 Ground 0 V
88A X_KP_COL0 I/O NVDD6_8_9_10 Keypad Port Column 0
89A X_KP_COL1 I/O NVDD6_8_9_10 Keypad Port Column 1
90A X_KP_COL2 I/O NVDD6_8_9_10 Keypad Port Column 2
91A X_KP_ROW0 I/O NVDD6_8_9_10 Keypad Port Row 0
92A GND - 0 Ground 0 V
93A X_KP_ROW3 I/O NVDD6_8_9_10 Keypad Port Row 3
94A X_KP_ROW5 I/O NVDD6_8_9_10 Keypad Port Row 5
95A X_PC28 I/O NVDD6_8_9_10 GPIO PC28
96A not connected - - Pin left unconnected
97A GND - 0 Ground 0 V
98A X_PC29 I/O NVDD6_8_9_10 GPIO PC29
99A X_PC30 I/O NVDD6_8_9_10 GPIO PC30
100A X_PC31 I/O NVDD6_8_9_10 GPIO PC31

phyCOREi.MX27
12 ©PHYTEC Messtechnik GmbH 2011 L-710e_5
PIN ROW X1B
PIN # SIGNAL I/O SL DESCRIPTION
1B X_WDI I LV Watchdog input has to be kept high by the
processor to keep MC13783 active
2B X_VSTBY I LV Signal from primary processor to put
MC13783 in a low power mode
3B X_PWGT1EN I LV Power gate driver 1 enable
4B GND - 0 Ground 0 V
5B X_HSYNC I/O NVDD7_12_14 Display horizontal synchronization pulse
6B not connected - - Pin left unconnected
7B X_CONTRAST O NVDD7_12_14 Contrast control for display
8B X_CLS O NVDD7_12_14 CLS signal for display
9B GND - 0 Ground 0 V
10B X_LSCLK O NVDD7_12_14 Display Shift Clock
11B not connected - - Pin left unconnected
12B not connected - - Pin left unconnected
13B X_LD1 I/O NVDD7_12_14 Input/Output data to display
14B GND - 0 Ground 0 V
15B X_LD4 I/O NVDD7_12_14 Input/Output data to display
16B X_LD6 I/O NVDD7_12_14 Input/Output data to display
17B X_LD7 I/O NVDD7_12_14 Input/Output data to display
18B X_LD9 I/O NVDD7_12_14 Input/Output data to display
19B GND - 0 Ground 0 V
20B X_LD12 I/O NVDD7_12_14 Input/Output data to display
21B X_LD14 I/O NVDD7_12_14 Input/Output data to display
22B X_LD15 I/O NVDD7_12_14 Input/Output data to display
23B X_LD16 I/O NVDD7_12_14 Input/Output data to display
24B GND - 0 Ground 0 V
25B X_#CSD1 O NVDD1_2_3_4_5 Chip Select Output 1 for SDRAM
26B X_#CS5 O NVDD1_2_3_4_5 Chip Select Output 5
27B X_#PC_REG/#EB0 O NVDD1_2_3_4_5 Active low external enable byte signal that
controls D [15:8]
28B X_#PC_WE/#RW O NVDD1_2_3_4_5 #RW signal—Indicates whether external
access is a read (high) or write (low) cycle
29B GND - 0 Ground 0 V
30B X_#ECB I NVDD1_2_3_4_5 Active low signal sent by flash device
31B X_A0 O NVDD1_2_3_4_5 Address-Line A0
32B X_A1 O NVDD1_2_3_4_5 Address-Line A1
33B X_A3 O NVDD1_2_3_4_5 Address-Line A3
34B GND - 0 Ground 0 V
35B X_A6 O NVDD1_2_3_4_5 Address-Line A6