Sharp Mz-800 User manual

SHARP

SERVICE MANUAL

CODE:

OOZMZ8OOIIIIE

PERSONAL COMPUTER

MODEL

MZ-800

MZ-1P16

MZ-1E20

Table of contents

t,

Specification

..

2.

Parts identification

..

3.

Systemdiegram

..

4.

Systemdescriplion

..

4·',

Memorymep

..

4-2.

CustomLSI

.....

4-2-1.

Memoryconlroller

...

4-2-2.

VOcontroller

..

4-2-3. Clock generator end

timing

generator

..

4-2-4. Display address generator

...

4-2-5. Scroll control circuit .....

..................................... 4

................................................... 6

..

9

.

.......................

12

.. ......... 12

..

.....

13

. ......................................... 15

4·2·6. VRAMdeta

inputloutpulcircuil

..

4-2-7. Register functions

....

.............................................................. 20

4-2-8. Pal1etcircuit .....

..

...........

25

4-2-9.

CRTC

register

map

•.

.

................................

26

4-2-10.

ROMconfigufation

...

............................................... 27

4-3. 8255 Programmable Peripheral Interface

...

4-4. 8253 Programmable Interval

Timer

..

.........

................................ 27

..

......

31

4-5. Printer interface

..

4-6. Programmable sound generator

.•

4-7. Joystick

..

4-8.Systemswitchsetups

...

5.

Powersupply

.....

MZ-1P16

.....

. ..................................................

31

.................................................................. 34

.........

35

. .....................................................

35

..

......................................................... 35

. ...................................................

35

SHARP CORPORATION

1

SpedfIution

-f-

I-

tI

;:'

-

:::.

..

.

Dicpl'vmethod

.CoIor

8'lm.p

.....

thod

-

Resolution

PCGmalhocl

320

>e

200

...

,

,..

OP 320

>e

2OO

10<121

~~

>e

2OO

10<121

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slgn.......1

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----

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...

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of

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tlon

_+---+

==",-

~

__

~keOfI8caIO"

Cen"onlclinterl_

=:!.~-dtofd

~n~l~naISPllk"

P\o!point

..

VI""'output

Joystick

RF

,

VIDEO

,AnalagRG8woth

tI

••

Ml-820FI

I'ntlrlac.'

Ml-700 -

"'ItB

W.fJOO

-

8ItB

CG

-"'1t8

~h'ndling



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M!~7~moo.only

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180< '''',

c:oIora

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~~

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interl_

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fO<IheRGBllrmlnl'

AlAR,

compatibll

ijo'flitickdldlcatedl

~

-

~

----+

TO'_

:::

.

O'-

"'"'

......

--,

"'

c----I'

~""c:::"'2:::.:ii_

RS-232C OP

Joyllick

density MZ-88,03

-o;;t;;;",,,ixp<lntlr

PlOt

printer

ATAAlcompat,bll

W-1E19,MZ·1Fl1

MZ.'0'lcomPl~

:~'.:::",PI"~

_

Ml-1P18

St.ttu.SC£I011

2.

Parts identification

IFront

view

I

Definable keys

RF

connector

Main keyboard

Channel knob

(home TV channel selection)

BW/color select switch

Composite connector

RGB

connector

EXT cassette jack

Dip switch

(home

TC

cable connection)

Data recorder

POWER

lamp

Cursor control keys

Expantion slot

External printer

output connector

Joystick connector

DELETE

and INSERT keys

RESET

switch

Power input

Volum!! control

2

MZ-1P16

power

supply socket (+SV)

POWER

switch

~ilZ-800

MZ-800

3. System diagram

MZ-1A18

AAMfile

MZ-1A25

Expansion RAM

MZ-1E19

MZ-1x17

MZ interface

MZ-1E20 MZ-1U06

1U06 interfacing

PWB

Expansion

VO

box

MZ-1P16

Plot printer

MZ-1D04

12", 8-tone,

monochrome

CAT

MZ-1D19

14", 18-color, AGBI, CAT

/I~

0,

'J).oh

,

MZ-1E05 MZ-1F19

M

FD

interface Single

floppy

disk drive

MZ-1T04

MZ-811 connection

tape recorder

MZ-8BI03

AS-232C card

MZ-SOP5(K)

MZ-1F02

Dual MFD drive

SO-column,

dot

matrix

printer

25.

/1~

JOYSTICK

ATAAI compatible

3

MZ·1F11 MZ-6F03

MZ

driver

MZ

blank media

MZ-2Z046

DISK BASIC

MZ-2Z047

CP/M

MZ-1C30 MZ-1F19

Expansion cable Single floppy disk drive

MZ-1C30 MZ-1F02

Expansion cable Dual MFD drive

4. System description

Basic RAM, 64KB

KEY

CMT

VF

AMP

r-

--,

I MZ-1R18 slol I

I (dedicated) I

L

___

-.J

PPI

8255

CTC

8253

PSG

SN76489

Expansion

slot-l

[2]'

MFD MZ-1F02

MZ-800

16

KB

l

r---'

I

l.

MZ-1P16

OP

I

r-

---

-,

L

_~

Plot printer I

l

,.--J

PlO

Z-80

PlO

MlSOP5K printer

Printer interface

r----+----.J

Joystick interface

4

VRAM

16

KB

CRTC

(Semi-cuslom)

r-

-----,

I VRAM I

I

16

KB

(OP)

HZ-1R25

L

_____

J )

--~

RS-232C

MZ-8BI03

RGBI

Video

(ATARI compatible)

o

o 0

TV

MZ-1D19

CJ1

-~

Option 16

KB

RESET

GDG

VRAM

ADR.

BUS

'17.73

MHz

VRAM DATA BUS

I-

00

~~~

t

-u

RGBI

0"

u.,

~

I

~CustomlC

OSC

556

Monitor, JI

--ffi]

16KBROM

:'~::::::~

CSROiI.1

(27128

,I

i

0=

3.547 MHz

cPU~

LJ

[

1 Z-80A

t...

OSCJ

Cursor

556

·1

RAS

VRAS

WE

CAS

ADDRESS BUS £

~

"

0

'Cij

1

DATA BUS T J

"

..

CONTROL BUS c.

)(

w--c=

Bus

driver

dn'

Peripheral

VO

bus

CTC

~

Z-80A

~rl

8253

PlO

If

fi

I

1""

General purpose

input

bus '

.~

lci7Jt

&J

PC21

II~~

~

DATA

RECORDER

AMP

L--+

___

,

PA5

PA4

SP

~

PBI

PRINTER

DATA BUS

'1L\2-

CTRLBUS I L/"""'I

PAf

I

~

r I

~fl,--I

~~--'-I

~CTRLBUS

';~

System switch

..)J

(MZ

+--+

Centronics)

External

printer

bus

aJ

,

Q.

.'

CD

iil

3

-

4-1.

Memory

map

The MZ-800 has a different

memory

map depending on

o MZ-800

memory

map

FFFF"

EOOO

0000

COOO

AOOO

01000

--

4000

2000

1000

MAIN

o-RAM

64K.

O-RAM

MZ-700

mode

r---,

~

ROM

~

VRAM

MZ-800

mode

MAIN

o-RAM

64 KB

O-RAM

MZ-800

the mode. To have

compatibility

with

the MZ-700, it has

two

modes

of

the MZ-700

mode

and MZ-800 mode.

O

[J

D

OVOR"';:

__

,

I I I I

: :

In:

lml:

~

__

J L

__

J

,.--,

1 I

: IIV) I

1 I

L

__

oJ

~

640

)(

200

mode

VRAM

320 x 200

mode

NOTE:

r--..,

1 1

:

eX):

1 1

,-

__

.J

Item within

dotted

lin.

represents

an

option

unit

MZ·1R25

Memory

map

changes

after

initial

program

loading

$0000

SI

000

$2000

$8000

SEooo

SFFFF

® Power on (resel)

MZ-800

mode

MON. ROM

CG.ROM

DRAM

V-RAM

(320x2oo

mode)

DRAM

MON. ROM

@

At

start

of

monitor

MZ-700

mode

$0000

r------,

MON.

ROM

$1000

r-----;

LD

A, 08H

OUT (CE), A

=>

DRAM

SDOOO

V-RAM

SEooo

SE010

I<.!'Y.

nM~K

MON. ROM

SFFFF

•

Memory

map at

power

on is in the MZ-800

mode

as

in

®,

but

it

changes

to

the MZ-700

mode

by the

monitor

ROM

when

the

monitor

program

starts.

After

transferring the

CG

data

to

the

VRAM

PCG

area

from

the

CG

ROM at @, the

memory

map

then returns

to

®.

• When the system

program

is completed

to

load,

the

memory

map goes

into

the MZ-700

mode

if

the

system switch (SW1) is set

to

ON side.

If

set

to

OFF

side,

it

changes

to

the MZ-800 mode, then the

memory

map

as

in @. During those changes, all

memory

spaces are composed

of

RAM and isolated

from

ROM and VRAM.

IN

(EOH),

A

=>

©

Wril.

10

PeG

from

CG

MZ-7oo

mode

$0000

$1000

$2000

MON. ROM

CG.ROM

D-RAM

@ System operation

MZ-7oo & 800 modes

$0000

D-RAM

IN

(El

H), A

~

6

SCOOO

V-RAM (CG)

SDOOO

SEooo V-RAM

SE010

MON. ROM

SFFFF SFFFF

L...

___

---'

• Depression

of

the manual reset switch assumes

memory

map transition in order

of

®

~

®

~

@

~

®,

similar

as in the case

of

power

on.

• However, depression

of

the reset switch in conjunc-

tion

with

the ICTRL Ikey assumes the

memory

map

of

@ after being changed once

to

the

MZ-700

or

MZ-800

mode

depending on the state

of

the system switch.

In

the case

of

the

MZ-800 mode,

it

is set

to

the plane I.

IT

(4-color mode)

of

the

320 x 200 mode.

MZ-800

~

port

SEO

MODE -

Function o

SOOOO

-S7FFF

to

DRAM.

0000

1000

2000

3000

4000

DRAM

5000

6000

7000

8000 I

9000 I

I

Aooo I

I

BOOO

I

COOO

I

Dooo I

I

EOOO

I

E070

Fooo I

I

FFFF

L

__

..J

Memory Sank Control

SEl

SE2

SE3 SE4

MZ-7oo

mode

MZ-SOO

mode

-MZ-7oo

mode

MZ-SOO

mode

MZ-7oo

mode

MZ-800

mode

o Soooo -

SFFFF

o SEooo -

SFFFF

o

SOOOO

-

$OFFF

o

$0000

-

SFFFF

o SEooo -

SFFFF

o

SOOOO

-

$OFFF

o

SOOOO

-

$OFFF

to

DRAM.

to

DRAM.

to

monitor

to

VRAM,

key

to

monitor

to

monitor

to

monitor

ROM.

timer,

and

ROM.

ROM. ROM.

monitor

ROM. o

Slooo

-$CFFF o

Slooo

-SlFFF

to

DRAM

to

CG

ROM.

o

Soooo

-$FFFF o S2000 -$7FFF

to

VRAM,

key

and

timer,

and $Cooo -

SDFFF

monitor

ROM.

to

DRAM.

o $8000 -

SBFFF

to

VRAM

(NOTE).

o SEooo -

SFFFF

to

monitor

ROM.

i--l

,---, MONITOR

'--I

1--'

MONITOR MONITOR

I I ROM I I I I ROM ROM

I I I I I I

I I I I I

I

I I I I

I I I

I I I I

I

I I I I

I

I I I I I

I I I

I

I I I I

I I I

I I

I

DRAM

CG

ROM

DRAM

I

I V

RAM

I r--

---

I I

I I (NOTE)

I I

I

I I

DRAM

I I V

RAM

I V

RAM

B I KEY, TIMER

DRAM

I I MONITOR MONITOR

ROM

I ROM

I

L

__

J

Area

within

dotted

line

does

not

involve

change.

DEY,

nMER

MONITOR

ROM

MONITOR

ROM

----1

(NOTE): In

the

case

of

320 x 200

mode,

contents

of

$8000 -$9FFF are

transferred,

instead,

and

those

after

$Aooo are

transferred

to

DRAM.

Power

on

or

RESET

input

7

MZ-800

~rt

OUT

(SE5)

OUT

(SEe)

IN

(SEO)

IN

(SE1)

MODE

MZ-700

mode

MZ-800

mode

MZ-700

mode

MZ-800

mode

MZ-700

mode

MZ-800

mode

MZ-700

mode

MZ-800

mode

Function

o

SDOOO

-S7FFF o

SEOOO

-

SFFFF

o

SDOOO

-

SFFFF

o

SEOOO

-

SFFFF

o S1000 -S1FFF o S1000 -

S1

FFF

o S1000 -S1FFF o S1000 -

S1

FFF

prohibited.

returned

to

returned

to

toCG

ROM.

toCG

ROM.

returned

to

returned

to

the

state

be-

the

state be- o

SCOOO

-

SCFFF

o $8000 -SBFFF

the

state ba-

the

state ba-

fore

prohi-

fore

prohi-

toVRAM

(PCG

to

VRAM

fore

CG

was

fore

CG

was

bited. bited.

RAM).

(NOTE). set. set.

o

SCOOO

-

SCFFF

o $8000 -

SBFFF

to

DRAM.

to

DRAM.

0000

r--l

I--l

1--'

1--,

,---,

1--,

,---,

r--,

I I I I I I I I I I I I

1000 I B B

I I I R

Q8

I ROM ROM

2000 I I I I I I I I

I I I I I I

3000 I I I

I I I I

I I I

4000 I I I I I I

I I I I

5000 I I I I I I

I I

I I I I

8000

I I

I 1 I I

7000 1 I 1 1 I I

'1

I I I

I

8000

I

1

9000 I 1 V

RAM

I 1

Aooo I I

----

DRAM

1 I

Booo 1 I (NOTE)

Cooo I

~

I V

RAM

I

(CGRAM) I 1

DOOO

1 I I

Eooo I I I I

Prohibited

State

before

1 I I

prohibited

I I I

Fooo

Prohibited

State

before

I I I I I

prohibited

I I

1 I I I L

__

J

FFFF

L

__

-.l L

__

-.l L

__

.J

8

MZ-800

4-2. Custom

LSI

The custom

LSI

is a 100-pin single

chip

LSI

on which the

MZ-800

memory

controller (I/O controller) and

CRT

controller, etc. are contained.

4-2-1. Memory controller

Used

for

the control

of

the

memory

bank. Addressing

of

DRAM, ROM, and VRAM is conducted by selection I/O

address,

$EO

-$E6, using OUT

or

IN

command.

I/O

Signal Device (I/O)

address name

4-2-2. 1/0 controller

In this I/O controller is created the select signal

for

assignment

of

MZ-800 internal device.

See Table-2

for

relation

of

internal device vs

I/O

address.

Function

FF

Port

B,

printer data

output

FE

CPR

Z80A Port A, printer control and

timer

interrupt

FD

PlO (I/O) Port B control (Mode

0)

FC

Port A control (Mode

3)

F2

PSG PSG

(0)

PSG

output

port

F1

JOY JOYSTICK (I) Joystick-2

input

port

FO

Joystick-1

input

port

FO

--

(0)

Pallet

write

E6

1

--

(110)

Memory

bank control

EO

D7

Control

port

output

D6

C53

8253 (I/O) Counter-2 (NOTE): Mapped

to

E007

-E004 in the

D5

Counter-1 MZ-700 mode.

D4

Counter-O

D3

Control

D2

KEY

8255

(110)

Port

C,

cassette, etc. (NOTE): Mapped

to

E003

-

EOOO

in the

D1

Port

B,

key

input

MZ-700 mode.

DO

Port A, key strobe

output

CF

0

CE

I/O

CRTC

register

CD

--

0

CC

0

$E008

-- --

I/O

TEMP, HBLK

input;

and 8253

GO

ON/OFF

output

for

the MZ-700

mode

only.

* When above I/O address is accessed,

it

makes 10WR active

for

OUT

or

lORD

for

IN

command.

9

MZ-800

Pin Signal name

1/0

Functional description Note

No.

1

CPU

0

CPU

clock (3.547 MHz)

2

5V

-Power

supply

3 GND -Ground

4

ADO

I I I

CPU

address bus

19

ADF

20

DTO

I I

1/0

CPU

data bus

27

on

28

GND -Ground

-----0---

VCC

Power

supply

29

-

--30

MREO I

CPU

MREQ signal Negative logic

--

31

RD

I

CPU

RD

signal Negative logic

32

WR

I

CPU

WR

signal Negative logic

33

RFSH I

CPU

RFSH signal Negative logic

34

IORQ

I

CPU

lORQ

signal Negative logic

e----,.;-----

I---

I

CPU

Ml

signal Negative logic

35

Ml

---36-

--

SEL1

0 System RAM address

multiplexer

select signal

37

CASB 0 System RAM

column

address strobe signal

~8

INH5 0 Inhibit bank (OUT

$E5)

select signal (uH" = Inhibit).

OPEN

f------

0 Vertical blanking signal Negative logic

39

VBLN

1--

40

GND -

41

VRAS 0 VRAM

RAS

control signal Negative logic

42

IJCli:S

0 VRAM CAS control signal Negative logic

-

43

VADO

I I 0 VRAM address signal (multiplexer

output)

50

VAD7

_._--

51

VOE

0 VRAM

output

enable Negative logic

52

VCC

-Power

supply

53

GND -Ground

54

VRWR 0 VRAM

write

signal Negative logic

55

VAO

I I

1/0

VRAM data bus (standard RAM)

62

VA7

---

63--f--

VCO

I I

1/0

VRAM data bus (option RAM)

70

VC7

I----

i

,--

I-----

SBCR

0 Color sub-carrier wave

--ii--

I----

RED

0 Video signal, red

--73--

BLUE 0 Video signal, blue

-~---

----GREN

0 Video signal, green

1-----

YITN 0 Brightness control signal

75

1-------

VSYN 0 Vertical sync signal Negative logic

76

77 HSYN 0 Horizontal sync signal Negative logic

f---

--

GND

78 -

------

-.

---

79

VCC

-

80

CLKO

I Clock

input

(17.7344 MHz)

-_

..

_---

81

CROM 0 ROM chip enable Negative logic

-8-2-

KEY 0 8255 chip enable Negative logic

---a3-

f------NTpL I NTSC/PAL selection (PAL -

"L")

GND

--

--------f---- I Test pin

("H"

-test mode) GND

~~=p~SD~

I MZ-700/800

mode

selection

("L"

= MZ-700 mode)

86

lOWR 0

Sum

of

CS

and

WR

of

1/0

controlled

by

the

custom

IC

Negative logic

C---

S7

--

lORD 0 Sum

of

CS

and

RD

of

1/0

controlled

by

the custom

IC

Negative logic

-------aa--

--------cR

S 0

1/0

$BO

-$B4 chip enable

OPEN

89

SIO

0

1/0

$F4

$F7

chip enable

OPEN

90

RSTO 0 Reset

output

Negative logic

f--

----- I Manual reset

input

Negative logic

91

MNRT

92

PORT

---

I Power on reset

input

Negative logic

93

WTGD 0 Wait signal

to

CPU

Open drain

94

JOY 0 Joystick chip enable Negative logic

95

CPR

0 PlO chip select Negative logic

96

PSG

0 76489 chip select Negative logic

97

CKMS 0 8253 musical interval clock

1------g8

53G

0 8253 musical interval ONIOFF gate signal

---

99

C53 0 8253 chip enable Negative logic

100

TEMP I MZ-700 mode, $E800

tempo

input

* Term "OPEN" represents the signal

not

used on the board.

10

I

MZ-800

conflgur.tlon

GNO

ADO

AOl

AD'

AD7

...

AOO

AOA

ADO

ADC

AOO

AD'

OTO

on

072

073

0"

on

GNO

TlM'

m

~G

JOY

IIOIIT

IIISTO

CI"$

IOWR

TEST

KEY

C&3

CKMS

CIJR

MOO

MNIfT

SIC

lORD

MOO'

Mm

CJIIOM

""IIJ

lO!SH

lilT

~

VI[R

VJIA!"

VADO

VA02

VA04

VAD6

WJr

~

SEll

[NHS

GND

~

VAD' VADJ

VAOS

VA07

GNO

.....

......

~TN

G"N

BlUE

••

0

sac.

VC>

VCI

vet;

\IC4

VC,

VC2

VC.

\/CO

VA7

VAB

VAS

VM

VA3

VA2

VA1

VAD

.....

GNO

Custom

LSI

block diagram VSYN

SBCR

HSYN

VBlN

CKMS

CPU

CLKO

NTPL

ADO

- F

DTO

-7

RD

WR

MREO

M1

10RO

RFSH

CROM

SEL1

CASB

INHS

CPR

KEY

C53

53G

JOY

PSG

CRS

SIO

lORD

10WR

WTGD

,16

8

I

Clock generator &

timing

generator

CPU

address

CPU

VF

CONTROL

t--

Memory

I--

controller

----

110

controller

WAIT

controller

•

--1

Display address

generator

-

~

DATA I

)~

MPX I

R~iSplay

contro T

.--

register +

~

Rscroll

register~

I--

Scroll circuit

! t

~

MPX l

VRAM address

controller

!

r MPX l

1VRAM 1

-I

Timing control 1

VRAS

11

8

VCAS

VRWR

VADO-7

VROE

Vcc

2,

29,

52,

79,

GND

3,

28,

40,

53,

78 pin

PORT

MNRT

RESET

I

-

Input

BUFF

-

Pallet

circuit

Shift

register

~

VRAM data

110

circuit

, 8 8

VAO-7

VCO-7

RSTO

MOD7

TEMP

RED

GREN

BLUE

YITN

1·

4-2-3. Clock generator and

timing

generator

Oscillation

from

the

crystal oscillator is divided

to

create

the

CPU

clock, horizontal sync, vertical sync, and dis-

play address control signals.

Since the

low

state

of

signal is used

for

NTPL (NTSCI

PAL

selection)

with

the MZ-800, the

CPU

clock

of

3.547 MHz is derived

from

the

crystal frequency

of

17.734 MHz by

dividing

it

1/5.

NTPl

1>-----'

CK32 (112)

001

(114)

To

displ.-v

.dd

.....

generator

Clock generator and

timing

generator

circuits

IO,splay

mode

'egoslll')

OM02

t>----+---'

OTO-7

ICPU

dala)

IScroll regosted

,-----,

sw

Scroll

control

SSA

Display address

generator

block

diagram

VSYN

12

4-2-4. Display address generator

1)

Display address generation

MZ-800

• Display address increments

from

left

to

right

as

beginning

from

the

home

position at the upper left

corner

of

the

CRT

screen (address $000). The first

display line dominates address $000 through $027.

Because a screen

frame

consists

of

200

rasters, the

address at the

right

side

of

the

bottom

corner is

as

follows:

(200 x 40) - 1 = 7999 =

$1

F3F

• The address counter stops counting

for

a horizontal

flyback line and stored in the address latch circuit.

When the horizontal flyback line terminates, the

address latch

output

is preset in the address counter

(display address generator).

• Address is generated even

while

the vertical flyback

line is active and

it

makes the counter reset before

termination

of

the

vertical flyback line.

2)

Display address generation in the MZ-700 mode

• Because characters are displayed under the

PCG

method

in the MZ-700 mode, address is generated

for

each character and

the

same address is used

for

displaying

of

one character. The 3-bit horizontal line

counter is provided

to

count horizontal lines

to

generate

the

address

(LCO

-

LC2)

for

selection

of

the

character front.

Display address increments

from

left

to

right having

the

uppermost

left corner

of

the screen

for

the home

position.

Since

25

lines are used

to

develop displaying

of

characters composed

of

8 x 8 dots, the address at

the

right

of

the

bottom

lines becomes

$3EF.

3)

Display address

multiplexed

with

CPU

address

• Address used

to

write

data

to

the

VRAM is latched in

order

to

avoid

CPU

wait. Display modes

of

640 dots

and 320

dots

are assigned by the mode switch

(DMD2).

• Display address is

multiplexed

with

the VRAM

write

address in the

timing

of

DISP which has the

timing

that

the display address and

CPU

address may

become a pseudo cycle steal.

I

MZ-800

4-2-5. Scroll

1)

Scrolling is possible

for

both

horizontal

and

vertical

directions

by

means

of

software

offset.

The

following

four

registers are

use~

for

scroll

control.

a.

Scroll start address register: SSA (7-bit)

b.

Scroll end address register: SEA (7-bit)

c.

Scroll

width

register:

SW

= SEA-SSA (7-bit)

d. Scroll offset register: SOF (10-bit)

(

x y z

I

SEA

+--

__

I

!

l,

___

_ )

---

2)

Control

of

scroll starts

by

the

initialization

of

the

scroll control register.

SSA = $0

SEA = $7D

SW = $7D

SOF = $0

3)

Way

of

smooth

scrolling

SOF = $0

~

$5

Programming

"SOF =

$5"

makes

the

display

screen

shifted one line up.

The highest line (address: $0 -$27) is then assigned

to

the

lowest

line

($1

F18

-.:

$1

F3F).

As

normal

scroll

involves

updating

of

the data

for

the

lowest

line,

the

data

of

address

$1

F18

-

$1

F3F

are

updated.

SOF = $5

~

$0

By reducing the value

of

SOF

by

"5",

it

makes the

screen shifted one line

down.

SEAL-

____________________________

~

13

4)

Line scroll

SOF =

$O~

$28

Programming

"SOF =

$28"

makes

the

display screen

shifted

eight

lines up. Data on the highest line

therefore shifted

to

the

bottom

line.

Programming

"$28

~

$0"

makes the

display

screen

shifted

eight

lines

down,

and

the

line

on

the

bottom

moves

to

the

highest

line.

5)

Screen

split

Appropriate

deviation

of

SSA. SEA, and

SW

permits

to

divide

the

screen

into

three sections

of

®,

® and

©.

Though

the

section ® is

permitted

to

scroll, sections

® and © are

not

permitted

to

scroll.

See the

figure

to

explain

with.

@

SSA-.

®

SEA-.

©

Assume

now

that

the

top

of

the

section ® is on the

5th line (40 raster) and

the

top

of

the section © is on

the 18th line (144 raster).

Attention

must

be paid to

the fact

that

values SSA and SEA are used

for

assigning lines. Scroll registers are set

with

the

following

values.

SSA = $19

SEA =

$5A

SW

=

$41

SOF = $0

In

this

occasion,

it

needs

to

initialize

the

screen that

has been displayed. "SOF =

$5"

must

be program-

med

to

scroll ® one line. Then,

only

the

section ® is

shifted up, and

the

highest

line

of

® moves

to

the

bottom

line

of

®.

Programming

"SOF =

$A"

makes

it

scrolled one

more

line.

SOF

~

SW

Scroll offset (SOF)

should

necessarily be

within

a

range

of

the

scroll

width.

Display is

not

assured

with

SOF set greater than SW.

Scroll and and

control

circuit

hardware

• Block diagram

Start address

SEA-SOF

10

DA(MA)

10

7 SEA

DA(MA)

7

Scroll

width

SOF

c

Scroll offset

Relation

of

display address. SEA. SSA. vs

SOF

Display address m I k j i

SSA SSA SSA SSA SSA SSA

6 5 4 3 2

SEA SEA SEA SEA SEA

SEA 6 5 4 3 2

SOF

SOF SOF

SOF

SOF SOF

9 8 7 6 5

Screen left end address

oLine 0 0 0 0 0

1 Line 0 0 0 0 0

2 Line 0 0 0 0 0

3 Line 0 0 0 0 0

8 Line 0 0 0 0 1

16 Line 0 0 0 0

24 Line 0 0 0 1

192 Line 0

199 Line

Relation

of

SW vs

SOF

SW>

SOF

h

SSA

1

SEA

1

SOF

4

0

1

0

14

MZ-800

Scroll

control

register

SSA: Scroll start address

Increment

of

SSA: $5

Minimum

value

of

SSA:

$0

Maximum

value

of

SSA: $78

MSB

LSB

N 6 5 4 3 2

SEA: Scroll end address

Increment

of

SEA: $5

Minimum

value

of

SEA: $5

Maximum

value

of

SEA:

$70

MSB

LSB

N 6 5 4 3 2

SW: Scroll

width

Increment

of

SW:

$5

Minimum

value

of

SW: $5

Maximum

value

of

SW:

$70

Relation

of

SW. SEA. vs SSA

SW = SEA -SSA

SW>

SSA

MSB

LSB

N 6 5 4 3 2

S~

I

SOF: Scroll offset

Increment

of

SOF: $5

Minimum

value

of

SOF: $0

(without

offset)

Maximum

value

of

SOF: $3E8

MSB

LSB

SOF

1 I 7 6 5 4 3 2

S~F

I

MSB

LSB

SOF

21

__________

1 9

S~F

1

S~A

I f e d

I

c b a

--

0

SEA I I

S~F

IS~F

S~F

I

-

SOF

3 2

I I

I

0 0 0 0 0 0 0

0 1 0 0 0 0 First line

1 0 0 0 0 0

1 1 0 0 0

1 0 0 0 0 0 0 Second line

0 0 0 0 0 0 0 Second line

1 0 0 0 0 0 0

0 0 0 0 0 0 0

Twenty

fifth line

0 0 0 0 0

MZ-800

Concept of

the

scroll control circuit

Scroll method

• Scrolling by means

of

VRAM address conversion.

Range of scroll

• y-axis programmable.

BASIC console command compatible

• x-axis fixed

Scroll sequence

• The scroll start address is termed

"SSA"

and end

address "SEA".

• Execution

of

scroll,

with

offset given

from

the

CPU.

• One line (line

S)

starting

from

SSA disappears

from

the display screen.

• A new line (line S') is added

to

SEA. Line S' is the

same refresh

memory

as

the line

S.

The contents

of

the

memory

was erased (nullified by the

CPU)

before

the execution.

x

Fig-a Scroll area

_________

(640/320)

SS'/!

ABCDE

ABC

1

23456

1234

r--

XYZ

Line S

~

OPORSTU

9876543

Fig-b Screen before scroll

SSA

ABCDE

A

BC

-

XYZ

OPORSTU

SEA

I--

9876543

Line S'

Fig-c Line after scroll

15

Execution of scrolling by address conversion

• Scroll offset (SOF) is the count

of

lines which the

CPU

gives

to

the

CRTC.

For instance, the

following

must

be observed

to

perform scrolling.

3-line scroll:

SOF

3 =

OF

x 3

5-line scroll:

SOF

5 =

OF

x 5

And,

to

scroll one

more

line after 5-line scroll;

5-line scroll:

SOF5'

= SOF5 +

OF

=

OF

x 6

Display screen

000

SOF

SSA

t----''-------------i

A Scroll screen

o SW

SEA

1-----1

OB

IF400

(FAOO)

• Display address DA is the signal created in the

CRTC

display address generation circuit and arranged in

their

order

from

the

upper

left corner

of

the screen.

The

bottom

right

address is 1

F400

in the 640 x

200

mode.

• Display

memory

address

DMA

represents the VRAM

address corresponding

to

DA.

Since scroll is executed by means

of

address conver-

sion, the

order

of

DMA

may

not

be

the same

as

DA,

necessarily.

•

CPU

address

MA

is the VRAM address

that

obtained

from

the

CPU

through

the

CRTC.

To lighten burden

on the CPU, a circuit is added

to

make order

of

DA

identical

to

order

of

MA

arrangement.

VRAM

~DMA

Fig-d Address conversion

4-2-6.

VRAM

data

input/output

circuit

1.

Nothing intervenes

for

input

and

output

of

data in the

case

of

the MZ-700 mode.

2.

MZ-800

mode

• Write

Read

data

(RD)

from

the VRAM and

write

data (WD)

from

the

CPU

are subjected

to

logical operation

accordi'1~

to

the direction

from

the

write

format

register (WF) and its result

is

written.

•

Read

For

plane read data from the VRAM, data to

be

read

by the

CPU

are arranged in accordance with the

direction

of

the read format register

(RF).

*Logic circuit

11"'0

-1

~".n.

•.

t.

11

)

\/eo

-1

t

Pl

IMII.IJJ,IV!

Read

data from the VRAM and write data from the

CPU

are subjected to logical operation

(OR,

XOR,

RESET,

etc.) and its result is used

for

the write data.

VRAM

acee

..

timing

1)

MZ-700 mode

See

separate page

for

display timing chart.

The

VRAM

is

configured in the following manner in

this instance.

VA

vc

(option)

$0000

Not used

$2000

Not

used

CG

area

$3000 TEXT area

ATB area

$3FFF

16

MZ-800

As the

PCG

method

is

adopted for the MZ-700 mode,

the text and ATB areas are actually mapped to $0000

-

$OFFF.

So, the VRAM address

has

the following

relation with the display character position.

1 2 3

40

:1::

1

0001

1-1

======t=a

I I I I I

I I I I I I

251

03CO

I I I

-_-_~~~~

2)

MZ-800 mode

As

the bit map method is used for the MZ-800 mode,

it

is possible to four screens

of

320

x

200

dots and

two

screens (maximum)

of

640'x

200

data.

The cycle steal method is used

for

this mode.

i)

320

x

200

dots

See

separate page

for

the timing chart

duing

display and

CPU

read timing.

What

i.

p.eudo

cycle steal

With the MZ-800, the pseudo cycle steal method is

adopted

for

VRAM accessing.

LOAO~

u

x:~~.

===:x

OISP.

addr

..

s X

cpu

address X

OISP.

add

re

..

I--

OISP.

clcle I

CPU

clcle I

OISP.

clcle

As shown in the figure, a next display data fetch and

CPU

accessing are multiplexed during a display period.

Because accessing

of

the VRAM while characters are on

display causes the screen to blink with the MZ-700

mode,

it

awaits

for

blinking to complete before

acces-

sing

of

the VRAM. But, with the cycle steal method it

enhances faster screen processing

as

it

enables to

access the VRAM during a display period. Because

it

is

not a complete cycle steal with the MZ-800 but timing is

taken using a

wait

in order to synchronize with the

CPU

cycle

for

accessing from the

CPU,

it

is therefore called

"pseudo cycle stealH•

•

MZ-800

ClK

VRAS

VCAS

VOE

VAD

0-7

VAO

-7

lOAD

MZ-700 MODE DISPLAY TIMING

56.3ns

r=:

451ns

...

1

~--------------~,

,'----

''-_----'I ,

~

ROW X

COL.

X ATB. adr. X ROW X COL. X

DUMMY

adr. • X X

'-----v-----'

'---'-'-'-''--''-'-----'

'---v----'

'----------'

~

__

-.J

'----

text

adr.

CG.

adr.

---

----

--~C=>>----<C=>>--------<C=>>------<c=>>-----

text

DATA ATB. DATA

CG.DATA

invalid

DATA

(shift register) '

....

-----'

,

....

_---

MZ-SOO

MODE (320 X 200 dot)

ClK

\

..

DISP.

cycle

.1

..

CPU

cycle

VRAS

-.J

\ \

VCAS \ \

VOE

\ \ \

VADO

-7

~

ROW

X

COL.

X

COL.

X ROW X

COL.

II

(IV)

plane adr.

I

(III)

plane adr.

CPU

adr. latch DATA

VCO

-7

------

C=>>-------<C=>>-------<C=>>---------<

I plane DATA

II

plane DATA

CPU

read DATA

VAO

- 7

---------C=>-----<C=>>-----<C=>~----------~

III

plane DATA

IV

plane DATA

CPU

read DATA

lOAD

, ,

17

•

1)

320 x 200 dots

See the figure

below

for

VRAM configuration and

CRT

character display position.

VA

ve

(option)

$0000

0 0

1 1

2 2

I

40

I

I Plane I I

I I

I

($1F3F)

7999

Not

used

$2000

0 0

1 1

2 2

I I

I

Plane

II

I I

I

7999

Not

used

$3FFF

2)

640 X

200

dots

Because

it

operates in the cycle steal mode,

two

bytes

of

display data are fetched

during

one byte

display cycle. (See the chart in separate page.)

See the figure

below

for

VRAM configuration and

CRT

character display position.

$0000

($1F3F)

$2000

($3F3F)

$3FFF

0

2

4

I

80

I

15988

Not

used

1---,

---

3

5

:

79

I

15999

Not

used

VA

(Plane

I)

0

2

4

I

--,---

3

:,

I

ve

(option)

(Plane

Ill)

>Plane

III

Plane

IV

18

2

;I:I

I I

: I

I I

I

2~

17960

(Raster)

2 3

2

40

---"DJ

~

I

----hd

7999

----

eRT display position

2 3 4 80

o I'I't'

I-~EJ

80

__

--l--H

I

200

"'-159-20--1---+-1

~::::::::::::::::::

i

'''''

I

eRT

display

position

•

MZ-800

800 MODE (640 X 200

dot)

DISP. cycle -I·

CPU

cycle

-I·

DISP. cycle

VRAS

,'---

___

----~I

\~--

__

----_~I

\'-----

VCAS

\'---~/

''---~

\~-----------~

\'-----

VOE

,'-------/ ,

VAD 0 - 7

~

ROW

X'__

__

CO_L_.

----'X'__

__

C_O_L._~'C~'__

______

_:_--~X

X'-

__

--,--_

'---;;~

N+1th

adr.

'------C~

~===N=+=-2th~ad-r.~~

VA 0 - 7

-------~~~----~~~----~<==>~------------------~

I plane N th DATA I plane

N+l

th DATA

cPU

read

DATA

vc

0 - 7

----------~~~----~~~----~<==>~---------------~

III

plane

Nth

DATA 1II plane

N+

1th DATA

CPU

read DATA

LOAD

(sift register)

LJ

CPU

and

VRAM

accessing

1.

Accessing

of

the

VRAM

by

the

CPU

is carried

out

in

the cycle steal

mode

(MZ-800

mode

only)

during

the

flyback period

of

the

display

under

the

control

of

the

CRT

controller.

2.

Even

when

there is

no

accessing

from

the

CPU

in

the

CPU

cycle, such

as

VRAS, VCAS, VOE, etc. are

outputted

in

the

timing

of

the

read cycle at all times.

3.

Write

to

the

VRAM is carried

out

after

logical opera-

tion

of

the

read and

write

data

by

means

of

the

read-modify-write

method.

But, in

the

case

of

the

320

x 200, 16-color

mode,

data are

written

in

two

CPU

cycles as

there

is a need

of

writing

to

Plane IV.

See separate

paper

for

timing

chart.

4.

CPU

wait

1)

Write

• As there is a

one-byte

buffer

in

the

CRT

controller,

write

to

the

VRAM

from

the

CPU is carried

out

through

the

buffer. But, actual

write

to

the

VRAM is

cpu

cycle

<D

done

by

the

CRT

controller.

Therefore,

there

would

be

no

need

of

wait

under

almost

any

condition

in

the

MZ-800

mode.

• Even in

the

MZ-700

mode,

wait

is issued

when

there

are

more

than

two

writes

in a

display

period.

Display

period

Flyback period

HBLN

~r-.-----------1.l"

'--

______

~:~~w:R-----LJ~<D~-----t-L----~®l--,~rl-,-:------

~t..._J

<D@

WAIT

------------4,,\

".)r.

)l"-----

'-

______

J

2)

Read

Wait

is issued

along

with

the

CPU

write

action

both

during

displaying

and

flyback

periods

to

perform

reading

operation

in

synchronization

with

the

CPU

cycle.

DISP. cycle

cpu

cycle@

~-

-I-

..

------.--------

-_.

r-'I

.~

------------

VRAS

-.J

\ \ r

VCAS

~

\

\~-----------

V

OE

~

\

VADO-7

~

ROW

X

COL.

~~~======~----x'--~~==x~====~x===~~~x

ROW

X'--

__

C_O_L.

_________

X

CPU

adr. latch

DATA

I.

III

plane DISP. adr.

11.

IV

plane

VRWR

L-.J

VA

0-7

----~CJ:J___{

I plane

)>--------<c=::)>-----c=>-~

read

DATA

write

DATA

VC

0,-7

-----~

1II plane

)>---------<c=::)>-----c=>>-----QD---(

IV plane

}--

19

DISP.

DATA

Sharp MZ-800 User manual

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