Texas Instruments TPS55165Q1-EVM User manual

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TPS5516xQ1-EVM Evaluation Module for 1-A Single-Inductor Buck-Boost-
Converter
User's Guide
SLVUAY1–November 2017
TPS5516xQ1-EVM Evaluation Module for 1-A Single-
Inductor Buck-Boost-Converter
The Texas Instruments TPS55160Q1-EVM and TPS55165Q1-EVM evaluation modules (EVMs) help
designers evaluate the operation and performance of the TPS55160-Q1 and TPS55165-Q1 1-A single-
inductor buck-boost converters. This user's guide describes how to set up and configure the EVMs for
operation. This document also provides the board layout, the schematic, and the bill of materials (BoM) for
the EVMs.
The TPS55160-Q1 device allows users to set the output voltage from 5.7 V to 9 V through a feedback-
divider. The TPS55165-Q1 device has a selectable output voltage of 5 V or 12 V.
Contents
1 Introduction ................................................................................................................... 3
2 Schematic, Bill of Materials, and Layout ................................................................................. 3
2.1 Schematic ........................................................................................................... 4
2.2 Bill of Materials...................................................................................................... 5
2.3 Layout and Component Placement............................................................................... 7
3 Setup and Operation ...................................................................................................... 11
3.1 Input and Output Connector Descriptions...................................................................... 11
3.2 Jumper Configuration............................................................................................. 12
3.3 Test Point Description ............................................................................................ 14
3.4 Basic Operation.................................................................................................... 15
4 Typical Performance....................................................................................................... 16
4.1 Efficiency ........................................................................................................... 16
4.2 Startup Waveforms................................................................................................ 16
4.3 Switch Node Waveforms in Buck Mode, Boost Mode, and in Buck-Boost Mode......................... 17
4.4 Load-Step Response ............................................................................................. 18
4.5 Line step response / Cranking support......................................................................... 19
5 Related Documentation.................................................................................................... 20
List of Figures
1 TPS55160Q1-EVM With Jumper Settings................................................................................ 3
2 TPS55165Q1-EVM With Jumper Settings................................................................................ 3
3 Schematic Diagram—No Variations ...................................................................................... 4
4 TPS55160Q1-EVM Schematic Diagram—Assembly Option .......................................................... 4
5 TPS55165Q1-EVM Schematic Diagram—Assembly Option........................................................... 5
6 Component Placement—Top .............................................................................................. 7
7 TPS55160Q1-EVM Top Layer—Overview ............................................................................... 8
8 TPS55165Q1-EVM Top Layer—Overview ............................................................................... 8
9 Component Placement—Bottom .......................................................................................... 9
10 TPS55160Q1-EVM Bottom Layer—Overview .......................................................................... 9
11 TPS55165Q1-EVM Bottom Layer—Overview ......................................................................... 10
12 Layout—Top Layer......................................................................................................... 10
13 Layout—Layer 2............................................................................................................ 10
14 Layout—Layer 3............................................................................................................ 10
15 Layout—Bottom Layer..................................................................................................... 10

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16 TPS55165Q1-EVM Showing Supply and Load Connections ........................................................ 11
17 Ignition Jumper Configuration Default: ON (Device powers up when power is applied).......................... 12
18 Power-Latch Jumper Configuration Default: LATCH .................................................................. 12
19 Spread Spectrum Enable Jumper Configuration Default: Jumper Installed, Spread Spectrum Disabled...... 13
20 Power-Good Delay Selection Jumper Configuration Default: Jumper Not Installed, 3-ms Delay ............... 13
21 Low-Power-Mode Enable Jumper Configuration Default: Jumper Set to PWM, LPM Prohibited ............... 13
22 Output Voltage Selection Jumper Configuration Default: 5 V for TPS55165-Q1 .................................. 14
23 Output Voltage Selection Jumper Configuration Default: 8 V for TPS55160-Q1, Configured by R6 and R7.. 14
24 Typical Efficiency for 5-V Output......................................................................................... 16
25 Typical Efficiency for 12-V Output ....................................................................................... 16
26 Startup When VIN is Already Present and IGN is Pulled High....................................................... 16
27 Startup With IGN Tied to VIN and Both Ramp Up..................................................................... 16
28 Switch-Nodes in Buck Mode (VVIN = 12 V, VVOUT = 5 V) ............................................................... 17
29 Switch-Nodes in Buck-Boost-Mode (VVIN = 5 V, VVOUT = 5 V)......................................................... 17
30 Switch-Nodes in Boost Mode (VVIN = 2.5 V, VVOUT = 5 V).............................................................. 17
31 Load-Step Response VVIN = 12 V, VVOUT = 5 V (Buck Mode), 100 mA-1 A-100 mA ............................... 18
32 Load-Step Response VVIN = 2.5 V, VVOUT = 5 V (Boost Mode), 50 mA-400 mA-50 mA ........................... 18
33 Load-Step Response VVIN = 14 V, VVOUT = 12 V (Buck Mode), 100 mA-800 mA-100 mA ........................ 18
34 Load-Step Response VVIN = 12 V, VVOUT = 12 V (Buck-Boost Mode), 100 mA-600 mA-100 mA................. 18
35 Load-step-response VVIN = 4 V, VVOUT = 12 V (Boost Mode), 50 mA-150 mA-50 mA ............................. 18
36 Cranking Pulse Response With 5-V Output, 200-mA Load, 2 s/div................................................. 19
37 Cranking Pulse Response With 5-V Output, 200-mA Load, Zoom to 100 ms/div................................. 19
38 Cranking Pulse Response With 5-V Output, 200-mA Load, Zoom to 5 ms/div.................................... 19
39 Cranking Pulse Response With 5-V Output, 200-mA load, Zoom to 200 µs/div................................... 19
List of Tables
1 Bill of Materials (BOM) ..................................................................................................... 5
2 Terminal Descriptions...................................................................................................... 11
Trademarks
All trademarks are the property of their respective owners.

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TPS5516xQ1-EVM Evaluation Module for 1-A Single-Inductor Buck-Boost-
Converter
1 Introduction
The HVL143B is a fully-assembled EVM design for evaluation of TPS55165-Q1 or TPS55160-Q1 1-A
single-inductor buck-boost converter. Figure 1 and Figure 2 show the TPS55160Q1-EVM and
TPS55165Q1-EVM boards with jumper settings.
Figure 1. TPS55160Q1-EVM With Jumper Settings
Figure 2. TPS55165Q1-EVM With Jumper Settings
2 Schematic, Bill of Materials, and Layout
This section provides a more detailed description of the schematic, bill of materials (BOM), and layout.

100k
R4
PG_DLY
PG
VREG
L2
VBAT_F VOUTTP5
PG
TP6
VREG
VOS_FB
PGND 1
VINP
4
VINL
5
IGN
6
PS
7
IGN_PWRL
8SS_EN 9
PG_DLY 10
VREG_Q 11
VREG 12
GND 13
VOS_FB 14
PG 15
VOUT_SENSE 16
VOUT 17
GND 18
PAD 21
L1
2
BST1
3
BST2
19
L2
20
U1
TPS55165PWPQ1
BST1
L1
VREG
VREG
VREG
BST2
TP7
GND
10.0k
R3
D2
DNP
VOUT
VOUT
VOUT
1.00k
R1
DNP 1.00k
R2
DNP
4V - 36V (12V output)
2V - 36V (5V output)
5V / 12V / adjustable
1A (buck mode only,
4.7µH
L2
0.1µF
C8
0.1µF
C12
0.1µF
C13
9.09k
R7
DNP
82.5k
R6
DNP
0.01µF
C9
DNP
0.01µF
C10
DNP
0.47µF
C11
0.1µF
C15
TP1
VBAT
TP2
Vbat_GND
TP3
VOUT
TP4
Vout_GND
4.7µF
C14
D1
DNP
10µF
C3
10µF
C4
PGND PGNDPGND PGND
reduced in boost-mode)
PGND PGND PGND
PGND
PGND
PGND
PGND
PGND
VBAT
10µF
C6
10µF
C7
1
2
3
LPM
PWM
J5
PS
1
2
3
UNLATCH
LATCH
J2
IGN_PWRL
1
2
3
ON
OFF
J1
IGN
100µF
C5
0.1µF
C2
2.2µHL1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND PGND
PGND
PGND
PGND
PGND
1
2
3
3ms
40ms
0.6ms
J4
PG_DLY
1
2
J3
SS_EN
0.01µF
C1
DNP
0.01µF
C22
DNP
10µF
C19
DNP
PGND
0
R5
VREG
PGND
1
2
3
5V
12V
J6
Vout_Set
0.1µF
C21
2.2µF
C20
10µF
C16
10µF
C17
10µF
C18
DNP
Copyright © 2017, Texas Instruments Incorporated
100k
R4
PG_DLY
PG
VREG
L2
VBAT_F VOUTTP5
PG
TP6
VREG
VOS_FB
PGND 1
VINP
4
VINL
5
IGN
6
PS
7
IGN_PWRL
8SS_EN 9
PG_DLY 10
VREG_Q 11
VREG 12
GND 13
VOS_FB 14
PG 15
VOUT_SENSE 16
VOUT 17
GND 18
PAD 21
L1
2
BST1
3
BST2
19
L2
20
U1
TPS55165PWPQ1
BST1
L1
VREG
VREG
VREG
BST2
TP7
GND
10.0k
R3
D2
VOUT
VOUT
VOUT
1.00k
R1
1.00k
R2
4V - 36V (12V output)
2V - 36V (5V output)
5V / 12V / adjustable
1A (buck mode only,
4.7µH
L2
0.1µF
C8
0.1µF
C12
0.1µF
C13
9.09k
R7
82.5k
R6
0.01µF
C9
0.01µF
C10
0.47µF
C11
0.1µF
C15
TP1
VBAT
TP2
Vbat_GND
TP3
VOUT
TP4
Vout_GND
4.7µF
C14
D1
10µF
C3
10µF
C4
PGND PGNDPGND PGND
reduced in boost-mode)
PGND PGND PGND
PGND
PGND
PGND
PGND
PGND
VBAT
10µF
C6
10µF
C7
1
2
3
LPM
PWM
J5
PS
1
2
3
UNLATCH
LATCH
J2
IGN_PWRL
1
2
3
ON
OFF
J1
IGN
100µF
C5
0.1µF
C2
2.2µHL1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND PGND
PGND
PGND
PGND
PGND
1
2
3
3ms
40ms
0.6ms
J4
PG_DLY
1
2
J3
SS_EN
0.01µF
C1
0.01µF
C22
10µF
C19
PGND
0
R5
VREG
PGND
1
2
3
5V
12V
J6
Vout_Set
0.1µF
C21
2.2µF
C20
10µF
C16
10µF
C17
10µF
C18
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2.1 Schematic
Figure 3. Schematic Diagram—No Variations
Figure 4. TPS55160Q1-EVM Schematic Diagram—Assembly Option

100k
R4
PG_DLY
PG
VREG
L2
VBAT_F VOUTTP5
PG
TP6
VREG
VOS_FB
PGND 1
VINP
4
VINL
5
IGN
6
PS
7
IGN_PWRL
8SS_EN 9
PG_DLY 10
VREG_Q 11
VREG 12
GND 13
VOS_FB 14
PG 15
VOUT_SENSE 16
VOUT 17
GND 18
PAD 21
L1
2
BST1
3
BST2
19
L2
20
U1
TPS55160PWPQ1
BST1
L1
VREG
VREG
VREG
BST2
TP7
GND
10.0k
R3
D2
DNP
VOUT
VOUT
VOUT
1.00k
R1
DNP 1.00k
R2
DNP
4V - 36V (12V output)
2V - 36V (5V output)
5V / 12V / adjustable
1A (buck mode only,
4.7µH
L2
0.1µF
C8
0.1µF
C12
0.1µF
C13
9.09k
R7
82.5k
R6
0.01µF
C9
DNP
0.01µF
C10
DNP
0.47µF
C11
0.1µF
C15
TP1
VBAT
TP2
Vbat_GND
TP3
VOUT
TP4
Vout_GND
4.7µF
C14
D1
DNP
10µF
C3
10µF
C4
PGND PGNDPGND PGND
reduced in boost-mode)
PGND PGND PGND
PGND
PGND
PGND
PGND
PGND
VBAT
10µF
C6
10µF
C7
1
2
3
LPM
PWM
J5
PS
1
2
3
UNLATCH
LATCH
J2
IGN_PWRL
1
2
3
ON
OFF
J1
IGN
100µF
C5
0.1µF
C2
2.2µHL1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND PGND
PGND
PGND
PGND
PGND
1
2
3
3ms
40ms
0.6ms
J4
PG_DLY
1
2
J3
SS_EN
0.01µF
C1
DNP
0.01µF
C22
DNP
10µF
C19
DNP
PGND
0
R5
DNP
VREG
PGND
1
2
3
5V
12V
J6
Vout_Set
DNP
0.1µF
C21
2.2µF
C20
10µF
C16
10µF
C17
10µF
C18
DNP
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Figure 5. TPS55165Q1-EVM Schematic Diagram—Assembly Option
2.2 Bill of Materials
Table 1. Bill of Materials (BOM)
Designator
Quantityfor
TPS55165Q
1-EVM
(Variant
001)
Quantityfor
TPS55160Q
1-EVM
(Variant
002)
Value Description Package Reference Part Number Manufacturer
!PCB 1 1 Printed Circuit Board HVL143 Any
C2, C8, C12, C13, C15,
C21 6 6 0.1 µF CAP, CERM, 0.1 µF, 50 V, ± 10%, X7R, 0603 0603 GCM188R71H104KA57D MuRata
C3, C4, C6, C7, C16, C17 6 6 10 µF CAP, CERM, 10 µF, 50 V, ± 10%, X7R, AEC-Q200
Grade 1, 2220 2220 CGA9N3X7R1H106K230KB TDK
C5 1 1 100 µF CAP, AL, 100 µF, 50 V, ± 20%, 0.3 ohm, SMD SMT Radial G EEE-FC1H101P Panasonic
C11 1 1 0.47 µF CAP, CERM, 0.47 µF, 50 V, +/- 10%, X7R, AEC-Q200
Grade 1, 0603 0603 CGA3E3X7R1H474K080AE TDK
C14 1 1 4.7 µF CAP, CERM, 4.7 µF, 16 V, ± 10%, X7R, AEC-Q200
Grade 1, 0805 0805 GCM21BR71C475KA73K MuRata
C20 1 1 2.2 µF CAP, CERM, 2.2 µF, 50 V, +/- 10%, X7R, AEC-Q200
Grade 1, 1206 1206 GCM31CR71H225KA55L MuRata
FID1, FID2, FID3, FID4,
FID5, FID6 6 6 Fiducial mark. There is nothing to buy or mount. N/A N/A N/A
H9, H10, H11, H12 4 4 Bumpon, Hemisphere, 0.44 X 0.20, Clear Transparent Bumpon SJ-5303 (CLEAR) 3M
J1 1 1 ON Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1, TH HTSW-103-07-G-S Samtec
J2 1 1 Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1, TH HTSW-102-07-G-S Samtec

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Table 1. Bill of Materials (BOM) (continued)
Designator
Quantityfor
TPS55165Q
1-EVM
(Variant
001)
Quantityfor
TPS55160Q
1-EVM
(Variant
002)
Value Description Package Reference Part Number Manufacturer
J3 1 1 Header, 100mil, 2x1, Gold, TH Header, 100mil, 2x1, TH HTSW-103-07-G-S Samtec
J4 1 1 3 ms Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1, TH HTSW-103-07-G-S Samtec
J5 1 1 LPM Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1, TH HTSW-103-07-G-S Samtec
J6 1 0 5 V Header, 100mil, 3x1, Gold, TH Header, 100mil, 3x1, TH HTSW-103-07-G-S Samtec
L1 1 1 2.2 µH Inductor, Shielded, Powdered Iron, 2.2 µH, 4.7 A, 0.035
ohm, AEC-Q200 Grade 1, SMD 4.1x4.1mm 78438356022 Wurth Elektronik
L2 1 1 4.7 µH Inductor, Wirewound, 4.7 µH, 5.5 A, 0.04 ohm, AEC-
Q200 Grade 0, SMD 7.3 x 6.6 mm SRP7028A-4R7M Bourns
LBL1 1 1 Thermal Transfer Printable Labels, 0.650" W x 0.200" H
- 10,000 per roll PCB Label 0.650 x 0.200 inch THT-14-423-10 Brady
R3 1 1 10.0 k RES, 10.0 k, 1%, 0.1 W, 0603 0603 CRCW060310K0FKEA Vishay-Dale
R4 1 1 100 k RES, 100 k, 5%, 0.1 W, 0603 0603 CRCW0603100KJNEA Vishay-Dale
R5 1 0 0 RES, 0, 5%, 0.063 W, 0402 0402 CRCW04020000Z0ED Vishay-Dale
R6 0 1 82.5 k RES, 82.5 k, 1%, 0.1 W, 0603 0603 CRCW060382K5FKEA Vishay-Dale
R7 0 1 9.09 k RES, 9.09 k, 1%, 0.1 W, 0603 0603 CRCW06039K09FKEA Vishay-Dale
SH-J1, SH-J2, SH-J3, SH-
J4, SH-J5 5 5 1 × 2 Shunt, 100mil, Gold plated, Black Shunt 969102-0000-DA 3M
TP1, TP2, TP3, TP4 4 4 PCB Pin, Swage Mount, TH PCB Pin (2505-2) 2505-2-00-44-00-00-07-0 Mill-Max
TP5, TP6, TP7 3 3 Test Point, Miniature, SMT Test Point, Miniature, SMT 5019 Keystone
U1 1 1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator, PWP0020P
(TSSOP-20) PWP0020P TPS55165PWPQ1 Texas Instruments
C1, C9, C10, C22 0 0 0.01 µF CAP, CERM, 0.01 µF, 50 V, +/- 10%, X7R, AEC-Q200
Grade 1, 0603 0603 GCM188R71H103KA37D MuRata
C18, C19 0 0 10 µF CAP, CERM, 10 µF, 50 V, +/- 10%, X7R, AEC-Q200
Grade 1, 2220 2220 CGA9N3X7R1H106K230KB TDK
D1, D2 0 0 60 V Diode, Schottky, 60 V, 1 A, SOD-123F SOD-123F PMEG6010CEH,115 Nexperia
H1, H2, H3, H4 0 0 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips
panhead Screw NY PMS 440 0025 PH B & F Fastener Supply
H5, H6, H7, H8 0 0 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
R1, R2 0 0 1.00 k RES, 1.00 k, 1%, 0.1 W, 0603 0603 CRCW06031K00FKEA Vishay-Dale
R6 0 0 82.5 k RES, 82.5 k, 1%, 0.1 W, 0603 0603 CRCW060382K5FKEA Vishay-Dale
R7 0 0 9.09 k RES, 9.09 k, 1%, 0.1 W, 0603 0603 CRCW06039K09FKEA Vishay-Dale

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2.3 Layout and Component Placement
The TPS55160Q1-EVM and TPS55165Q1-EVM share the same PCB which is named HVL143B.
The C1, C18, C19, and C22 capacitors are not installed. Their footprints allow for additional input
decoupling or bulk capacitance.
The R6 and R7 resistors are not populated on the TPS55165Q1-EVM. Select the output voltage of either
5V or 12V using J6, which is named Vout_Set.
The R6 and R7 resistors are populated on the TPS55160Q1-EVM. These resistors set the output voltage
to 8V. To eliminate the long trace to the J6jumper, which is prone to pick up noise, the R5 resistor and J6
jumper are not assembled on the TPS55160Q1-EVM.
Figure 4,Figure 7, and Figure 8 show the top layout of the EVM, with assembly options for the fixed
voltage version (TPS55165Q1-EVM) at the adjustable voltage version (TPS55160Q1-EVM).
Figure 6. Component Placement—Top

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Figure 7. TPS55160Q1-EVM Top Layer—Overview
Figure 8. TPS55165Q1-EVM Top Layer—Overview

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Figure 9,Figure 10, and Figure 11 show the bottom layout of the EVM, with assembly options for the fixed
voltage version (TPS55165Q1-EVM) at the adjustable voltage version (TPS55160Q1-EVM).
Figure 9. Component Placement—Bottom
Figure 10. TPS55160Q1-EVM Bottom Layer—Overview

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Figure 11. TPS55165Q1-EVM Bottom Layer—Overview
Figure 12,Figure 13,Figure 14, and Figure 15 show the EVM board layers.
Figure 12. Layout—Top Layer Figure 13. Layout—Layer 2
Figure 14. Layout—Layer 3 Figure 15. Layout—Bottom Layer

Load +
Load GND
Supply Line +
Supply Line GND
TPS55165EVM
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TPS5516xQ1-EVM Evaluation Module for 1-A Single-Inductor Buck-Boost-
Converter
3 Setup and Operation
This section describes the setup and configuration of the EVM for basic operation. This section provides a
detailed description of connectors, jumpers, and test points. A description of the typical operation of the
EVM is also included.
3.1 Input and Output Connector Descriptions
The EVM has one pair of connectors (turrets) for the input and one pair for the output. Table 2lists all the
connectors with their functional description and electrical specification.
(1) The initial startup voltage is 5.3 V (typical).
(2) In boost-mode and for higher output voltages, the maximum output current is decreased. For details, refer to the TPS5516x-Q1
36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step- Down Voltage Regulator data sheet .
Table 2. Terminal Descriptions
TERMINAL DIRECTION DESCRIPTION
VBAT (TP1) and Vbat_GND (TP2) Input These terminals are the supply-voltage
input for the buck-boost converter. The
terminals accept an input voltage between
2 V and 36 V.(1)
VOUT (TP3) and Vout_GND (TP4) Output
VOUT is the output voltage of the buck-
boost regulator and supplies 5V or 12V for
the TPS55165-Q1 device, depending on
the Vout_Set setting.
For the TPS55160-Q1 device, the default
output voltage is 8V. The selection of the
R6 and R7 resistors determines the output
voltage.
The device delivers a maximum output
current of 1 A in buck-mode for a 5-V
output. (2)
Figure 16. TPS55165Q1-EVM Showing Supply and Load Connections

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3.2 Jumper Configuration
3.2.1 IGN
The IGN jumper enables the device. By default, this jumper is set to the ONposition. Put this jumper in the
OFFposition to disable the output.
NOTE: The enable and disable thresholds of this pin are higher than the minimum supply voltage
(VBAT) that this pin is tied to. The boost itself supports a VBAT supply voltage of 2 V, but the
device is disabled if the IGN pin is connected to the VBAT pin. To prevent a shutdown event
in this scenario, apply a voltage higher than 3.7 V to the center pin of this jumper or keep the
device latched (set the IGN_PWRL jumper to LATCH).
Figure 17. Ignition Jumper Configuration
Default: ON (Device powers up when power is applied)
3.2.2 IGN_PWRL
The IGN_PWRL jumper keeps the device on even if the IGN pin goes low (power-latch function) after the
device is enabled by a high signal on the IGN pin. The IGN_PWRL jumper resembles an external MCU
signal to keep the TPS5516x-Q1 on after the IGN pin goes low. The default setting of this jumper is
LATCH. To disable the latch, move the jumper to UNLATCH.
NOTE: This pin does not enable the device. To activate the regulator, set the IGN to ON (see the
IGN description in Section 3.2.1). The purpose of the IGN_PWRL jumper is only as a keep-
alive to keep the device on.
Figure 18. Power-Latch Jumper Configuration
Default: LATCH
3.2.3 SS_EN
The SS_EN jumper selects if spread-spectrum modulation is enabled. If enabled, spread-spectrum
modulation reduces the harmonic peak amplitude. The default of this jumper is DIS-ABLED (spread
spectrum disabled). The jumper is installed by default.
NOTE: Spread spectrum modulation is only active in normal mode when the device is in step-down
(buck) operation.
To make a jumper change effective, power cycle the supply or turn off the output (move the
IGN jumper to OFF while the device is unlatched).

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Figure 19. Spread Spectrum Enable Jumper Configuration
Default: Jumper Installed, Spread Spectrum Disabled
3.2.4 PG_DLY
The PG_DLY jumper sets the power-good delay time. This time defines how long before the power-good
pin (PG pin, TP3) goes low after the output voltage decreases to less than the PG undervoltage threshold
(PGTH_UV). The default of this jumper is 3ms (no jumper installed).
Figure 20. Power-Good Delay Selection Jumper Configuration
Default: Jumper Not Installed, 3-ms Delay
3.2.5 PS
The PS jumper selects between low-power mode (LPM) and pulse-width modulation (PWM). The default
of this jumper is PWM.
Figure 21. Low-Power-Mode Enable Jumper Configuration
Default: Jumper Set to PWM, LPM Prohibited
3.2.6 Vout_Set
The Vout_Set jumper selects the output voltage for the TPS5516x-Q1 device. For the TPS55165-Q1
device, the default of this jumper is 5V. Move this jumper to 12V select the 12-V output voltage. If no
jumper is installed, the output voltage defaults to 5 V.
NOTE: To make a jumper change effective, power cycle the supply or turn off the output (move the
IGN jumper to OFF while the device is unlatched).

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Figure 22. Output Voltage Selection Jumper Configuration
Default: 5 V for TPS55165-Q1
The TPS55160-Q1 variant does not have this jumper installed because the output voltage is set by the
resistive divider formed by the R6 and R7 resistors on the bottom side of the board. The installed
components set the output voltage to 8 V.
Figure 23. Output Voltage Selection Jumper Configuration
Default: 8 V for TPS55160-Q1, Configured by R6 and R7
3.3 Test Point Description
The test points are defined as:
TP5 (PG)— This test point measures the power-good output of the buck-boost converter.
TP6 (VREG)— This test point measures the internal voltage on the VREG pin of the device.
TP7 (GND)— Connect ground-test leads to this test point for sensitive measurements.
The output voltage can be measured at the turrets provided for the output.

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3.4 Basic Operation
The input voltage range for the converter is from 2 V to 36 V (5.3 V typical minimum for initial start-up).
For operation of TPS5516xQ1-EVM, configure the jumpers in the default configuration:
• IGN = ON
• IGN_PWRL = Irrelevant as long as the IGN jumper is set to ON (the default of the IGN_PWRL jumper
is LATCH)
• SS_EN = Irrelevant for basic operation (default: jumper installed, SS disabled)
• PG_DLY = Irrelevant for basic operation (default: jumper not installed, 3 ms delay)
• PS = PWM
• Vout_Set = (TPS55165-Q1-variant only) Desired output voltage (set this jumper before setting the IGN
jumper to ON; the default of the Vout_Set jumper is 5 V for the TPS55165-Q1)
If input voltage is present, the EVM with this configuration delivers an output voltage of 5 V for the
TPS55165-Q1 device and 8 V for the TPS55160-Q1 device.
NOTE: In buck mode, the TPS5516x-Q1 device can drive up to 1 A. In boost mode, the maximum
output current scales with the input and output voltage (refer to the TPS5516x-Q1 36-V, 1-A
Output, 2-MHz, Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator
data sheet).
To change the output voltage on the TPS55165Q1-EVM, follow these steps:
1. Power down the device.
2. Move the Vout_Set jumper to the new position.
3. Power up the device.
The output voltage can also be changed by following these steps on the TPS55165Q1-EVM:
1. Move the IGN jumper to the OFF setting while the device is unlatched.
2. Move the Vout_Set jumper to the new position.
3. Move the IGN jumper to the ON setting.
If the jumper moves while power is applied and the IGN pin is high or latched, the change in output
voltage does not take effect.
To change the output voltage for the adjustable TPS55160-Q1 device, change the resistive divider. Use
Equation 1 to calculate the resistor values to change the output voltage.
(1)
Assuming the desired output voltage is 8 V and R7 is chosen as 10 kΩ, the value of the R6 resistor is
calculated for a desired output voltage as shown in Equation 2.
(2)
NOTE: To allow for a suitable feedback current, the total divider resistance must not exceed 1 MΩ.
If the IGN jumper is moved to the OFF position, the device turns off the output if the the IGN_PWRL
jumper is unlatched. To keep the device active when the IGN goes low, set the IGN_PWRL jumper to the
LATCH position.
If the the IGN_PWRL jumper is latched, the output remains active until the power supply is turned off or
the IGN_PWRL jumper is moved to the UNLATCH position while the IGN pin is low.
After the supply is turned on, move the IGN jumper to the ON position to turn on the output again, even if
the IGN_PWRL jumper is latched.

Load Current (A)
Efficiency
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
D001
36-V Supply Voltage
18-V Supply Voltage
12-V Supply Voltage
5-V Supply Voltage
3-V Supply Voltage
Load Current (A)
Efficiency
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
D002
36-V Supply Voltage
18-V Supply Voltage
12-V Supply Voltage
9-V Supply Voltage
5-V Supply Voltage
4-V Supply Voltage
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The default configuration disables spread-spectrum modulation. To mitigate emissions enable spread-
spectrum modulation by removing the jumper on SS_EN and power cycling or turning off and on the IGN
jumper while unlatched.
The PG_DLY jumper sets the delay time of the PG output. The default is 3 ms. The PG delay time can be
decreased 0.6 ms or increased 40 ms. To change the PG delay time, install the jumper in the respective
position. This configuration refers to the PGexttime time (refer to the TPS5516x-Q1 36-V, 1-A Output, 2-MHz,
Single Inductor, Synchronous Step-Up and Step-Down Voltage Regulator). The PG pin is not asserted low
if the output voltage decreases to less than the PGTH_UV threshold for a time shorter than the PGexttime
time. If the supply voltage is decreased, follow the limited output current constraints for a given input-
voltage to output-voltage ratio (for details refer to the TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single
Inductor, Synchronous Step-Up and Step-Down Voltage Regulator).
For shutdown, no special requirements apply.
4 Typical Performance
4.1 Efficiency
Figure 24 and Figure 25 show the graphs for typical efficiency.
Figure 24. Typical Efficiency for 5-V Output Figure 25. Typical Efficiency for 12-V Output
4.2 Startup Waveforms
Figure 26 and Figure 27 show the typical startup behavior for a 5-V output.
Figure 26. Startup When VIN is Already Present and IGN is
Pulled High Figure 27. Startup With IGN Tied to VIN and Both Ramp Up

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4.3 Switch Node Waveforms in Buck Mode, Boost Mode, and in Buck-Boost Mode
The following graphs show the switch-nodes in the various modes. The modes are determined by the ratio
of input voltage to output voltage. In buck mode and boost mode, the device switches at 2 MHz. In buck-
boost, both nodes switch interleaved, resulting in a 1-MHz switching frequency per node.
Figure 28. Switch-Nodes in Buck Mode (VVIN = 12 V, VVOUT =
5 V) Figure 29. Switch-Nodes in Buck-Boost-Mode (VVIN = 5 V,
VVOUT = 5 V)
Figure 30. Switch-Nodes in Boost Mode (VVIN = 2.5 V, VVOUT = 5 V)

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4.4 Load-Step Response
The following graphs show the load-step responses as taken on the EVM.
NOTE: Different slew-rates, capacitive loading, filtering, and other setups can result in different
results (for example, ramp times of several 100 µs decrease the dips to « 100 mV).
Figure 31. Load-Step Response
VVIN = 12 V, VVOUT = 5 V (Buck Mode), 100 mA-1 A-100 mA Figure 32. Load-Step Response VVIN = 2.5 V, VVOUT = 5 V (Boost Mode), 50 mA-400 mA-50
mA
Figure 33. Load-Step Response
VVIN = 14 V, VVOUT = 12 V (Buck Mode), 100 mA-800 mA-100
mA
Figure 34. Load-Step Response
VVIN = 12 V, VVOUT = 12 V (Buck-Boost Mode), 100 mA-600
mA-100 mA

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Figure 35. Load-step-response
VVIN = 4 V, VVOUT = 12 V (Boost Mode), 50 mA-150 mA-50 mA
4.5 Line step response / Cranking support
The following graphs show the response of the part to the cold-crank pulse as defined in the OEM
specification LV124. The pulse decreases to 3 V, followed by some ringing before recovering to normal
input voltage.
These graphs are with a 5-V output at 200-mA load.
Figure 36. Cranking Pulse Response With 5-V Output, 200-
mA Load, 2 s/div Figure 37. Cranking Pulse Response With 5-V Output, 200- mA Load, Zoom to 100 ms/div
Figure 38. Cranking Pulse Response With 5-V Output, 200-
mA Load, Zoom to 5 ms/div Figure 39. Cranking Pulse Response With 5-V Output, 200-
mA load, Zoom to 200 µs/div

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5 Related Documentation
Texas Instruments, TPS5516x-Q1 36-V, 1-A Output, 2-MHz, Single Inductor, Synchronous Step-Up and
Step-Down Voltage Regulator data sheet