Toshiba TMPR4925 User manual

64-Bit TX System RISC
TX49 Family
TMPR4925
Rev. 3.0

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for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
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© 2004 TOSHIBA CORPORATION
All Rights Reserved

Preface
Thank you for new or continued patronage of TOSHIBA semiconductor products. This is the 2003
edition of the user’s manual for the TMPR4925 64-bit RISC microprocessor.
This databook is written so as to be accessible to engineers who may be designing a TOSHIBA
microprocessor into their products for the first time. No prior knowledge of this device is assumed. What
we offer here is basic information about the microprocessor, a discussion of the application fields in
which the microprocessor is utilized, and an overview of design methods. On the other hand, the more
experienced designer will find complete technical specifications for this product.
Toshiba continually updates its technical information. Your comments and suggestions concerning this
and other Toshiba documents are sincerely appreciated and may be utilized in subsequent editions. For
updating of the data in this manual, or for additional information about the product appearing in it, please
contact your nearest Toshiba office or authorized Toshiba dealer.
September 2004

Table of Contents
i
Table of Contents
Handling Precautions
TX4925
1. Features................................................................................................................................................................... 1-1
1.1 Outline ........................................................................................................................................................... 1-1
1.2 Features.......................................................................................................................................................... 1-2
1.2.1 TX49/H2 Processor Core Features........................................................................................................ 1-2
1.2.2 TX4925 Peripheral Circuit Features...................................................................................................... 1-3
2. Block Diagram........................................................................................................................................................ 2-1
2.1 TX4925 Block Diagram................................................................................................................................. 2-1
3. Signals .................................................................................................................................................................... 3-1
3.1 Pin Signal Description ................................................................................................................................... 3-1
3.1.1 Signals Common to SDRAM and External Bus Interfaces................................................................... 3-1
3.1.2 SDRAM Interface Signals..................................................................................................................... 3-2
3.1.3 External Interface Signals ..................................................................................................................... 3-3
3.1.4 DMA Interface Signals.......................................................................................................................... 3-5
3.1.5 PCI Interface Signals............................................................................................................................. 3-5
3.1.6 Serial I/O Interface Signals ................................................................................................................... 3-7
3.1.7 Timer Interface Signals ......................................................................................................................... 3-7
3.1.8 Parallel I/O Interface Signals ................................................................................................................ 3-7
3.1.9 AC-link Interface Signals...................................................................................................................... 3-8
3.1.10 Interrupt Signals.................................................................................................................................... 3-8
3.1.11 CHI Interface Signals............................................................................................................................ 3-8
3.1.12 SPI Interface Signals............................................................................................................................. 3-9
3.1.13 NAND Flash Memory Interface Signals............................................................................................... 3-9
3.1.14 Extended EJTAG Interface Signals....................................................................................................... 3-9
3.1.15 Clock Signals ...................................................................................................................................... 3-10
3.1.16 Initialization Signals............................................................................................................................ 3-10
3.1.17 Test Signals ......................................................................................................................................... 3-11
3.1.18 Power Supply Pins .............................................................................................................................. 3-11
3.2 Boot Configuration ...................................................................................................................................... 3-12
3.3 Pin Multiplexing .......................................................................................................................................... 3-15
4. Address Mapping.................................................................................................................................................... 4-1
4.1 TX4925 Physical Address Map...................................................................................................................... 4-1
4.2 Register Map.................................................................................................................................................. 4-2
4.2.1 Addressing............................................................................................................................................. 4-2
4.2.2 Ways toAccess to Internal Registers..................................................................................................... 4-2
4.2.3 Register Map......................................................................................................................................... 4-3
5. Configuration Register............................................................................................................................................ 5-1
5.1 Outline ........................................................................................................................................................... 5-1
5.1.1 Detecting G-Bus Timeout...................................................................................................................... 5-1
5.2 Register .......................................................................................................................................................... 5-2
5.2.1 Chip Configuration Register (CCFG) 0xE000..................................................................................... 5-3
5.2.2 Chip Revision ID Register (REVID) 0xE004 ....................................................................................... 5-5
5.2.3 Pin Configuration Register (PCFG) 0xE008........................................................................................ 5-6
5.2.4 Timeout Error Access Address Register (TOEA) 0xE00C................................................................... 5-8
5.2.5 Power Down Control Register (PDNCTR) 0xE010.............................................................................5-9
5.2.6 GBUSArbiter Priority Register (GARBP) 0xE018 ............................................................................5-10
5.2.7 Timeout Count Register (TOCNT) 0xE020 ....................................................................................... 5-10
5.2.8 DMA Request Control Register (DRQCTR) 0xE024 ........................................................................ 5-11
5.2.9 Clock Control Register (CLKCTR) 0xE028...................................................................................... 5-12
5.2.10 GBUS Arbiter Control Register (GARBC) 0xE02C........................................................................... 5-14

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ii
5.2.11 RegisterAddress Mapping Register (RAMP) 0xE030....................................................................... 5-14
6. Clocks..................................................................................................................................................................... 6-1
6.1 TX4925 Clock Signals................................................................................................................................... 6-1
6.2 Power-Down Mode........................................................................................................................................ 6-5
6.2.1 Halt Mode and Doze Mode................................................................................................................... 6-5
6.2.2 Power Reduction for Peripheral Modules ............................................................................................. 6-5
6.2.3 Power-Down Mode ............................................................................................................................... 6-5
6.3 Power-On Sequence....................................................................................................................................... 6-6
7. External Bus Controller.......................................................................................................................................... 7-1
7.1 Features.......................................................................................................................................................... 7-1
7.2 Block Diagram............................................................................................................................................... 7-2
7.3 Detailed Explanation...................................................................................................................................... 7-3
7.3.1 External Bus Control Register............................................................................................................... 7-3
7.3.2 Global/Boot-up Options........................................................................................................................ 7-4
7.3.3 Address Mapping .................................................................................................................................. 7-5
7.3.4 External Address Output ....................................................................................................................... 7-6
7.3.5 Data Bus Size........................................................................................................................................ 7-7
7.3.6 Access Modes........................................................................................................................................ 7-9
7.3.7 Access Timing..................................................................................................................................... 7-13
7.3.8 Clock Options...................................................................................................................................... 7-19
7.3.9 PCMCIA mode.................................................................................................................................... 7-20
7.4 Register ........................................................................................................................................................ 7-24
7.4.1 External Bus Channel Control Register (EBCCRn) 0x9000 (ch. 0), 0x9008 (ch. 1)
0x9010 (ch. 2), 0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7)....... 7-25
7.4.2 External Bus Base Address Register (EBBARn) 0x9000 (ch. 0), 0x9008 (ch. 1) 0x9010 (ch. 2),
0x9018 (ch. 3) 0x9020 (ch. 4), 0x9028 (ch. 5) 0x9030 (ch. 6), 0x9038 (ch. 7) ................................ 7-28
7.5 Timing Diagrams ......................................................................................................................................... 7-29
7.5.1 UAE Signal ......................................................................................................................................... 7-30
7.5.2 Normal Mode Access (Single, 32-bit Bus).......................................................................................... 7-32
7.5.3 Normal Mode Access (Burst, 32-bit Bus) ........................................................................................... 7-36
7.5.4 Normal Mode Access (Single, 16-bit Bus).......................................................................................... 7-38
7.5.5 Normal Mode Access (Burst, 16-bit Bus) ........................................................................................... 7-42
7.5.6 Normal Mode Access (Single, 8-bit Bus)............................................................................................ 7-44
7.5.7 Normal Mode Access (Burst, 8-bit Bus) ............................................................................................. 7-47
7.5.8 Page Mode Access (Burst, 32-bit Bus)................................................................................................ 7-49
7.5.9 External ACK Mode Access (32-bit Bus) ...........................................................................................7-51
7.5.10 READY Mode Access (32-bit Bus)..................................................................................................... 7-57
7.6 Flash ROM, SRAM Usage Example ........................................................................................................... 7-59
8. DMA Controller...................................................................................................................................................... 8-1
8.1 Features.......................................................................................................................................................... 8-1
8.2 Block Diagram............................................................................................................................................... 8-2
8.3 Detailed Explanation...................................................................................................................................... 8-3
8.3.1 Transfer Mode....................................................................................................................................... 8-3
8.3.2 On-chip Registers.................................................................................................................................. 8-3
8.3.3 External I/O DMATransfer Mode ........................................................................................................ 8-4
8.3.4 Internal I/O DMATransfer Mode.......................................................................................................... 8-7
8.3.5 Memory-Memory Copy Mode.............................................................................................................. 8-7
8.3.6 Memory Fill Transfer Mode.................................................................................................................. 8-8
8.3.7 Single Address Transfer ........................................................................................................................ 8-8
8.3.8 Dual Address Transfer......................................................................................................................... 8-10
8.3.9 DMATransfer ..................................................................................................................................... 8-15
8.3.10 Chain DMA Transfer........................................................................................................................... 8-16
8.3.11 Dynamic Chain Operation................................................................................................................... 8-18
8.3.12 Interrupts............................................................................................................................................. 8-19
8.3.13 Transfer Stall Detection Function........................................................................................................ 8-19
8.3.14 Arbitration Among DMA Channels..................................................................................................... 8-20

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8.3.15 Restrictions inAccess to PCI Bus....................................................................................................... 8-20
8.4 Registers....................................................................................................................................................... 8-21
8.4.1 DMA Master Control Register (DMMCR) 0xB0A8...........................................................................8-22
8.4.2 DMA Channel Control Register (DMCCRn) 0xB018 (ch. 0) 0xB038 (ch. 1)
0xB058 (ch. 2) 0xB078 (ch. 3)............................................................................................................ 8-24
8.4.3 DMA Channel Status Register (DMCSRn) 0xB01C (ch. 0) 0xB03C (ch. 1)
0xB05C (ch. 2) 0xB07C (ch. 3) .......................................................................................................... 8-28
8.4.4 DMA Source Address Register (DMSARn) 0xB004 (ch. 0) 0xB024 (ch. 1)
0xB044 (ch. 2) 0xB064 (ch. 3)............................................................................................................ 8-30
8.4.5 DMA Destination Address Register (DMDARn) 0xB008 (ch. 0) 0xB028 (ch. 1)
0xB048 (ch. 2) 0xB068 (ch. 3)............................................................................................................ 8-31
8.4.6 DMA Chain Address Register (DMCHARn) 0xB000 (ch. 0) 0xB020 (ch. 1)
0xB040 (ch. 2) 0xB060 (ch. 3)............................................................................................................ 8-32
8.4.7 DMA Source Address Increment Register (DMSAIRn) 0xB010 (ch. 0) 0xB030 (ch. 1)
0xB050 (ch. 2) 0xB070 (ch. 3)............................................................................................................ 8-33
8.4.8 DMA Destination Address Increment Register (DMDAIRn) 0xB014 (ch. 0) 0xB034 (ch. 1)
0xB054 (ch. 2) 0xB074 (ch. 3)............................................................................................................ 8-34
8.4.9 DMA Count Register (DMCNTRn) 0xB00C (ch. 0) 0xB02C (ch. 1)
0xB04C (ch. 2) 0xB06C (ch. 3) .......................................................................................................... 8-35
8.4.10 DMA Memory Fill Data Register (DMMFDR) 0xB0A4.................................................................... 8-36
8.5 Timing Diagrams ......................................................................................................................................... 8-37
8.5.1 SingleAddress Single Transfer from Memory to I/O (32-bit ROM) ..................................................8-37
8.5.2 SingleAddress Single Transfer from Memory to I/O (16-bit ROM) ..................................................8-38
8.5.3 SingleAddress Single Transfer from I/O to Memory (32-bit SRAM)................................................ 8-39
8.5.4 SingleAddress Burst Transfer from Memory to I/O (32-bit ROM).................................................... 8-40
8.5.5 Single Address Burst Transfer from I/O to Memory (32-bit SRAM).................................................. 8-41
8.5.6 SingleAddress Single Transfer from Memory to I/O (16-bit ROM) ..................................................8-43
8.5.7 SingleAddress Single Transfer from I/O to Memory (16-bit SRAM)................................................ 8-44
8.5.8 SingleAddress Single Transfer from Memory to I/O (32-bit Half Speed ROM)................................ 8-45
8.5.9 SingleAddress Single Transfer from I/O to Memory (32-bit Half Speed SRAM).............................. 8-46
8.5.10 SingleAddress Single Transfer from Memory to I/O (32-bit SRAM) ................................................ 8-47
8.5.11 Single Address Single Transfer from I/O to Memory (32-bit SDRAM) ............................................. 8-48
8.5.12 Single Address Single Transfer from Memory to I/O of Last Cycle when DMADONE*
Signal is Set to Output......................................................................................................................... 8-49
8.5.13 SingleAddress Single Transfer from Memory to I/O (32-bit SDRAM) ............................................. 8-50
8.5.14 SingleAddress Single Transfer from I/O to Memory (32-bit SDRAM) ............................................. 8-51
8.5.15 External I/O Device – SRAM DualAddress Transfer......................................................................... 8-52
8.5.16 External I/O Device – SDRAM DualAddress Transfer...................................................................... 8-54
8.5.17 External I/O Device (Non-burst) – SDRAM Dual Address Transfer.................................................. 8-56
9. SDRAM Controller................................................................................................................................................. 9-1
9.1 Characteristics................................................................................................................................................ 9-1
9.2 Block Diagram............................................................................................................................................... 9-2
9.3 Detailed Explanation...................................................................................................................................... 9-3
9.3.1 Supported SDRAM Configurations ...................................................................................................... 9-3
9.3.2 Address Mapping .................................................................................................................................. 9-4
9.3.3 Initialization of SDRAM....................................................................................................................... 9-9
9.3.4 Low Power Consumption Function..................................................................................................... 9-10
9.3.5 Bus Errors............................................................................................................................................ 9-11
9.3.6 Memory Read and Memory Write....................................................................................................... 9-11
9.3.7 Slow Write Burst................................................................................................................................. 9-11
9.3.8 Clock Feedback................................................................................................................................... 9-12
9.4 Registers....................................................................................................................................................... 9-12
9.4.1 SDRAM Channel Control Register (SDCCR0) 0x8000 (ch. 0) (SDCCR1) 0x8004 (ch. 1)
(SDCCR2) 0x8008 (ch. 2) (SDCCR3) 0x800C (ch. 3) ...................................................................... 9-13
9.4.2 SDRAM Timing Register (SDCTR) 0x8020 ......................................................................................9-15
9.4.3 SDRAM Command Register (SDCCMD) 0x802C............................................................................. 9-17
9.5 Timing Diagrams ......................................................................................................................................... 9-18
9.5.1 Single Read (32-bit Bus)..................................................................................................................... 9-18

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9.5.2 Single Write (32-bit Bus) .................................................................................................................... 9-20
9.5.3 Burst Read (32-bit Bus)....................................................................................................................... 9-22
9.5.4 Burst Write (32-bit Bus)...................................................................................................................... 9-23
9.5.5 Burst Write (32-bit Bus, Slow Write Burst) ........................................................................................ 9-24
9.5.6 Single Read (16-bit Bus)..................................................................................................................... 9-25
9.5.7 Single Write (16-bit Bus) .................................................................................................................... 9-27
9.5.8 Low Power Consumption and Power Down Mode............................................................................. 9-29
9.6 SDRAM Usage Example............................................................................................................................. 9-33
10. PCI Controller....................................................................................................................................................... 10-1
10.1 Features........................................................................................................................................................ 10-1
10.1.1 Overall................................................................................................................................................. 10-1
10.1.2 Initiator Function................................................................................................................................. 10-1
10.1.3 Target Function.................................................................................................................................... 10-1
10.1.4 PCI Arbiter.......................................................................................................................................... 10-2
10.1.5 PDMAC (PCI DMA Controller) ......................................................................................................... 10-2
10.2 Block Diagram............................................................................................................................................. 10-3
10.3 Detailed Explanation.................................................................................................................................... 10-4
10.3.1 Terminology Explanation.................................................................................................................... 10-4
10.3.2 On-Chip Register................................................................................................................................. 10-4
10.3.3 Supported PCI Bus Commands........................................................................................................... 10-6
10.3.4 Initiator Access (G-Bus →PCI Bus address conversion) ................................................................... 10-8
10.3.5 Target Access (PCI Bus →G-Bus Address Conversion) .................................................................. 10-10
10.3.6 Post Write Function........................................................................................................................... 10-13
10.3.7 Endian Switching Function............................................................................................................... 10-13
10.3.8 Power Management........................................................................................................................... 10-14
10.3.9 PDMAC (PCI DMA Controller) ....................................................................................................... 10-15
10.3.10 Error Detection, Interrupt Reporting................................................................................................. 10-19
10.3.11 PCI Bus Arbiter................................................................................................................................. 10-20
10.3.12 PCI Boot............................................................................................................................................ 10-22
10.3.13 Set Configuration Space.................................................................................................................... 10-23
10.3.14 PCI Clock Signal............................................................................................................................... 10-23
10.4 PCI Controller Control Register................................................................................................................. 10-24
10.4.1 ID Register (PCIID) 0xD000 ............................................................................................................ 10-26
10.4.2 PCI Status, Command Register (PCISTATUS) 0xD004................................................................... 10-27
10.4.3 Class Code, Revision ID Register (PCICCREV) 0xD008 ................................................................ 10-29
10.4.4 PCI Configuration 1 Register (PCICFG1) 0xD00C.......................................................................... 10-30
10.4.5 P2G Memory Space 0 PCI Base Address Register (P2GM0PBASE) 0xD010................................. 10-31
10.4.6 P2G Memory Space 1 PCI Base Address Register (P2GM1PBASE) 0xD014................................. 10-32
10.4.7 P2G Memory Space 2 PCI Base Address Register (P2GM2PBASE) 0xD018................................. 10-33
10.4.8 P2G I/O Space PCI BaseAddress Register (P2GIOPBASE) 0xD01C ............................................. 10-34
10.4.9 Subsystem ID Register (PCISID) 0xD02C ....................................................................................... 10-35
10.4.10 Capabilities Pointer Register (PCICAPPTR) 0xD034 ...................................................................... 10-36
10.4.11 PCI Configuration 2 Register (PCICFG2) 0xD03C.......................................................................... 10-37
10.4.12 G2P Timeout Count Register (G2PTOCNT) 0xD040....................................................................... 10-38
10.4.13 G2P Configuration Register (G2PCFG) 0xD060............................................................................. 10-39
10.4.14 G2P Status Register (G2PSTATUS) 0xD064.................................................................................... 10-41
10.4.15 G2P Interrupt Mask Register (G2PMASK) 0xD068......................................................................... 10-42
10.4.16 Satellite Mode PCI Status Register (PCISSTATUS) 0xD088 ........................................................... 10-43
10.4.17 PCI Status Interrupt Mask Register (PCIMASK) 0xD08C............................................................... 10-44
10.4.18 P2G Configuration Register (P2GCFG) 0xD090.............................................................................. 10-45
10.4.19 P2G Status Register (P2GSTATUS) 0xD094.................................................................................... 10-46
10.4.20 P2G Interrupt Mask Register (P2GMASK) 0xD098......................................................................... 10-47
10.4.21 P2G Current Command Register (P2GCCMD) 0xD09C.................................................................. 10-48
10.4.22 PCI BusArbiter Request Port Register (PBAREQPORT) 0xD100 .................................................. 10-49
10.4.23 PCI BusArbiter Configuration Register (PBACFG) 0xD104........................................................... 10-51
10.4.24 PCI BusArbiter Status Register (PBASTATUS) 0xD108................................................................. 10-52
10.4.25 PCI BusArbiter Interrupt Mask Register (PBAMASK) 0xD10C..................................................... 10-53
10.4.26 PCI BusArbiter Broken Master Register (PBABM) 0xD110........................................................... 10-54

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10.4.27 PCI Bus Arbiter Current Request Register (PBACREQ) 0xD114 .................................................... 10-56
10.4.28 PCI BusArbiter Current Grant Register (PBACGNT) 0xD118........................................................ 10-57
10.4.29 PCI BusArbiter Current State Register (PBACSTATE) 0xD11C..................................................... 10-58
10.4.30 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 0xD120............................. 10-59
10.4.31 G2P Memory Space 1 G-Bus Base Address Register (G2PM1GBASE) 0xD128............................. 10-60
10.4.32 G2P Memory Space 2 G-Bus Base Address Register (G2PM2GBASE) 0xD130............................. 10-61
10.4.33 G2P I/O Space G-Bus Base Address Register (G2PIOGBASE) 0xD138 ......................................... 10-62
10.4.34 G2P Memory Space 0Address Mask Register (G2PM0MASK) 0xD140 ........................................ 10-63
10.4.35 G2P Memory Space 1Address Mask Register (G2PM1MASK) 0xD144 ........................................ 10-64
10.4.36 G2P Memory Space 2Address Mask Register (G2PM2MASK) 0xD148 ........................................ 10-65
10.4.37 G2P I/O Space Address Mask Register (G2PIOMASK) 0xD14C .................................................... 10-66
10.4.38 G2P Memory Space 0 PCI BaseAddress Register (G2PM0PBASE) 0xD150 ................................. 10-67
10.4.39 G2P Memory Space 1 PCI BaseAddress Register (G2PM1PBASE) 0xD158 ................................. 10-68
10.4.40 G2P Memory Space 2 PCI BaseAddress Register (G2PM2PBASE) 0xD160 ................................. 10-69
10.4.41 G2P I/O Space PCI Base Address Register (G2PIOPBASE) 0xD168.............................................. 10-70
10.4.42 PCI Controller Configuration Register (PCICCFG) 0xD170............................................................ 10-71
10.4.43 PCI Controller Status Register (PCICSTATUS) 0xD174.................................................................. 10-72
10.4.44 PCI Controller Interrupt Mask Register (PCICMASK) 0xD178....................................................... 10-73
10.4.45 P2G Memory Space 0 G-Bus Base Address Register (P2GM0GBASE) 0xD180 ............................ 10-74
10.4.46 P2G Memory Space 0 Control Register (P2GM0CTR) 0xD184 ...................................................... 10-75
10.4.47 P2G Memory Space 1 G-Bus Base Address Register (P2GM1GBASE) 0xD188 ............................ 10-76
10.4.48 P2G Memory Space 1 Control Register (P2GM1CTR) 0xD18C...................................................... 10-77
10.4.49 P2G Memory Space 2 G-Bus Base Address Register (P2GM2GBASE) 0xD190 ............................ 10-78
10.4.50 P2G Memory Space 2 Control Register (P2GM2CTR) 0xD194 ...................................................... 10-79
10.4.51 P2G I/O Space G-Bus Base Address Register (P2GIOGBASE) 0xD198......................................... 10-80
10.4.52 P2G I/O Space Control Register (P2GIOCTR) 0xD19C .................................................................. 10-81
10.4.53 G2P Configuration Address Register(G2PCFGADRS) 0xD1A0..................................................... 10-82
10.4.54 G2P Configuration Data Register (G2PCFGDATA) 0xD1A4 .......................................................... 10-83
10.4.55 G2P InterruptAcknowledge Data Register (G2PINTACK) 0xD1C8 ............................................... 10-84
10.4.56 G2P Special Cycle Data Register (G2PSPC) 0xD1CC ..................................................................... 10-85
10.4.57 Configuration Data 0 Register (PCICDATA0) 0xD1E0.................................................................... 10-86
10.4.58 Configuration Data 1 Register (PCICDATA1) 0xD1E4.................................................................... 10-87
10.4.59 Configuration Data 2 Register (PCICDATA2) 0xD1E8.................................................................... 10-88
10.4.60 Configuration Data 3 Register (PCICDATA3) 0xD1EC................................................................... 10-89
10.4.61 PDMAC Chain Address Register (PDMCA) 0xD200....................................................................... 10-90
10.4.62 PDMAC G-Bus Address Register (PDMGA) 0xD204 ..................................................................... 10-91
10.4.63 PDMAC PCI Bus Address Register (PDMPA) 0xD208 ................................................................... 10-92
10.4.64 PDMAC Count Register (PDMCTR) 0xD20C ................................................................................. 10-93
10.4.65 PDMAC Configuration Register (PDMCFG) 0xD210..................................................................... 10-94
10.4.66 PDMAC Status Register (PDMSTATUS) 0xD214 .......................................................................... 10-96
10.5 PCI Configuration Space Register............................................................................................................. 10-98
10.5.1 Capability ID Register (Cap_ID) 0xDC............................................................................................ 10-99
10.5.2 Next Item Pointer Register (Next_Item_Ptr) 0xDD........................................................................ 10-100
10.5.3 Power Management Capability Register (PMC) 0xDE................................................................... 10-101
10.5.4 Power Management Control/Status Register (PMCSR) 0xE0 ........................................................ 10-102
11. Serial I/O Port....................................................................................................................................................... 11-1
11.1 Features........................................................................................................................................................ 11-1
11.2 Block Diagram............................................................................................................................................. 11-2
11.3 Detailed Explanation.................................................................................................................................... 11-3
11.3.1 Overview............................................................................................................................................. 11-3
11.3.2 Data Format......................................................................................................................................... 11-3
11.3.3 Serial Clock Generator........................................................................................................................ 11-5
11.3.4 Data Reception.................................................................................................................................... 11-7
11.3.5 Data Transmission............................................................................................................................... 11-7
11.3.6 DMATransfer ..................................................................................................................................... 11-8
11.3.7 Flow Control ....................................................................................................................................... 11-8
11.3.8 Reception Data Status ......................................................................................................................... 11-9
11.3.9 Reception Time Out ...........................................................................................................................11-10
11.3.10 Software Reset ...................................................................................................................................11-10

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11.3.11 Error Detection/Interrupt Signaling....................................................................................................11-11
11.3.12 Multi-Controller System ....................................................................................................................11-12
11.4 Registers......................................................................................................................................................11-13
11.4.1 Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1)
0xF400 (Ch. 1) ...................................................................................................................................11-14
11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1
(SIDICR1) 0xF404 (Ch. 1).................................................................................................................11-15
11.4.3 DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0) DMA/Interrupt Status Register 1
(SIDISR1) 0xF408 (Ch. 1).................................................................................................................11-17
11.4.4 Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0)
Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1)............................................11-19
11.4.5 FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0) FIFO Control Register 1 (SIFCR1)
0xF410 (Ch. 1) ...................................................................................................................................11-20
11.4.6 Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0) Flow Control Register 1
(SIFLCR1) 0xF414 (Ch. 1) ................................................................................................................11-21
11.4.7 Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0) Baud Rate Control Register 1
(SIBGR1) 0xF418 (Ch. 1)..................................................................................................................11-22
11.4.8 Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0) Transmit FIFO Register 1
(SITFIFO1) 0xF41C (Ch. 1) ..............................................................................................................11-23
11.4.9 Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0) Receive FIFO Register 1
(SIRFIFO1) 0xF420 (Ch. 1)...............................................................................................................11-24
12. Timer/Counter....................................................................................................................................................... 12-1
12.1 Features........................................................................................................................................................ 12-1
12.2 Block Diagram............................................................................................................................................. 12-2
12.3 Detailed Explanation.................................................................................................................................... 12-3
12.3.1 Overview............................................................................................................................................. 12-3
12.3.2 Counter Clock ..................................................................................................................................... 12-3
12.3.3 Counter................................................................................................................................................ 12-4
12.3.4 Interval Timer Mode............................................................................................................................ 12-4
12.3.5 Pulse Generator Mode......................................................................................................................... 12-6
12.3.6 Watchdog Timer Mode........................................................................................................................ 12-7
12.4 Registers....................................................................................................................................................... 12-9
12.4.1 Timer Control Register n(TMTCRn) TMTCR0 0xF000 TMTCR1 0xF100 TMTCR2 0xF200 .... 12-10
12.4.2 Timer Interrupt Status Register n(TMTISRn) TMTISR0 0xF004 TMTISR1 0xF104
TMTISR2 0xF204..............................................................................................................................12-11
12.4.3 Compare Register An (TMCPRAn) TMCPRA0 0xF008 TMCPRA1 0xF108 TMCPRA2 0xF20812-12
12.4.4 Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C TMCPRB1 0xF10C................................ 12-13
12.4.5 Interval Timer Mode Register n(TMITMRn) TMITMR0 0xF010 TMITMR1 0xF110
TMITMR2 0xF210............................................................................................................................ 12-14
12.4.6 Divide Register n(TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220.... 12-15
12.4.7 Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF030 TMPGMR1 0xF130 ........... 12-16
12.4.8 Watchdog Timer Mode Register n(TMWTMRn) TMWTMR2 0xF240 .......................................... 12-17
12.4.9 Timer Read Register n(TMTRRn) 0xF0F0 TMTRR0 0xF0F0 TMTRR1 0xF1F0
TMTRR2 0xF2F0.............................................................................................................................. 12-18
13. Parallel I/O Port.................................................................................................................................................... 13-1
13.1 Characteristics.............................................................................................................................................. 13-1
13.2 Block Diagram............................................................................................................................................. 13-1
13.3 Detailed Description .................................................................................................................................... 13-2
13.3.1 Selecting PIO Pins............................................................................................................................... 13-2
13.3.2 General-purpose Parallel Port ............................................................................................................. 13-2
13.4 Registers....................................................................................................................................................... 13-2
13.4.1 PIO Output Data Register (PIODO) 0xF500....................................................................................... 13-3
13.4.2 PIO Input Data Register (PIODI) 0xF504........................................................................................... 13-3
13.4.3 PIO Direction Control Register (PIODIR) 0xF508............................................................................. 13-4
13.4.4 PIO Open Drain Control Register (PIOOD) 0xF50C..........................................................................13-4
14. AC-link Controller................................................................................................................................................ 14-1

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vii
14.1 Features........................................................................................................................................................ 14-1
14.2 Configuration............................................................................................................................................... 14-2
14.3 Functional Description................................................................................................................................. 14-3
14.3.1 CODEC Connection............................................................................................................................ 14-3
14.3.2 Pin Configuration................................................................................................................................ 14-4
14.3.3 Usage Flow.......................................................................................................................................... 14-5
14.3.4 AC-link Start Up ................................................................................................................................. 14-7
14.3.5 CODEC Register Access..................................................................................................................... 14-8
14.3.6 Sample-data Transmission and Reception........................................................................................... 14-9
14.3.7 GPIO Operation ................................................................................................................................ 14-14
14.3.8 Interrupt............................................................................................................................................. 14-15
14.3.9 AC-link Low-power Mode................................................................................................................ 14-15
14.4 Registers..................................................................................................................................................... 14-16
14.4.1 ACLC Control Enable Register (ACCTLEN) 0xF700...................................................................... 14-17
14.4.2 ACLC Control Disable Register (ACCTLDIS) 0xF704 ................................................................... 14-20
14.4.3 ACLC CODEC Register Access Register (ACREGACC) 0xF708................................................... 14-22
14.4.4 ACLC Interrupt Status Register (ACINTSTS) 0xF710..................................................................... 14-23
14.4.5 ACLC Interrupt Masked Status Register (ACINTMSTS) 0xF714.................................................... 14-25
14.4.6 ACLC Interrupt Enable Register (ACINTEN) 0xF718..................................................................... 14-25
14.4.7 ACLC Interrupt Disable Register (ACINTDIS) 0xF71C.................................................................. 14-25
14.4.8 ACLC Semaphore Register (ACSEMAPH) 0xF720......................................................................... 14-26
14.4.9 ACLC GPI Data Register (ACGPIDAT) 0xF740.............................................................................. 14-27
14.4.10 ACLC GPO Data Register (ACGPODAT) 0xF744 .......................................................................... 14-28
14.4.11 ACLC Slot Enable Register (ACSLTEN) 0xF748............................................................................ 14-29
14.4.12 ACLC Slot Disable Register (ACSLTDIS) 0xF74C ......................................................................... 14-31
14.4.13 ACLC FIFO Status Register (ACFIFOSTS) 0xF750........................................................................ 14-32
14.4.14 ACLC DMA Request Status Register (ACDMASTS) 0xF780......................................................... 14-34
14.4.15 ACLC DMA Channel Selection Register (ACDMASEL) 0xF784................................................... 14-35
14.4.16 ACLC Surround Data Register (ACAUDODAT)
0xF7A0 ACLC Audio PCM Output Data Register (ACSURRDAT) 0xF7A4.................................. 14-36
14.4.17 ACLC Center Data Register (ACCENTDAT) 0xF7A8 ACLC LFE Data Register (ACLFEDAT)
0xF7AC ACLC Audio PCM Input Data Register (ACMODODAT) 0xF7B8................................... 14-37
14.4.18 ACLC Modem Output Data Register (ACAUDIDAT) 0xF7B0 ....................................................... 14-38
14.4.19 ACLC Modem Input Data Register (ACMODIDAT) 0xF7BC......................................................... 14-39
14.4.20 ACLC Revision ID Register (ACREVID) 0xF7FC .......................................................................... 14-40
15. Interrupt Controller............................................................................................................................................... 15-1
15.1 Characteristics.............................................................................................................................................. 15-1
15.2 Block Diagram............................................................................................................................................. 15-2
15.3 Detailed Explanation.................................................................................................................................... 15-4
15.3.1 Interrupt Sources................................................................................................................................. 15-4
15.3.2 Interrupt Request Detection................................................................................................................. 15-5
15.3.3 Interrupt Level Assigning.................................................................................................................... 15-5
15.3.4 Interrupt PriorityAssigning................................................................................................................. 15-5
15.3.5 Interrupt Notification........................................................................................................................... 15-6
15.3.6 Clearing Interrupt Requests................................................................................................................. 15-7
15.3.7 Interrupt Requests ............................................................................................................................... 15-7
15.4 Registers....................................................................................................................................................... 15-8
15.4.1 Interrupt Detection Enable Register (IRDEN) 0xF600....................................................................... 15-9
15.4.2 Interrupt Detection Mode Register 0 (IRDM0) 0xF604.................................................................... 15-10
15.4.3 Interrupt Detection Mode Register 1 (IRDM1) 0xF608.................................................................... 15-12
15.4.4 Interrupt Level Register 0 (IRLVL0) 0xF610 ................................................................................... 15-14
15.4.5 Interrupt Level Register 1 (IRLVL1) 0xF614 ................................................................................... 15-15
15.4.6 Interrupt Level Register 2 (IRLVL2) 0xF618 ................................................................................... 15-16
15.4.7 Interrupt Level Register 3 (IRLVL3) 0xF61C................................................................................... 15-17
15.4.8 Interrupt Level Register 4 (IRLVL4) 0xF620 ................................................................................... 15-18
15.4.9 Interrupt Level Register 5 (IRLVL5) 0xF624 ................................................................................... 15-19
15.4.10 Interrupt Level Register 6 (IRLVL6) 0xF628 ................................................................................... 15-20
15.4.11 Interrupt Level Register 7 (IRLVL7) 0xF62C................................................................................... 15-21

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viii
15.4.12 Interrupt Mask Level Register (IRMSK) 0xF640 ............................................................................. 15-22
15.4.13 Interrupt Edge Detection Clear Register (IREDC) 0xF660............................................................... 15-23
15.4.14 Interrupt Pending Register (IRPND) 0xF680.................................................................................... 15-24
15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0 ............................................................................ 15-27
15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510..................................................................... 15-29
15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514..................................................................... 15-29
15.4.18 Interrupt Request Polarity Control Register (IRPOL) 0xF518.......................................................... 15-30
15.4.19 Interrupt Request Control Register (IRRCNT) 0xF51C.................................................................... 15-30
15.4.20 Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xF520.................................... 15-31
15.4.21 Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xF524.................................. 15-31
16. CHI Module.......................................................................................................................................................... 16-1
16.1 Characteristics.............................................................................................................................................. 16-1
16.2 Block Diagram............................................................................................................................................. 16-2
16.3 Detailed Explanation.................................................................................................................................... 16-3
16.3.1 Transmitter .......................................................................................................................................... 16-3
16.3.2 Receiver............................................................................................................................................... 16-4
16.3.3 Clock and Control Generation............................................................................................................. 16-4
16.3.4 DMAAddress Generation................................................................................................................... 16-6
16.3.5 Timing Diagram .................................................................................................................................. 16-8
16.3.6 Interrupts ............................................................................................................................................. 16-9
16.3.7 Frame Structure and Serial Timing.................................................................................................... 16-10
16.3.8 Configurations................................................................................................................................... 16-16
16.4 Registers..................................................................................................................................................... 16-17
16.4.1 CHI Control Register (CTRL) 0xA800............................................................................................. 16-18
16.4.2 CHI Pointer Enable Register (PNTREN) 0xA804........................................................................... 16-21
16.4.3 CHI Receive Pointer A Register (RXPTRA) 0xA808....................................................................... 16-23
16.4.4 CHI Receive Pointer B Register (RXPTRB) 0xA80C...................................................................... 16-24
16.4.5 CHI Transmit PointerARegister (TXPTRA) 0xA810...................................................................... 16-25
16.4.6 CHI Transmit Pointer B Register (TXPTRB) 0xA814...................................................................... 16-26
16.4.7 CHI SIZE Register (CHISIZE) 0xA818............................................................................................ 16-27
16.4.8 CHI RX Start Register (RXSTRT) 0xA81C...................................................................................... 16-28
16.4.9 CHI TX Start Register (TXSTRT) 0xA820....................................................................................... 16-29
16.4.10 CHI TX Holding Register (CHIHOLD) 0xA824.............................................................................. 16-30
16.4.11 CHI RX Holding Register (CHIHOLD) 0xA824.............................................................................. 16-31
16.4.12 CHI Clock Register (CHICLOCK) 0xA828 ..................................................................................... 16-32
16.4.13 HI Interrupt Enable Register (CHIINTE) 0xA82C ........................................................................... 16-33
16.4.14 CHI Interrupt Status Register (CHIINT) 0xA830............................................................................. 16-34
17. Serial Peripheral Interface .................................................................................................................................... 17-1
17.1 Characteristics.............................................................................................................................................. 17-1
17.2 Block Diagram............................................................................................................................................. 17-2
17.3 Detailed Explanation.................................................................................................................................... 17-3
17.3.1 Operation mode................................................................................................................................... 17-3
17.3.2 Transmitter/Receiver........................................................................................................................... 17-3
17.3.3 Baud Rate Generator........................................................................................................................... 17-4
17.3.4 Transfer Format................................................................................................................................... 17-5
17.3.5 Inter Frame Space Counter.................................................................................................................. 17-6
17.3.6 SPI Buffer Structure............................................................................................................................ 17-7
17.3.7 SPI System Errors ............................................................................................................................... 17-7
17.3.8 Interrupts ............................................................................................................................................. 17-7
17.4 Registers....................................................................................................................................................... 17-8
17.4.1 SPI Master Control Register (SPMCR) 0xF800.................................................................................. 17-9
17.4.2 SPI Control Register 0 (SPCR0) 0xF804.......................................................................................... 17-10
17.4.3 SPI Control Register 1 (SPCR1) 0xF808.......................................................................................... 17-12
17.4.4 SPI Inter Frame Space Register (SPFS) 0xF80C .............................................................................. 17-13
17.4.5 SPI Status Register (SPSR) 0xF814.................................................................................................. 17-14
17.4.6 SPI Data Register (SPDR) 0xF818.................................................................................................... 17-16
18. NAND Flash Memory Controller......................................................................................................................... 18-1

Table of Contents
ix
18.1 Characteristics.............................................................................................................................................. 18-1
18.2 Block Diagram............................................................................................................................................. 18-1
18.3 Detailed Explanation.................................................................................................................................... 18-2
18.3.1 Access to NAND Flash Memory......................................................................................................... 18-2
18.3.2 ECC Control........................................................................................................................................ 18-4
18.4 Registers....................................................................................................................................................... 18-5
18.4.1 NAND Flash Memory Data Transfer Register (NDFDTR) 0xC000................................................... 18-5
18.4.2 NAND Flash Memory Mode Control Register (NDFMCR) 0xC004 .................................................18-6
18.4.3 NAND Flash Memory Status Register (NDFSR) 0xC008.................................................................. 18-7
18.4.4 NAND Flash Memory Interrupt Status Register (NDFISR) 0xC00C.................................................18-8
18.4.5 NAND Flash Memory Interrupt Mask Register (NDFIMR) 0xC010 ................................................. 18-9
18.4.6 NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0xC014......................................... 18-10
18.4.7 NAND Flash Memory Reset Register (NDFRSTR) 0xC018.............................................................18-11
18.5 Timing Diagrams ....................................................................................................................................... 18-12
18.5.1 Command and Address Cycle ........................................................................................................... 18-12
18.5.2 Data Read Cycle................................................................................................................................ 18-13
18.5.3 Data Write Cycle............................................................................................................................... 18-15
18.6 Example of Using NAND Flash Memory.................................................................................................. 18-16
19. Real Time Clock (RTC)........................................................................................................................................ 19-1
19.1 Features........................................................................................................................................................ 19-1
19.2 Block Diagrams ........................................................................................................................................... 19-2
19.3 Operations.................................................................................................................................................... 19-3
19.3.1 Operation............................................................................................................................................. 19-3
19.3.2 Interrupt............................................................................................................................................... 19-3
19.4 Registers....................................................................................................................................................... 19-3
19.4.1 RTC Register (High) (RTCHI) 0xF900............................................................................................... 19-4
19.4.2 RTC Register (Low) (RTCLO) 0xF904 .............................................................................................. 19-4
19.4.3 Alarm Register (High) (ALARMHI) 0xF908 ..................................................................................... 19-5
19.4.4 Alarm Register (Low) (ALARMLO) 0xF90C .................................................................................... 19-5
19.4.5 RTC Control Register (RTCCTRL) 0xF910 ....................................................................................... 19-6
19.4.6 RTC Interrupt Status Register (RTCINT) 0xF914............................................................................... 19-7
20. Removed............................................................................................................................................................... 20-1
21. Extended EJTAG Interface................................................................................................................................... 21-1
21.1 Extended EJTAG Interface .......................................................................................................................... 21-1
21.2 JTAG Boundary Scan Test .......................................................................................................................... 21-2
21.2.1 JTAG Controller and Register............................................................................................................. 21-2
21.2.2 Instruction Register ............................................................................................................................. 21-3
21.2.3 Boundary Scan Register...................................................................................................................... 21-3
21.2.4 Device ID Register.............................................................................................................................. 21-6
21.3 Initializing the Extended EJTAG Interface.................................................................................................. 21-7
22. Electrical Characteristics ...................................................................................................................................... 22-1
22.1 Absolute Maximum Rating (*1) ................................................................................................................... 22-1
22.2 Recommended Operating Conditions (*3).................................................................................................... 22-1
22.3 DC Characteristics....................................................................................................................................... 22-2
22.3.1 DC Characteristics Except for PCI Interface....................................................................................... 22-2
22.3.2 DC Characteristics Except for PCI Interface....................................................................................... 22-3
22.4 Power Circuit for PLL.................................................................................................................................. 22-3
22.4.1 Recommended Circuit for PLL........................................................................................................... 22-3
22.5 AC Characteristics....................................................................................................................................... 22-4
22.5.1 MASTERCLKAC Characteristics...................................................................................................... 22-4
22.5.2 Power OnAC Characteristics.............................................................................................................. 22-4
22.5.3 SDRAM InterfaceAC Characteristics................................................................................................. 22-5
22.5.4 External Bus Interface AC Characteristics.......................................................................................... 22-6
22.5.5 PCI Interface AC Characteristics (33 MHz)........................................................................................ 22-7

Table of Contents
x
22.5.6 DMA Interface AC Characteristics...................................................................................................... 22-8
22.5.7 Interrupt Interface AC Characteristics............................................................................................... 22-10
22.5.8 SIO Interface AC Characteristics ...................................................................................................... 22-10
22.5.9 Timer Interface AC Characteristics....................................................................................................22-11
22.5.10 PIO Interface AC Characteristics.......................................................................................................22-11
22.5.11 AC-link Interface AC Characteristics................................................................................................ 22-12
22.5.12 NAND Flash Memory Interface AC Characteristics......................................................................... 22-13
22.5.13 CHI Interface AC Characteristics...................................................................................................... 22-14
22.5.14 SPI Interface AC Characteristics....................................................................................................... 22-15
23. Pin Layout, Package ............................................................................................................................................. 23-1
23.1 Pin Layout.................................................................................................................................................... 23-1
23.2 Package ........................................................................................................................................................ 23-6
24. Usage Notes.......................................................................................................................................................... 24-1
24.1 Limitation on DMAData Chaining..............................................................................................................24-1
24.2 Limitation on a Register Read After an SIO Software Reset.......................................................................24-1
24.3 Other Precautions......................................................................................................................................... 24-1
Appendix A. TX49/H2 Core Supplement.............................................................................................................. A-1
A.1 Processor ID.................................................................................................................................................. A-1
A.2 Interrupts....................................................................................................................................................... A-1
A.3 Bus Snoop..................................................................................................................................................... A-1
A.4 Halt/Doze Mode............................................................................................................................................ A-1
A.5 MemoryAccess Order .................................................................................................................................. A-1

Handling Precautions

1 Using Toshiba Semiconductors Safely
1-1
1. Using Toshiba Semiconductors Safely
TOSHIBAare continually working to improve the quality and the reliability of their products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity
and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to
observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product
could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set
forth in the TOSHIBA Semiconductor Reliability Handbook.
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.). These TOSHIBAproducts are neither intended nor warranted for usage in equipment that
requires extraordinarilyhigh quality and/or reliabilityor a malfunction or failure of which maycause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion
control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer’s own risk.

1 Using Toshiba Semiconductors Safely
1-2

2 Safety Precautions
2-1
2. Safety Precautions
This section lists important precautions which users of semiconductor devices (and anyone else) should observe
in order to avoid injury and damage to property, and to ensure safe and correct use of devices.
Please be sure that you understand the meanings of the labels and the graphic symbol described below before
you move on to the detailed descriptions of the precautions.
[Explanation of labels]
Indicates an imminently hazardous situation which will result in death or serious
injury if you do not follow instructions.
Indicates a potentially hazardous situation which could result in death or serious injury
if you do not follow instructions.
Indicates a potentially hazardous situation which if not avoided, may result in minor
injury or moderate injury.
[Explanation of graphic symbol]
Graphic symbol Meaning
Indicates that caution is required (laser beam is dangerous to eyes).

2 Safety Precautions
2-2
2.1 General Precautions regarding Semiconductor Devices
Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or
temperature).
This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury.
Do not insert devices in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum
current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it
to catch fire or explode and resulting in injury.
When power to a device is on, do not touch the device’s heat sink.
Heat sinks become hot, so you may burn your hand.
Do not touch the tips of device leads.
Because some types of device have leads with pointed tips, you may prick your finger.
When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to
the pins of the device under test before powering it on.
Otherwise, you may receive an electric shock causing injury.
Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it.
Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock.
Always wear protective glasses when cutting the leads of a device with clippers or a similar tool.
If you do not, small bits of metal flying off the cut ends may damage your eyes.