ADLINK Technology cPCI-7300A User manual

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NuIPC/ NuDAQ
cPCI-7300A & PCI-7300A
80MB Ultra-High Speed 32-CH
Digital I/O Boards
User’s Guide
Recycle Paper

Copyright 2002 ADLINK Technology Inc.
All Rights Reserved.
Manual Rev 2.22: July 16, 2002
Part No.: 50-11106-100
The information in this document is subject to change without prior notice in
order to improve reliability, design and function and does not represent a
commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use or inability to
use the product or documentation, even if advised of the possibility of such
damages.
This document contains proprietary information protected by copyright. All
rights are reserved. No part of this manual may be reproduced by any
mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.
Trademarks
NuDAQ, NuIPC, DAQBenchare registered trademarks of ADLINK
Technology Inc.,
Other product names mentioned herein are used for identification purposes
only and may be trademarks and/or registered trademarks of their
respective companies.

Getting service from ADLINK
•CustomerSatisfactionisthemostimportantpriorityforADLINKTechInc.If
you need any help or service, please contact us.
ADLINK Technology Inc.
Web Site http://www.adlinktech.com
Sales &
Service [email protected]
NuDAQ + USBDAQ [email protected]
Automation [email protected]
NuIPC [e-mail]
Technical
Support
NuPRO / EBC [email protected]
TEL [phone] FAX [phone]
Address 9F, No. 166, Jian Yi Road, Chungho City, Taipei, 235 Taiwan.
•Please email or FAX us of your detailed information for a prompt,
satisfactory and constant service.
Detailed Company Information
Company/Organization
Contact Person
E-mail Address
Address
Country
TEL FAX
Web Site
Questions
Product Model
Environment to Use
OS:
Computer Brand:
M/B: CPU:
Chipset: BIOS:
Video Card:
Network Interface Card:
Other:
Detail Description
Suggestions to ADLINK

Table of Contents•i
Table of Contents
Introduction...............................................................................1
1.1 APPLICATIONS...............................................................................................2
1.2 FEATURES .....................................................................................................2
1.3 SPECIFICATIONS...........................................................................................3
1.4 SOFTWARE SUPPORTING..............................................................................5
1.4.1 Programming Library.................................................................5
1.4.2 PCIS-LVIEW: LabVIEW®Driver..............................................5
1.4.3 PCIS-VEE: HP-VEE Driver......................................................6
1.4.4 DAQBenchTM: ActiveX Controls..............................................6
Installation.................................................................................7
2.1 WHAT YOU HAVE..........................................................................................7
2.2 UNPACKING...................................................................................................8
2.3 DEVICE INSTALLATION FOR WINDOWS SYSTEMS .........................................8
2.4 PCI-7300A'S LAYOUT..................................................................................9
2.5 HARDWARE INSTALLATION OUTLINE...........................................................11
2.6 CONNECTOR PIN ASSIGNMENT...................................................................12
2.7 WIRING AND TERMINATION ........................................................................14
2.8 DAUGHTER BOARD SUPPORTING..............................................................15
2.8.1 Connect with DIN-100S..........................................................15
2.8.2 Connect with DIN-502S..........................................................15
Registers..................................................................................16
3.1 I/O PORT BASE ADDRESS ..........................................................................17
3.2 DI_CSR: DI CONTROL & STATUS REGISTER ...........................................18
3.3 DO_CSR: DO CONTROL & STATUS REGISTER .......................................19
3.4 AUXILIARY DIGITAL I/O REGISTER ..............................................................21
3.5 INT_CSR: INTERRUPT CONTROL AND STATUS REGISTER .......................21
3.6 DI_FIFO: DI FIFODIRECT ACCESS PORT................................................22
3.7 DO_FIFO: DO EXTERNAL DATA FIFO DIRECT ACCESS PORT..................23
3.8 FIFO_CR: FIFOALMOST EMPTY/FULL REGISTER.....................................24
3.9 POL_CNTRL: CONTROL SIGNAL POLARITY CONTROL REGISTER ..........24
3.10 PLX PCI-9080 DMA CONTROL REGISTERS...........................................25
Operation Theory....................................................................26
4.1 I/O CONFIGURATION ...................................................................................26
4.2 BLOCK DIAGRAM.........................................................................................27

ii •Table of Contents
4.3DIGITAL I/O DATA FLOW .............................................................................28
4.4 INPUT FIFO AND OUTPUT FIFO................................................................29
4.5 BUS-MASTERING DMA...............................................................................30
4.6 SCATTER/GATHER DMA.............................................................................31
4.7 CLOCKING MODE........................................................................................32
4.8 STARTING MODE.........................................................................................33
4.9 ACTIVE TERMINATOR ..................................................................................34
4.10 DIGITAL INPUT OPERATION MODE.............................................................34
4.10.1 Digital Input DMA in Internal Clock Mode............................34
4.10.2 Digital Input DMA in External Clock Mode...........................36
4.10.3 Digital Input DMA in Handshaking Mode.............................38
4.10.4 Continuous Digital Input..........................................................40
4.11 DIGITAL OUTPUT OPERATION MODE .........................................................41
4.11.1 Digital Output DMA in Internal Clock Mode.........................41
4.11.2 Digital Output DMA in Handshaking Mode..........................42
4.11.3 Digital Output DMA in Burst Handshaking Mode...............44
4.11.4 Pattern Generator....................................................................45
4.12 AUXILIARY DIO..........................................................................................46
C/C++ Libraries.......................................................................47
5.1 LIBRARIES INSTALLATION ............................................................................47
5.2 PROGRAMMING GUIDE................................................................................48
5.2.1 Naming Convention.................................................................48
5.2.2 Data Types................................................................................48
5.3 _7300_INITIAL............................................................................................49
5.4 _7300_CLOSE ...........................................................................................50
5.5 _7300_CONFIGURE...................................................................................50
5.6 _7300_DI_MODE......................................................................................52
5.7 _7300_DO_MODE....................................................................................53
5.8 _7300_AUX_DI........................................................................................54
5.9 _7300_AUX_DI_CHANNEL ......................................................................54
5.10 _7300_AUX_DO.....................................................................................55
5.11 _7300_AUX_DO_CHANNEL....................................................................55
5.12 _7300_ALLOC_DMA_MEM......................................................................56
5.13 _7300_FREE_DMA_MEM........................................................................57
5.14 _7300_DI_DMA_START..........................................................................57
5.15 _7300_DI_DMA_STATUS........................................................................60
5.16 _7300_DI_DMA_ABORT.........................................................................60
5.17 _7300_GETOVERRUNSTATUS..................................................................61
5.18 _7300_DO_DMA_START........................................................................61

Table of Contents•iii
5.19 _7300_DO_DMA_STATUS......................................................................63
5.20 _7300_DO_DMA_ABORT.......................................................................63
5.21 _7300_DO_PG_START...........................................................................64
5.22 _7300_DO_PG_STOP ............................................................................65
5.23 _7300_DI_TIMER .....................................................................................65
5.24 _7300_DO_TIMER ...................................................................................66
5.25 _7300_INT_TIMER ....................................................................................66
5.26 _7300_GET_SAMPLE ...............................................................................67
5.27 _7300_SET_SAMPLE................................................................................68
5.28 _7300_GETUNDERRUNSTATUS ...............................................................68
Appendix A 8254 Programmable Interval Timer................70
A.1 THE INTEL (NEC) 8254.............................................................................70
A.2 THE CONTROL BYTE...................................................................................70
A.3 MODE DEFINITION.......................................................................................72
Warranty Policy.......................................................................74

How to Use This Guide•iv
How to Use This Guide
ThismanualisdesignedtohelpyouusethecPCI-7300andPCI-7300A Rev.B.
The manual describes how to modify various settings on the PCI-7300A card
to meet your requirements. It is divided into five chapters:
•Chapter 1, "Introduction", gives an overview of the product features,
applications, and specifications.
•Chapter 2,"Installation", describes how to install the PCI-7300A. The
layout of PCI-7300A is shown, and the installation procedures, pin
assignment of connectors, and timer pacer generation are specified.
•Chapter 3, "Register Structure & Format", describes the low-level
register structure and format of the PCI-7300A.
•Chapter 4,"OperationTheory",describeshowtousetheoperationsof
digital input and output on the PCI-7300A.
•Chapter 5,"C/C++ & DLL Library", describes the high level C and DLL
library functions. It will help you to programming in DOS, Win 3.11,
Win-95 and Win-NT environments.
•Appendix A, "8254 Programmable Interval Timer", describes the
detailed structure and register format of 8254-timer/counter chip.

Introduction •1
1
Introduction
The cPCI/PCI-7300A is cPCI/PCI form factor ultra-high speed digital I/O card,
it consists of 32 digital input or output channel. High performance designsand
the state-of-the-art technology make this card to be ideal for high speed digital
input and output applications.
The cPCI/PCI-7300A performs high-speed data transfers using bus mastering
DMA and scatter/gather via 32-bit PCI bus architecture. The maximum data
transfer rates can be up to 80MB per second. It is very suitable for interface
between high speed peripherals and your computer system.
The cPCI/PCI-7300A is configured as two ports, PORTA and PORTB, each
portcontrols16digitalI/Olines.TheI/O canconfigureaseitherinputoroutput,
and 8-bit or 16-bit. According to outside device environment, users can
configure cPCI/PCI-7300A to meet all high speed digital I/O data transfer.
There are 4 different digital I/O operation modes are supported:
1.Internal Clock: the digital input and output operations are paced by
internal clock and transferred by bus mastering DMA.
2. External Clock: the digital input operation is paced by external strobe
signal ( DIREQ ) and transferred by bus mastering DMA.
3. Handshaking: through REQ signal and ACK signal, the digital I/O
data can have simple handshaking data transfer.
4. Pattern Generation: You can output a digital pattern repeatedly at a
predetermined rate. The transfer rate is controlled by internal timer.