ADLINK Technology Express-SL2 User manual

Leading EDGE COMPUTING
Express-SL2
User’s Manual
COM Express Basic Size Type 2 Module with
64-bit 6th Gen Intel® Core™, Xeon® E3 and Celeron® processors
Manual Rev.: 1.0
Revision Date: September 2, 2019
Part Number: 50-1J100-1000

ii Preface
Preface
Copyright
Copyright © 2019 ADLINK Technology, Inc. This document contains proprietary information protected by copyright.
All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in
any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and
function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer
be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use
the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with
the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to
ensure that our products, manufacturing processes, components, and raw materials have as little impact on the
environment as possible. When products are at their end of life, our customers are encouraged to dispose of them
in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or
registered trademarks of their respective companies.
Revision History
Revision Description Date By
1.0 Initial release 2019-09-02 JC

Express-SL2
Preface iii
Table of Contents
Preface................................................................................................................................ii
List of Figures ....................................................................................................................v
List of Tables.....................................................................................................................vi
1. Introduction................................................................................................................1
2. Specifications............................................................................................................3
2.1. Core System ...................................................................................................................3
2.2. Expansion Busses...........................................................................................................3
2.3. Video...............................................................................................................................4
2.4. Audio...............................................................................................................................4
2.5. LAN ................................................................................................................................. 4
2.6. Multi I/O and Storage ......................................................................................................4
2.7. Trusted Platform Module (TPM)......................................................................................5
2.8. SEMA Board Controller...................................................................................................5
2.9. Debug ............................................................................................................................. 5
2.10. Power Specifications.......................................................................................................5
2.11. Power Consumption........................................................................................................5
2.12. Operating Temperatures.................................................................................................6
2.13. Environmental .................................................................................................................6
2.14. Specification Compliance................................................................................................6
2.15. Operating Systems..........................................................................................................6
2.16. Functional Diagram.........................................................................................................7
2.17. Mechanical Drawing........................................................................................................8
3. Pinouts and Signal Descriptions..............................................................................9
3.1. AB/CD Pin Definitions .....................................................................................................9
3.2. Signal Description Terminology ....................................................................................12
3.3. AB Signal Descriptions..................................................................................................13
3.4. CD Signal Descriptions .................................................................................................22
4. Connector Pinouts on Module................................................................................27
4.1. Connector, Switch and LED Locations..........................................................................27
4.2. 40-pin Debug Connector...............................................................................................29
4.3. Status LEDs ..................................................................................................................30
4.4. Fan Connector ..............................................................................................................31
4.5. BIOS Setup Defaults Reset Button ...............................................................................32
4.6. Switch Settings .............................................................................................................33
4.7. PCIe x16-to-two-x8 Adapter Card .................................................................................35
5. Smart Embedded Management Agent (SEMA) .....................................................37
5.1. Board Specific SEMA Functions ...................................................................................38
6. System Resources ..................................................................................................41
6.1. System Memory Map ....................................................................................................41
6.2. Direct Memory Access Channels..................................................................................41

iv Preface
6.3. I/O Map .........................................................................................................................41
6.4. Interrupt Request (IRQ) Lines.......................................................................................43
6.5. PCI Configuration Space Map.......................................................................................44
6.6. PCI Interrupt Routing Map ............................................................................................45
6.7. SMBus Address Table ..................................................................................................45
7. BIOS Setup...............................................................................................................47
7.1. Menu Structure..............................................................................................................47
7.2. Main .............................................................................................................................. 48
7.3. Advanced ......................................................................................................................52
7.4. Boot...............................................................................................................................69
7.5. Security ......................................................................................................................... 70
7.6. Save & Exit ...................................................................................................................71
8. BIOS Checkpoints, Beep Codes.............................................................................73
8.1. Status Code Ranges.....................................................................................................74
8.2. Standard Status Codes.................................................................................................74
8.3. OEM-Reserved Checkpoint Ranges.............................................................................81
9. Mechanical Information...........................................................................................83
9.1. Board-to-Board Connectors ..........................................................................................83
9.2. Thermal Solution...........................................................................................................84
9.3. Mounting Methods.........................................................................................................87
9.4. Standoff Types..............................................................................................................88
Safety Instructions...........................................................................................................89
Getting Service.................................................................................................................90

Express-SL2
Preface v
List of Figures
Figure 1: Express-SL2 Functional Block Diagram ...................................................................................7
Figure 2: Express-SL2 Mechanical Drawing ............................................................................................8
Figure 3: Express-SL2 Connector, Switch and LED Locations............................................................. 27
Figure 4: Express-SL2 and the DB40 Debug Module ........................................................................... 28
Figure 5: cExpress Switch Locations .................................................................................................... 33
Figure 6: COM Express Mounting Methods ..........................................................................................87
Figure 7: COM Express Standoff Types................................................................................................ 88

vi Preface
List of Tables
Table 1: Express-SL2 AB/CD Pin Definitions...........................................................................................9
Table 2: 40-pin Debug Connector Pin Definition ................................................................................... 29
Table 3: Express-SL2 LED Descriptions ............................................................................................... 30
Table 4: Fan Connector Pin Definition .................................................................................................. 31
Table 5: PCI Express Configuration Switch Settings ............................................................................ 33
Table 6: BIOS Select and Mode Configuration Switch Settings............................................................ 34
Table 7: SEMA Onboard Voltage Monitor ............................................................................................. 38
Table 8: SEMA BMC Status .................................................................................................................. 38
Table 9: SEMA Exception Codes .......................................................................................................... 39
Table 10: SEMA BMC Flags.................................................................................................................. 39

Express-SL2
Introduction 1
1. Introduction
The Express-SL2 is a COM Express® COM.0 R2.1 Type 2 module supporting the 64-bit 6th Generation Intel®
Core™, Intel® Xeon® E3 and Intel® Celeron® processors (formerly “Skylake H”) with Intel® 170, HM170 and
CM236 Chipset. The Express-SL2 supports all Type 2 legacy I/O as well as Windows 7 and WES7 operating
systems. It is ideally suited for customers who want to extend the production life of existing Type 2 based systems
for at least another 10 years.
The Express-SL2 features Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and DDR4 dual-channel
memory at 1866/2133 MHz with ECC/non-ECC support dependent on processor/chipset combination to provide
excellent overall performance. Intel® Flexible Display Interface and Direct Media Interface provide high speed
connectivity to the Mobile Intel® QM170, HM170, CM236 Chipset.
Integrated Intel® Generation 9 Graphics includes features such as OpenGL 4.4/4.3/4.2, DirectX 11, Intel® Clear
Video HD Technology, Advanced Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA)
support for full H.265/HEVC, MPEG2 hardware decode. Graphics outputs include VGA and LVDS.
The Express-SL2 supports a PATA port, 32-bit PCI bus rev 2.3, SATA 6Gb/s ports, a multiplexed PCI Express®
x16 graphics bus for discrete graphics expansion or general purpose PCI Express x8 or x4 connectivity, USB 2.0
ports and a single onboard Gigabit Ethernet port. In addition, two DDI channels are supported by build option in
place of PCI Express lanes. Support is also provided for SMBus and I2C and the module is equipped with SPI AMI
EFI BIOS with CMOS backup, supporting embedded features such as remote console, CMOS backup, hardware
monitor, and watchdog timer.

2 Introduction
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Express-SL2
Specifications 3
2. Specifications
2.1. Core System
CPU 6th Generation Intel® Core™, Intel® Celeron® and Xeon® E3-15xx v5 processors
(formerly “Skylake H”)
•Intel® Xeon® E3-1505M v5 2.8GHz (3.7GHz Turbo), 45W (35W cTDP) (4C/GT2)
•Intel® Xeon® E3-1505L v5 2GHz (2.8GHz Turbo), 25W (4C/GT2)
•Intel® Core™ i7-6820EQ 2.8GHz (3.5GHz Turbo), 45W (35W cTDP) (4C/GT2)
•Intel® Core™ i7-6822EQ 2GHz (2.8GHz Turbo), 25W(4C/GT2)
•Intel® Core™ i5-6440EQ 2.7GHz (3.4GHz Turbo), 45W (35W cTDP) (4C/GT2)
•Intel® Core™ i5-6442EQ 1.9GHz (2.7GHz Turbo), 25W (4C/GT2)
•Intel® Core™ i3-6100E 2.7GHz, 35W (4C/GT2)
•Intel® Core™ i3-6102E 1.9GHz, 25W (4C/GT2)
•Intel® Celeron® G3900E 2.4GHz, 35W (2C/GT1)
•Intel® Celeron® G3902E 1.6GHz, 25W (2C/GT1)
Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64
Architecture, Execute Disable Bit, Intel® Turbo Boost Technology 2.0, Intel® AVX2, Intel®
AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel®
Secure Key, Intel® TSXNI
Note: Availability of features may vary between processor SKUs.
Cache 8MB for Xeon®/Core™ i7, 6MB for Core™ i5, 3MB for Core™ i3 and 2MB for Celeron®
Memory Dual channel non-ECC/ECC 1866/2133 MHz DDR4 memory up to 32GB in dual stacked
SODIMM socket
Chipset Mobile Intel® QM170, HM170 and CM236 Chipset (HM170 does not support Intel® AMT)
•Core™ i7/i5 with QM170 Chipset (non-ECC memory support)
•Core™ i3/Celeron® with HM170 Chipset (non-ECC memory support)
•Xeon® with CM236 Chipset (ECC and non-ECC memory support)
•Core™ i3/Celeron® with CM236 Chipset (ECC and non-ECC memory support, by
project basis)
BIOS AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 11 support
(AMT not supported by HM170)
2.2. Expansion Busses
PCI Express •PCI Express x16 Gen3( or 2 x8, or 1 x8 and 2 x4)
•6 PCI Express x1 (AB): Lanes 0/1/2/3/4/5
•PCI: 32-bit PCI bus, rev 2.3 (via PCIe-to-PCI chip)
Other •LPC bus
•SMBus (system)
•I2C (user)

4 Specifications
2.3. Video
Integrated on Processor Intel® Generation 9 Graphics core architecture
GPU Feature Support •2 independent and simultaneous display combinations of VGA / LVDS monitors
•Encode/transcode HD content
•Playback of Blu-ray Disc 3D content using HDMI (1.4a spec compliant with 3D)
•DirectX Video Acceleration (DXVA) support for accelerated video processing
•HEVC/H.265, H.264, M/JPEG, MPEG2, VC1, WMV9, VP8/VP9 HW decode
•HEVC/H.265, M/JPEG, MPEG2 HW encode
•Advanced Scheduler 2.0, 1.0, XPDM support
•DirectX 12, DirectX 11.3, DirectX 11, DirectX 10.1, DirectX 10, DirectX 9 suppor
•OpenGL up to 4.4, OpenCL up to 2.1 support
Note: Availability of features s dependent on OS (Win 10/8.1/7, Linux, VxWorks)
Multi Display Support 2 independent displays
Display Interface Support •VGA Interface support through DP-to-VGA chip
•LVDS Interface single/dual channel 18/24-bit LVDS through eDP-to-LVDS chip;
supports DE mode and Hsync/Vsync mode; max. resolution 1920x1200 @60Hz in dual
mode; pixel clock frequency up to 112MHz; VESA and JEIDA panel data formats
supported
•Digital Display Interface support in place of PEG lanes (by build option, max. two DDI
channels)
2.4. Audio
Integrated Intel® HD Audio integrated in QM170/HM170/CM236 Chipset
Codec Located on Express-BASE carrier (Realtek ALC886)
2.5. LAN
Integrated MAC integrated in QM170/HM170/CM236 Chipset
Intel PHY Intel® Ethernet Connection I219LM or I219V (only LM supports Intel® AMT)
Interface 10/100/1000 Mbit/s GbE connection
2.6. Multi I/O and Storage
Integrated Intel® QM170/HM170/CM236 Chipset
USB 8x USB 2.0 (USB 0-7)
SATA* 3x SATA 6Gb/s (SATA 0-2)
PATA 1x PATA IDE (via SATA-to-PATA bridge), Master only
GPIO 4 GPO and 4 GPI with interrupt
*Note: Fourth SATA port (SATA 3) supported by build option in place of PATA

Express-SL2
Specifications 5
2.7. Trusted Platform Module (TPM)
zChipset: Infineon SLB 9665XT2.0
zVersion: TPM 2.0
2.8. SEMA Board Controller
zType: ADLINK Smart Embedded Management Agent (SEMA)
zFunctions:
•Voltage/Current monitoring
•Power sequence debug support
•AT/ATX mode control
•Logistics and forensic information
•Flat panel control
•General purpose I2C
•Failsafe BIOS (dual BIOS by build option)
•Watchdog timer and fan control
2.9. Debug
z40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
z60-pin XDP header for ICE debug of CPU/chipset
2.10. Power Specifications
Power Modes AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
Standard Voltage Input ATX: 12V±5% / 5Vsb ±5%; or AT: 12V±5%
Wide Voltage Input ATX: 8.5-20V, 5Vsb ±5%; or AT: 8.5-20V
Power Management ACPI 5.0 compliant, Smart Battery support
Power States Supports C1-C6, S0, S3, S4, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)
2.11. Power Consumption
Please contact your ADLINK representative for the document “COM Express Module Power Consumption”.

6 Specifications
2.12. Operating Temperatures
Standard Operating
Temperature 0°C to +60°C (Wide Voltage Input)
Storage: -20°C to +80°C
Extreme Rugged Operating
Temperature (optional) -40°C to +85°C (Standard Voltage Input, only select CPU SKUs by project basis)
Storage: -40°C to +85°C
2.13. Environmental
Humidity Operating: 5-90% RH, non-condensing
Storage: 5-95% RH (and operating with conformal coating)
Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,
Condition D
HALT Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.14. Specification Compliance
zPICMG COM.0: Rev 2.1 Type 2, Basic size 125 x 95 mm
2.15. Operating Systems
Standard Support •Windows 7/8 32/64-bit
•Linux 32/64-bit
Extended Support (BSP) •Windows Embedded Standard 7/8
•Linux
•VxWorks

Express-SL2
Specifications 7
2.16. Functional Diagram
Mobile 6th Gen
Intel® Xeon®
Intel® Core™
Intel® Celeron®
Processor
(“Skylake H”)
Thermal
Sensor
TPM
2.0
Mobile Intel®
QM170/HM170/CM236
Chipset
GPIO
AB
GP I2C
CD
SPI 0
BIOS
LPC bus
PCIex16Gen3
1x16,2x8,
or1x8+2x4
SPI
DMI
HD Audio
3x SATA 6Gb/s
(port 0/1/2)
8x USB 2.0
SPI 1
BIOS
DDC I2C
SODIMM 2
1866/2133 MHz
DDR4
SPI_CS#
DDI1
DP/HDMI/DVI
DDI2
DP/HDMI/DVI
single/dual
18/24 bit LVDS
6x PCIe x1 Gen3
(port 0-5)
New
SEMA
BMC
eDP - LVDS
GbE
i219 LM/V
PCIe x1
SMBus
SMBus
SODIMM 1
1866/2133 MHz
DDR4
eDP x2
eDP x4
VGA DP-to-VGA
Switch
PEG or
DDI
PEG
or
DDI 1
DDI 2
PCIe-to-PCI
PCI PCIe
SATA-to-PATA
PATA SATA
4GPI, 4GPO
1x SATA 6Gb/s (port 3)
Figure 1: Express-SL2 Functional Block Diagram

8 Specifications
2.17. Mechanical Drawing
All are dimensions shown in millimeters.
Tolerances should be ± 0.25mm (±0.010”), unless otherwise noted. The tolerances of the module
connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00]) should be ±0.10mm (±0.004”).
Figure 2: Express-SL2 Mechanical Drawing

Express-SL2
Pinouts and Signal Descriptions 9
3. Pinouts and Signal Descriptions
3.1. AB/CD Pin Definitions
The Express-SL2 is a Type 2 module supporting PCI and PATA on the CD connector. All pins in the COM Express
specification are described, including those not supported on the Express-SL2. Those not supported on the
Express-SL2 module are crossed out.
Table 1: Express-SL2 AB/CD Pin Definitions
Row A Row B Row C Row D
Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND (FIXED) D1 GND (FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10
A4
GBE0_LINK100
# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11
A5
GBE0_LINK100
0# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12
A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4
A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0
A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 IDE_REQ
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW#
A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK#
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ
A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0
A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1
A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2
A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 IDE_CS1#
A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 IDE_CS3#
A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET#
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 PCI_GNT3#
A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 PCI_REQ3#
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+ * C22 PCI_REQ0# D22 PCI_AD1
A23 SATA2_TX- B23 SATA3_TX-* C23 PCI_RESET# D23 PCI_AD3
A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5
A25 SATA2_RX+ B25 SATA3_RX+ * C25 PCI_AD2 D25 PCI_AD7
A26 SATA2_RX- B26 SATA3_RX-* C26 PCI_AD4 D26 PCI_C/BE0#
A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 PCI_AD8 D28 PCI_AD11
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 PCI_AD10 D29 PCI_AD13
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 PCI_AD12 D30 PCI_AD15
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32
AC/HDA_BITCL
K B32 SPKR C32 PCI_AD14 D32 PCI_PAR
A33
AC/HDA_SDOU
T B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR#
A34 BIOS_DIS0# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP#
A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY#

10 Pinouts and Signal Descriptions
Row A Row B Row C Row D
Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME#
A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20
A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24
A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28
A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30
A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC#
A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 PCI_IRQD#
A48
EXCD0_PERST
# B48 EXCD1_CPPE# C48 PCI_AD31 D48 PCI_CLKRUN#
A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49
PCI_M66EN
GND)
A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK
A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- D53 PEG_TX0-
A54 GPI0 B54 GPO1 C54 TYPE0# D54
PEG_LANE_RV
#
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2-
A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5-
A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED)
A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- D72 PEG_TX6-
A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK
A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- D75 PEG_TX7-
A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN B77 LVDS_B3+ C77 RSVD D77 IDE_CBLID#
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8-
A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)

Express-SL2
Pinouts and Signal Descriptions 11
Row A Row B Row C Row D
Pin Name Pin Pin Name Pin Pin Name Pin Pin Name
A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK B83
LVDS_BKLT_CT
RL C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND
A88
PCIE0_CK_REF
+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89
PCIE0_CK_REF
- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 GND B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 PEG_ENABLE#
A98 RSVD B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 RSVD B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 RSVD B101 RSVD C101 PEG_RX15+ D101 PEG_TX15+
A102 RSVD B102 RSVD C102 PEG_RX15- D102 PEG_TX15-
A103 RSVD B103 RSVD C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
Note: SATA port 3 is supported by build option, in place of PATA port.

12 Pinouts and Signal Descriptions
3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module

Express-SL2
Pinouts and Signal Descriptions 13
3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
A30 Reset output to codec, active low. O 3.3VSB
AC_SYNC /
HDA_SYNC
A29 Sample-synchronization signal to the
codec(s).
O 3.3VSB
AC_BITCLK /
HDA_BITCLK
A32 Serial data clock generated by the
external codec(s).
I/O 3.3V
AC _SDOUT /
HDA_SDOUT
A33 Serial TDM data output to the codec. O 3.3V Boot strap pin. No external
pull-up orpull-down resistor
on carrier board is
recommended to avoid
changing the configuration of
this signal
AC _SDIN[2:0]
HDA_SDIN[2:0]
B28
B29
B30
Serial TDM data inputs from up to 3
codecs.
I/O
3.3VSB
AC_SDIN0: supported
AC_SDIN1: supported
AC_SDIN2: not supported
3.3.2. Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog PD
150R
Shall also be terminated on
the carrier with 150Ω
resistor to ground close to
VGA connector
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog PD
150R
Shall also be terminated on
the carrier with 150Ω
resistor to ground close to
VGA connector
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog PD
150R
Shall also be terminated on
the carrier with 150Ω
resistor to ground close to
VGA connector
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to
identify VGA monitor capabilities)
I/O OD
3.3V
PU 2k2
3.3V
VGA_I2C_DAT B96 DDC data line. I/O OD
3.3V
PU 2k2
3.3V

14 Pinouts and Signal Descriptions
3.3.3. LVDS
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs O LVDS
LVDS_A_CK+
LVDS_A_CK-
A81
A82
LVDS Channel A differential clock O LVDS
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
B71
B72
B73
B74
B75
B76
B77
B78
LVDS Channel B differential pairs O LVDS
LVDS_B_CK+
LVDS_B_CK-
B81
B82
LVDS Channel B differential clock O LVDS
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 100K
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 10K
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V PD 100K
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. I/O OD
3.3V
PU 2k2
3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O OD
3.3V
PU 2k2
3.3V
3.3.4. Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface
Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000,
100, and 10Mbit/sec modes. Some pairs are unused in
some modes according to the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
I/O
Analog
Twisted pair
signals for
external
transformer.
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O
3.3VSB
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O
3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator,
active low.
O
3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator,
active low.
O
3.3VSB