ADLINK Technology COM Express cExpress-BL User manual

Leading EDGE COMPUTING
cExpress-BL
User’s Manual
Manual Revision: 1.2
Revision Date: January 2, 2018
Part Number: 50-1J061-1020

Page 2
Revision History
Revision Description Date By
1.00 Initial release 2015-05-07 JC
1.01 Update CPU, COM port, power mgmt. specifications; correct LVDS pinout; correct audio, LVDS,
eDP, GbE, SATA, SPI, Fan, SMBus, DDI signal descriptions; update BIOS setup
2015-07-22 JC
1.2 Update switch information 2018-01-02 JC

cExpress-BL
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Preface
Copyright 2015-18 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by
any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not
represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or
consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such
damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and
raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to
dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their
respective companies.

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Table of Contents
Revision History ............................................................................................................ 2
Preface............................................................................................................................ 3
1. Introduction......................................................................................................... 6
2. Specifications....................................................................................................... 7
2.1. Core System...............................................................................................................................7
2.2. Expansion Busses ......................................................................................................................7
2.3. Video .........................................................................................................................................7
2.4. Audio .........................................................................................................................................8
2.5. LAN ............................................................................................................................................8
2.6. Multi I/O and Storage................................................................................................................8
2.7. Serial I/O on Module .................................................................................................................8
2.8. Trusted Platform Module (TPM) ...............................................................................................8
2.9. SEMA Board Controller .............................................................................................................8
2.10. Debug ........................................................................................................................................9
2.11. Power Specifications .................................................................................................................9
2.12. Operating Temperatures...........................................................................................................9
2.13. Environmental ...........................................................................................................................9
2.14. Specification Compliance ..........................................................................................................9
2.15. Operating Systems ....................................................................................................................9
2.16. Functional Diagram ................................................................................................................ 10
2.17. Mechanical Drawing............................................................................................................... 11
3. Pinouts and Signal Descriptions...................................................................... 12
3.1. AB/CD Pin Definitions............................................................................................................. 12
3.2. Signal Description Terminology.............................................................................................. 15
3.3. AB Signal Descriptions............................................................................................................ 16
3.4. CD Signal Descriptions............................................................................................................ 25
4. Connector Pinouts on Module......................................................................... 31
4.1. 40-pin Debug Connector ........................................................................................................ 32
4.2. Status LEDs ............................................................................................................................. 34
4.3. XDP Debug header ................................................................................................................. 35
4.4. Fan Connector ........................................................................................................................ 36
4.5. BIOS Setup Defaults Reset Button.......................................................................................... 36
4.6. BIOS Select and Mode Configuration Switch ......................................................................... 37

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5. Smart Embedded Management Agent (SEMA) ............................................. 38
5.1. Board Specific SEMA Functions.............................................................................................. 39
6. System Resources.............................................................................................. 41
6.1. System Memory Map ............................................................................................................. 41
6.2. Direct Memory Access Channels............................................................................................ 41
6.3. I/O Map .................................................................................................................................. 42
6.4. Interrupt Request (IRQ) Lines................................................................................................. 44
6.5. PCI Configuration Space Map................................................................................................. 46
6.6. PCI Interrupt Routing Map ..................................................................................................... 47
6.7. SMBus Address Table .............................................................................................................47
7. BIOS Setup ......................................................................................................... 48
7.1. Menu Structure ...................................................................................................................... 48
7.2. Main ....................................................................................................................................... 49
7.3. Advanced................................................................................................................................ 53
7.4. Boot ........................................................................................................................................ 69
7.5. Security................................................................................................................................... 70
7.6. Save & Exit.............................................................................................................................. 70
8. BIOS Checkpoints, Beep Codes........................................................................ 71
8.1. Status Code Ranges ................................................................................................................ 72
8.2. Standard Status Codes ...........................................................................................................72
8.3. OEM-Reserved Checkpoint Ranges ........................................................................................ 79
9. Mechanical Information ................................................................................... 80
9.1. Board-to-Board Connectors ................................................................................................... 80
9.2. Thermal Solution .................................................................................................................... 81
9.3. Mounting Methods ................................................................................................................83
9.4. Standoff Types........................................................................................................................ 84
Safety Instructions ...................................................................................................... 85
Getting Service ............................................................................................................ 86

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1. Introduction
The cExpress-BL is a COM Express® COM.0 R2.1 Type 6 Compact size module featuring the 64-bit 5th Generation Intel® Core™ i7/i5/i3
and Intel® Celeron® Ultra-Low TDP processors (formerly “Broadwell-U”) with CPU, memory controller, graphics processor and I/O hub on a
single chip. Leveraging the benefits provided by the 5th generation Intel® Core™ and Celeron™ System-on-Chip, the cExpress-BL is
specifically designed for customers who need optimum processing and graphics performance with low power consumption in a long product
life solution. The cExpress-BL’s Intel® processors support Intel® Hyper-Threading Technology (up to 2 cores, 4 threads) and up to 16 GB of
non-ECC DDR3L dual-channel memory at 1333/1600 MHz in dual stacked SODIMM sockets to provide excellent overall performance.
Integrated Intel® Generation 8 Graphics includes features such as OpenGL 4.2, DirectX 11.1, Intel® Clear Video HD Technology, Advanced
Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics
outputs include dual-channel 18/24-bit LVDS (eDP optional) and two DDI ports supporting HDMI/DVI/DisplayPort. The cExpress-BL is
specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of
their systems for reduced development time.
The cExpress-BL features a single onboard Gigabit Ethernet port, two USB 3.0 ports, six USB 2.0 ports, and four SATA 6Gb/s ports.
Support is provided for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features
such as remote console, CMOS backup, hardware monitor, and watchdog timer.

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2. Specifications
2.1. Core System
¾CPU: 5th Generation Intel® Core™ processor SoC (formerly “Broadwell-U”)
•Intel® Core™ i7-5650U 2.2 GHz (3.1 GHz Turbo), 15W (2C/GT3)
•Intel® Core™ i5-5350U 1.8 GHz (2.7 GHz Turbo), 15W (2C/GT3)
•Intel® Core™ i3-5010U 2.1 GHz (no Turbo), 15W (2C/GT2)
•Intel® Celeron® 3765U 1.9 GHz (no Turbo), 15W (2C/GT1)
Supporting: Intel® VT, Intel® TXT, Intel® SSE4.2, Intel® HT Technology, Intel® 64 Architecture, Execute Disable Bit, Intel® Turbo
Boost Technology 2.0, Intel® AVX2, Intel® AES-NI, PCLMULQDQ Instruction, Intel® Device Protection Technology with Intel® Secure
Key, Intel® TSXNI
Note: Availability of features may vary between processor SKUs.
¾L3 Cache: 4MB for Core™ i7, 3MB for Core™ i5 and Core™ i3, 2MB for Celeron®
¾Memory: Dual channel non-ECC 1600/1333 MHz DDR3L memory up to 16 GB in dual SODIMM socket
¾BIOS: AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 10.0 support (AMT supported on i7/i5 SKUs only)
2.2. Expansion Busses
¾4x PCI Express x1 (AB): Lanes 0/1/2/3
¾LPC bus, SMBus (system), I2C (user)
2.3. Video
¾Integrated on Processor: Intel® Generation 8 Graphics core architecture
¾GPU Feature Support:
•3 independent and simultaneous display combinations of DisplayPort/HDMI/LVDS monitors (eDP optional in place of LVDS)
•Encode/transcode HD content
•Playback of high definition content including Blu-ray Disc
•Playback of Blu-ray disc S3D content using HDMI (1.4a spec compliant with 3D)
•DirectX Video Acceleration (DXVA) support for accelerated video processing
•Full AVC/VC1/MPEG2 HW decode
•Advanced Scheduler 2.0, 1.0, XPDM support
•DirectX 11.1
•Multi Display Support: 3 independent displays
Note: Availability of features may vary between operating systems.
¾Display Types
•Single/dual channel 18/24-bit LVDS via eDP-to-LVDS chip
(eDP available as BOM option in place of LVDS)
•2x Digital Display Ports
DDI1 supports DisplayPort/HDMI/DVI
DDI2 supports DisplayPort/HDMI/DVI

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2.4. Audio
¾Integrated: Intel® HD Audio integrated on SoC
¾Codec: Realtek ALC886 on Express-BASE6 Reference Carrier Board
2.5. LAN
¾Integrated: MAC integrated on SoC
¾Intel PHY: Intel® Ethernet Controller i218LM
¾Interface: 10/100/1000 GbE connection
2.6. Multi I/O and Storage
¾I/O Hub: Integrated on SOC
¾USB: 2x USB 3.0 ports (USB0,1) and 6x USB 2.0 ports (USB2,3,4,5,6,7)
¾SATA: 4x SATA 6Gb/s ports
¾GPIO: 4 GPO and 4 GPI
2.7. Serial I/O on Module
¾Chipset: Nuvoton NCT5104D
¾Ports: 2x UARTs Rx/Tx only
¾Console Redirection: selectable in BIOS, supported during BIOS POST
COM Port Description IRQ Address Console redirection support
COM 1 Supported by module (SER0, A98/A99) via NCT5104D 10 0x240 Yes
COM 2 Supported by module (SER1, A101/A102) via NCT5104D 11 0x248 Yes
COM 3 Supported by Super I/O (W83627DHG) on carrier board 4 0x3F8 Yes
COM 4 Supported by Super I/O (W83627DHG) on carrier board 3 0x2F8 Yes
2.8. Trusted Platform Module (TPM)
¾Chipset: AtmelAT97SC3204
¾Type: TPM 1.2
2.9. SEMA Board Controller
¾Type: ADLINK Smart Embedded Management Agent (SEMA)
¾Functions:
•Voltage/Current monitoring
•Power sequence debug support
•AT/ATX mode control
•Logistics and forensic information
•Flat panel control
•General purpose I2C
•Failsafe BIOS (dual BIOS )
•Watchdog timer and fan control

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2.10. Debug
¾40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs
¾60-pin XDP header for ICE debug of CPU/chipset
2.11. Power Specifications
¾Power Modes: AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
¾Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V±5%
¾Wide Voltage Input: ATX = 5~20 V / 5Vsb ±5% or AT = 5 ~20V
¾Power Management: ACPI 5.0 compliant, Smart Battery support
¾Power States: supports C1-C6, S0, S3, S4, S5 (Wake-on-USB S3/S4, WoL S3/S4/S5)
¾ECO mode: supports deep S5 for 5Vsb power saving
2.12. Operating Temperatures
¾Standard Operating Temperature: 0°C to +60°C (Wide Voltage Input)
¾Extreme Rugged™ Operating Temperature (optional): -40°C to +85°C (Standard Voltage Input)
2.13. Environmental
¾Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I, Condition D
¾HALT: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.14. Specification Compliance
¾PICMG COM.0: Rev 2.1 Type 6, Compact size 95 x 95 mm
2.15. Operating Systems
¾Standard Support: Windows 7/8.1u 32/64-bit, Linux 32/64-bit
¾Extended Support (BSP): Windows Embedded Standard 7 (WES7), Windows Embedded 8 Standard (WE8S), Linux, VxWorks

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2.16. Functional Diagram

cExpress-BL
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2.17. Mechanical Drawing
Top View
Side View
All tolerances ± 0.05 mm
Other tolerances ± 0.2 mm
connectors on bottom side
Dimensions: mm

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3. Pinouts and Signal Descriptions
3.1. AB/CD Pin Definitions
The cExpress-BL is a Type 6 module supporting USB 3.0 upgrade signals and DDI channels on the CD connector
All pins in the COM Express specification are described, including those not supported on the cExpress-BL. Those not supported on the
cExpress-BL module are crossed out.
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A1 GND (FIXED) B1 GND (FIXED) C1 GND FIXED) D1 GND FIXED)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 GND D2 GND
A3 GBE0_MDI3+ B3 LPC_FRAME# C3 USB_SSRX0- D3 USB_SSTX0-
A4 GBE0_LINK100# B4 LPC_AD0 C4 USB_SSRX0+ D4 USB_SSTX0+
A5 GBE0_LINK1000# B5 LPC_AD1 C5 GND D5 GND
A6 GBE0_MDI2- B6 LPC_AD2 C6 USB_SSRX1- D6 USB_SSTX1-
A7 GBE0_MDI2+ B7 LPC_AD3 C7 USB_SSRX1+ D7 USB_SSTX1+
A8 GBE0_LINK# B8 LPC_DRQ0# C8 GND D8 GND
A9 GBE0_MDI1- B9 LPC_DRQ1# C9 USB_SSRX2- D9 USB_SSTX2-
A10 GBE0_MDI1+ B10 LPC_CLK C10 USB_SSRX2+ D10 USB_SSTX2+
A11 GND (FIXED) B11 GND (FIXED) C11 GND (FIXED) D11 GND (FIXED)
A12 GBE0_MDI0- B12 PWRBTN# C12 USB_SSRX3- D12 USB_SSTX3-
A13 GBE0_MDI0+ B13 SMB_CK C13 USB_SSRX3+ D13 USB_SSTX3+
A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND
A15 SUS_S3# B15 SMB_ALERT# C15 DDI1_PAIR6+ D15 DDI1_CTRLCLK_AUX+
A16 SATA0_TX+ B16 SATA1_TX+ C16 DDI1_PAIR6- D16 DDI1_CTRLDATA_AUX
A17 SATA0_TX- B17 SATA1_TX- C17 RSVD D17 RSVD
A18 SUS_S4# B18 SUS_STAT# C18 RSVD D18 RSVD
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCIE_RX6+ D19 PCIE_TX6+
A20 SATA0_RX- B20 SATA1_RX- C20 PCIE_RX6- D20 PCIE_TX6-
A21 GND (FIXED) B21 GND (FIXED) C21 GND (FIXED) D21 GND (FIXED)
A22 SATA2_TX+ B22 SATA3_TX+ C22 PCIE_RX7+ D22 PCIE_TX7+
A23 SATA2_TX- B23 SATA3_TX- C23 PCIE_RX7- D23 PCIE_TX7-
A24 SUS_S5# B24 PWR_OK C24 DDI1_HPD D24 RSVD
A25 SATA2_RX+ B25 SATA3_RX+ C25 DDI1_PAIR4+ D25 RSVD
A26 SATA2_RX- B26 SATA3_RX- C26 DDI1_PAIR4- D26 DDI1_PAIR0+
A27 BATLOW# B27 WDT C27 RSVD D27 DDI1_PAIR0-
A28 (S)ATA_ACT# B28 AC/HDA_SDIN2 C28 RSVD D28 RSVD
A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 DDI1_PAIR5+ D29 DDI1_PAIR1+
A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 DDI1_PAIR5- D30 DDI1_PAIR1-
A31 GND (FIXED) B31 GND (FIXED) C31 GND (FIXED) D31 GND (FIXED)
A32 AC/HDA_BITCLK B32 SPKR C32 DDI2_CTRLCLK_AUX+ D32 DDI1_PAIR2+
A33 AC/HDA_SDOUT B33 I2C_CK C33 DDI2_CTRLDATA_AUX- D33 DDI1_PAIR2-
A34 BIOS_DIS0# B34 I2C_DAT C34 DDI2_DDC_AUX_SEL D34 DDI1_DDC_AUX_SEL
A35 THRMTRIP# B35 THRM# C35 RSVD D35 RSVD

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Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A36 USB6- B36 USB7- C36 DDI3_CTRLCLK_AUX+ D36 DDI1_PAIR3+
A37 USB6+ B37 USB7+ C37 DDI3_CTRLDATA_AUX- D37 DDI1_PAIR3-
A38 USB_6_7_OC# B38 USB_4_5_OC# C38 DDI3_DDC_AUX_SEL D38 RSVD
A39 USB4- B39 USB5- C39 DDI3_PAIR0+ D39 DDI2_PAIR0+
A40 USB4+ B40 USB5+ C40 DDI3_PAIR0- D40 DDI2_PAIR0-
A41 GND (FIXED) B41 GND (FIXED) C41 GND (FIXED) D41 GND (FIXED)
A42 USB2- B42 USB3- C42 DDI3_PAIR1+ D42 DDI2_PAIR1+
A43 USB2+ B43 USB3+ C43 DDI3_PAIR1- D43 DDI2_PAIR1-
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 DDI3_HPD D44 DDI2_HPD
A45 USB0- B45 USB1- C45 RSVD D45 RSVD
A46 USB0+ B46 USB1+ C46 DDI3_PAIR2+ D46 DDI2_PAIR2+
A47 VCC_RTC B47 EXCD1_PERST# C47 DDI3_PAIR2- D47 DDI2_PAIR2-
A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 RSVD D48 RSVD
A49 EXCD0_CPPE# B49 SYS_RESET# C49 DDI3_PAIR3+ D49 DDI2_PAIR3+
A50 LPC_SERIRQ B50 CB_RESET# C50 DDI3_PAIR3- D50 DDI2_PAIR3-
A51 GND (FIXED) B51 GND (FIXED) C51 GND (FIXED) D51 GND (FIXED)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ D52 PEG_TX0+
A53 PCIE_TX5-B53 PCIE_RX5-C53 PEG_RX0- D53 PEG_TX0-
A54 GPI0 B54 GPO1 C54 TYPE0# D54 PEG_LANE_RV#
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ D55 PEG_TX1+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- D56 PEG_TX1-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ D58 PEG_TX2+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- D59 PEG_TX2-
A60 GND (FIXED) B60 GND (FIXED) C60 GND (FIXED) D60 GND (FIXED)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ D61 PEG_TX3+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- D62 PEG_TX3-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ D65 PEG_TX4+
A66 GND B66 WAKE0# C66 PEG_RX4- D66 PEG_TX4-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ D68 PEG_TX5+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- D69 PEG_TX5-
A70 GND (FIXED) B70 GND (FIXED) C70 GND (FIXED) D70 GND (FIXED)
A71 LVDS_A0+
(eDP_TX2+)* B71 LVDS_B0+ C71 PEG_RX6+ D71 PEG_TX6+
A72 LVDS_A0-
(eDP_TX2+)* B72 LVDS_B0- C72 PEG_RX6- D72 PEG_TX6-
A73 LVDS_A1+
(eDP_TX1+ )* B73 LVDS_B1+ C73 GND D73 GND
A74 LVDS_A1-
(eDP_TX1- )* B74 LVDS_B1- C74 PEG_RX7+ D74 PEG_TX7+
A75 LVDS_A2+
(eDP_TX0+ )* B75 LVDS_B2+ C75 PEG_RX7- D75 PEG_TX7-
A76 LVDS_A2-
(eDP_TX0- )* B76 LVDS_B2- C76 GND D76 GND
A77 LVDS_VDD_EN
(eDP_VDD_EN)* B77 LVDS_B3+ C77 RSVD D77 RSVD
A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+
A79 LVDS_A3- B79 LVDS_BKLT_EN
(eDP_BKLT_EN)* C79 PEG_RX8- D79 PEG_TX8-

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Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A80 GND (FIXED) B80 GND (FIXED) C80 GND (FIXED) D80 GND (FIXED)
A81 LVDS_A_CK+
(eDP_TX3+) B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
A82 LVDS_A_CK-
(eDP_TX3-) B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9-
A83 LVDS_I2C_CK
/eDP_AUX+ * B83 LVDS_BKLT_CTRL /eDP_BKLT_CTRL * C83 RSVD D83 RSVD
A84 LVDS_I2C_DAT
/eDP_AUX- * B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+
A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10-
A87 RSVD
/eDP_HPD * B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+
A89 PCIE0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11-
A90 GND (FIXED) B90 GND (FIXED) C90 GND (FIXED) D90 GND (FIXED)
A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+
A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12-
A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND
A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+
A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13-
A96 TPM_PP B96 VGA_I2C_DAT C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 RSVD
A98 SER0_TX B98 RSVD C98 PEG_RX14+ D98 PEG_TX14+
A99 SER0_RX B99 RSVD C99 PEG_RX14- D99 PEG_TX14-
A100 GND (FIXED) B100 GND (FIXED) C100 GND (FIXED) D100 GND (FIXED)
A101 SER1_TX B101 FAN_PWMOUT C101 PEG_RX15+ D101 PEG_TX15+
A102 SER1_RX B102 FAN_TACHIN C102 PEG_RX15- D102 PEG_TX15-
A103 LID# B103 SLEEP# C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (FIXED) B110 GND (FIXED) C110 GND (FIXED) D110 GND (FIXED)
*Note: eDP is available as BOM option in place of LVDS.

cExpress-BL
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3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module

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3.3. AB Signal Descriptions
3.3.1. Audio Signals
Signal Pin # Description I/O PU/PD Comment
AC_RST# /
HDA_RST#
A30 Reset output to codec, active low. O 3.3VSB VSB because PCH uses suspend
power for RESET
AC_SYNC /
HDA_SYNC
A29 Sample-synchronization signal to the codec(s). O 3.3V
AC_BITCLK /
HDA_BITCLK
A32 Serial data clock generated by the external
codec(s).
I/O 3.3V
AC _SDOUT /
HDA_SDOUT
A33 Serial TDM data output to the codec. O 3.3V
AC _SDIN[2:0]
HDA_SDIN[2:0]
B28
B29
B30
Serial TDM data inputs from up to 3 codecs. I/O 3.3VSB PD 1M No AC/HDA_SDIN 2 (B28)
support on this platform
3.3.2. Analog VGA
Signal Pin # Description I/O PU/PD Comment
VGA_RED B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog Not supported
VGA_GRN B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog Not supported
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
O Analog Not supported
VGA_HSYNC B93 Horizontal sync output to VGA monitor O 3.3V Not supported
VGA_VSYNC B94 Vertical sync output to VGA monitor O 3.3V Not supported
VGA_I2C_CK B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
I/O OD 3.3V Not supported
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V Not supported

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Page 17
3.3.3. LVDS/eDP
Signal Pin # Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2- -
LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs O LVDS
LVDS_A_CK+
LVDS_A_CK-
A81
A82
LVDS Channel A differential clock O LVDS
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
B71
B72
B73
B74
B75
B76
B77
B78
LVDS Channel B differential pairs O LVDS
LVDS_B_CK+
LVDS_B_CK-
B81
B82
LVDS Channel B differential clock O LVDS
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 100K
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V PD 100K
LVDS is default.
(through eDP to LVDS
bridge)
Note: eDP support is a
BOM option
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V ePD to LVDS
requirement
LVDS_I2C_CK A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
eDP BOM Option Signal Descriptions
Signal Pin # Description I/O PU/PD Comment
eDP_TX2+
eDP_TX2-
eDP_TX1+
eDP_TX1-
eDP_TX0+
eDP_TX0--
A71
A72
A73
A74
A75
A76
eDP differential pairs O PCIE AC coupled off module
eDP_TX3+
eDP_TX3--
A81
A82
eDP differential pairs O PCIE AC coupled off module
eDP_VDD_EN A77 eDP power enable O 3.3V PD 100K
eDP_BKLT_EN B79 eDP backlight enable O 3.3V PD 100K
eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V
eDP_AUX+ A83 eDP AUX+ I/O PCIE AC coupled off module
eDP_AUX- A84 eDP AUX- I/O PCIE AC coupled off module
eDP_HPD A87 Detection of Hot Plug / Unplug and notification of
the link layer
I 3.3V

Page 18
3.3.4. Gigabit Ethernet
Gigabit Ethernet Pin # Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
I/O Analog Twisted pair
signals for
external
transformer.
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low. O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low. O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics
center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The reference
voltage output shall be current limited on the Module. In the case in which
the reference is shorted to ground, the current shall be 250 mA or less.
GND min
3.3V max
No support on
this product
3.3.5. Serial ATA
Signal Pin # Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
A16
A17
Serial ATA channel 0, Transmit Output
differential pair.
O SATA AC coupled on Module
SATA0_RX+
SATA0_RX-
A19
A20
Serial ATA channel 0, Receive Input
differential pair.
I SATA AC coupled on Module
SATA1_TX+
SATA1_TX-
B16
B17
Serial ATA channel 1, Transmit Output
differential pair.
O SATA AC coupled on Module
SATA1_RX+
SATA1_RX-
B19
B20
Serial ATA channel 1, Receive Input
differential pair.
I SATA AC coupled on Module
SATA2_TX+
SATA2_TX-
A22
A23
Serial ATA channel 2, Transmit Output
differential pair.
O SATA AC coupled on Module
SATA2_RX+
SATA2_RX-
A25
A26
Serial ATA channel 2, Receive Input
differential pair.
I SATA AC coupled on Module
SATA3_TX+
SATA3_TX-
B22
B23
Serial ATA channel 3, Transmit Output
differential pair.
O SATA AC coupled on Module
SATA3_RX+
SATA3_RX-
B25
B26
Serial ATA channel 3, Receive Input
differential pair.
I SATA AC coupled on Module
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity
indicator, active low.
O 3.3V PU 10K 3.3V

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Page 19
3.3.6. PCI Express
Signal Pin # Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
A68
A69
PCI Express channel 0, Transmit Output differential
pair.
O PCIE AC coupled on Module
PCIE_RX0+
PCIE_RX0-
B68
B69
PCI Express channel 0, Receive Input differential
pair.
I PCIE AC coupled off Module
PCIE_TX1+
PCIE_TX1-
A64
A65
PCI Express channel 1, Transmit Output differential
pair.
O PCIE AC coupled on Module
PCIE_RX1+
PCIE_RX1-
B64
B65
PCI Express channel 1, Receive Input differential
pair.
I PCIE AC coupled off Module
PCIE_TX2+
PCIE_TX2-
A61
A62
PCI Express channel 2, Transmit Output differential
pair.
O PCIE AC coupled on Module
PCIE_RX2+
PCIE_RX2-
B61
B62
PCI Express channel 2, Receive Input differential
pair.
I PCIE AC coupled off Module
PCIE_TX3+
PCIE_TX3-
A58
A59
PCI Express channel 3, Transmit Output differential
pair.
O PCIE AC coupled on Module
PCIE_RX3+
PCIE_RX3-
B58
B59
PCI Express channel 3, Receive Input differential
pair.
I PCIE AC coupled off Module
PCIE_TX4+
PCIE_TX4-
A55
A56
PCI Express channel 4, Transmit Output differential
pair.
O PCIE PCIe port 4 is
Connected to LAN
PCIE_RX4+
PCIE_RX4-
B55
B56
PCI Express channel 4, Receive Input differential
pair.
I PCIE PCIe port 4 is
Connected to LAN
PCIE_TX5+
PCIE_TX5-
A52
A53
PCI Express channel 5, Transmit Output differential
pair.
O PCIE Not supported
PCIE_RX5+
PCIE_RX5-
B52
B53
PCI Express channel 5, Receive Input differential
pair.
I PCIE Not supported
PCIE_CLK_REF+
PCIE_CLK_REF-
A88
A89
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
O PCIE
3.3.7. Express Card
Signal Pin # Description I/O PU/PD Comment
EXCD0_CPPE#
EXCD1_CPPE#
A49
B48
PCI ExpressCard: PCI Express capable card request I 3.3V PU 10k 3.3V
EXCD0_PERST#
EXCD1_PERST#
A48
B47
PCI ExpressCard: reset O 3.3V
3.3.8. LPC Bus
Signal Pin # Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7 LPC multiplexed address, command and data bus I/O 3.3V
LPC_FRAME# B3 LPC frame indicates the start of an LPC cycle O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request I 3.3V
LPC_SERIRQ A50 LPC serial interrupt I/O OD 3.3V PU 8k2 3.3V
LPC_CLK B10 LPC clock output - 33MHz nominal O 3.3V

Page 20
3.3.9. USB
Signal Pin # Description I/O PU/PD Comment
USB0+
USB0-
A46
A45
USB differential data pairs for Port 0 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB1+
USB1-
B46
B45
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB2+
USB2-
A43
A42
USB differential data pairs for Port 1 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB3+
USB3-
B43
B42
USB differential data pairs for Port 2 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB4+
USB4-
A40
A39
USB differential data pairs for Port 3 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB5+
USB5-
B40
B39
USB differential data pairs for Port 4 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB6+
USB6-
A37
A36
USB differential data pairs for Port 5 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB7+
USB7-
B37
B37
USB differential data pairs for Port 6 I/O 3.3VSB USB 1.1/ 2.0 compliant
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low. .
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up
for this line shall be present on the module. An open
drain driver from a USB current monitor on the carrier
board may drive this line low.
I 3.3VSB PU 10k 3.3VSB Do not pull high on
carrier