
PCIE-1803 User Manual vi
Figure 3.12Synchronization of up to four PCIE-1803 cards by using
specially designed HDMI cable ................................ 22
Figure 3.13Synchronization of more than four PCIE-1803 cards by
using specially designed HDMI cable....................... 22
Table 3.4: Software configuration for synchronization by using
specially designed HDMI cable ................................ 23
Figure 3.14Synchronization of multiple PCIE-1803 cards by using
MDSI cable............................................................... 23
Table 3.5: Software configuration for synchronization by using
MDSI cable............................................................... 23
3.5 Field Wiring Considerations .................................................................... 24
Appendix A Specifications.................................... 25
A.1 Analog Input............................................................................................ 26
A.1.1 Functions .................................................................................... 26
A.1.2 ADC Modulator Oversample Rate .............................................. 26
A.1.3 Maximum Operating Voltage ...................................................... 26
A.1.4 Input Overvoltage Protection ...................................................... 27
A.1.5 AC Coupled Measurement Accuracy.......................................... 27
A.1.6 DC Coupled Measurement Accuracy ......................................... 27
A.1.7 Input Impedance ......................................................................... 27
A.1.8 Common-Mode Rejection Ratio (CMRR) ................................... 28
A.1.9 Frequency Response.................................................................. 28
A.1.10 AC Coupling................................................................................ 28
A.1.11 Idle Channel Noise ..................................................................... 28
A.1.12 Dynamic Range (DR).................................................................. 28
A.1.13 Spurious Free Dynamic Range (SFDR) ..................................... 28
A.1.14 Signal-to-Noise Ratio (SNR)....................................................... 29
A.1.15 Total Harmonic Distortion (THD) ................................................ 29
A.1.16 Total Harmonic Distortion Plus Noise (THD+N) ......................... 29
A.1.17 Crosstalk..................................................................................... 29
A.1.18 Integrated Electronic Piezoelectric Excitation (IEPE) ................. 30
A.1.19 IEPE Fault Detection .................................................................. 30
A.2 Trigger..................................................................................................... 30
A.2.1 Analog Trigger ............................................................................ 30
A.2.2 External Digital Trigger ............................................................... 31
A.2.3 Trigger Output............................................................................. 31
A.3 Timing Signals ........................................................................................ 31
A.3.1 Timing Signal Inputs ................................................................... 31
A.3.2 Timing Signal Outputs ................................................................ 31
A.4 Digital Input/Output ................................................................................. 31
A.4.1 Digital Input................................................................................. 31
A.4.2 Digital Output .............................................................................. 32
A.5 General Specifications ............................................................................ 32
A.5.1 Bus Interface............................................................................... 32
A.5.2 Power Requirements .................................................................. 32
A.5.3 Physical ...................................................................................... 32
A.5.4 Environmental............................................................................. 32
Appendix B Block Diagram................................... 33
B.1 Function Block Diagrams ........................................................................ 34
Figure B.1 Function block diagram - overview........................... 34