Advantech SOM 144 Guide

SOM 144
System-on-Module
Design Specification Rev. 1.0

Copyright Notice
This document is copyrighted 2001 by Advantech Co. Ltd. All rights
are reserved. Advantech Co., Ltd. reserves the right to make improve-
ments to the products described in this manual at any time without
notice.
No part of this manual may be reproduced, copied, translated or
transmitted in any form or by any means without the prior written
permission of Advantech. Information provided in this manual is
intended to be accurate and reliable. However, Advantech assumes no
responsibility for its use, nor for any infringements upon the rights of
third parties which may result from its use.
All brand and product names mentioned herein are trademarks or
registered trademarks of their respective holders.
Acknowledgments
SOM 144 is a trademark of Advantech Co., Ltd. IBM, PC/AT, and PS/
2 are trademarks of International Business Machines Corporation. MS-
DOS and Windows CE are trademarks of Microsoft Corporation. All
other brand and product names mentioned herein are trademarks or
registered trademarks of their respective holders.
Part No. 2006014410 1st Edition
Printed in Taiwan June 2001

History
The SOM 144 specification and design guide has gone through
revisions since its inception. To keep user’s current with the latest
version of the Advantech SOM 144 specifications and designs, this
page lists the most recently printed revision of the SOM 144 specifica-
tion and design guide. This revision history corresponds with the
revision on the SOM 144 specifications and designs. The guide prints
are ordered from oldest to newest.
Specification and Design Guide
Document No. Date Rev. Changes Items
2006014410 31 May 2001 1.0 Initiation of SOM 144/
PCI Design Specifica
tion

Contents
Chapter 1 General Information 1
1.1 Overviewview ................................................................... 2
Chapter 2 Connector Assignments and Descriptions 3
2.1 144-pin SODIMM (PCI/IDE/ Serial port /USB/AC97/ .
KB/Mouse) ....................................................................... 4
2.2 Recommended 80-pin Front-end Connector (VGA/.....
Ethernet/IrDA/Printer/FDD/ATX) ................................. 6
Chapter 3 Signal Description 7
3.1 144 pin SODIMM (PCI/IDE/ Serial port /USB/AC97/ ..
KB/Mouse) ....................................................................... 8
3.1.1 PCI ............................................................................. 8
3.1.2 IDE .............................................................................9
3.1.3 Serial Ports ............................................................... 11
3.1.4 USB .......................................................................... 11
3.1.5 AC97 ........................................................................ 12
3.1.6 PS/2 Keyboard/Mouse ............................................. 12
3.1.7 Miscellaneous ........................................................... 13
3.2 Recommended front-end 80pin board to board con ......
nector (VGA/Ethernet/IrDA/Printer/FDD/ATX) ....... 13
3.2.1 VGA ......................................................................... 13
3.2.2 Ethernet ................................................................... 14
3.2.3 IrDA ......................................................................... 15
3.2.4 LPT/FDD ................................................................. 15
3.2.5 Miscellaneous ........................................................... 17
Chapter 4 Mechanical Characteristics 19
4.1 Mechanical Characteristics .......................................... 20
4.1.1 Dimensions of SOM 144 Module ............................. 20

4.1.2 SOM 144 Solution Board Layout ............................ 21
4.1.4 SODIMM Layout ..................................................... 22
4.1.3 Recommand Component Suppliers .......................... 22
4.1.5 SOM 144 Module Installation ................................... 23
4.1.6 SOM 144 Module Removal ...................................... 24
Chapter 5 Electrical Characteristics 27
5.1 PCI Bus ........................................................................... 28
5.1.1 IDSEL mapping ........................................................ 28
5.1.2 Interrupt-Routing ...................................................... 28
5.1.3 Onboard resources ................................................... 28
5.2 Power supply definition ................................................. 29
5.3 Electrical Specifications ................................................ 29
5.4 Serial ports ..................................................................... 29
5.5 IrDA ................................................................................. 30
5.6 Parallel Port..................................................................... 30
5.7 FDD .................................................................................. 30
5.8 IDE ................................................................................... 30
5.9 Ethernet specification.................................................... 30
Appendix A Electrical Characteristics 31
A.1 Standard PS/2 - Connectors .......................................... 34
A.2 RS232C ............................................................................ 34
A.3 ATA .................................................................................. 34
A.4 USB .................................................................................. 34
A.5 PCI .................................................................................... 35
A.6 ATX .................................................................................. 35
A.7 AC-LINK 97 (AC97) ..................................................... 35

CHAPTER
1
General Information
This chapter explains the concept of the
SOM 144 (System-on-Module) module. It
also gives the reasons why SOM 144 can
give the most value and benefits to
embedded system applications.

2SOM 144 Design Specification Rev.1.0
1.1Overview
SOM 144 is a new form factor to speed up developing embedded systems.
Simply put, it takes one SODIMM plus a front-end
connector on a 2.5-inch-Hard-Drive-size PC board. Through the
interface of the SODIMM transfer most of the common signals, such as
PCI and USB interfaces for most of peripheral devices and IDE interface
for Hard-Drive, CD-ROM, or Compact Flash. At the same time, special
signals or other function requests go through the
front-end connector.
Based on this specification, it is easier to develop a customer’s
solution board with an off the shelf SOM 144 module and reduce the time
to market of your product. With the SODIMM socket and within 5 sec, a
SOM 144 module is easy to install into or unload from
customer’s solution board.
This standard is a reference for board dimension and pinout of SOM 144
module. Different SOM 144 module may provide a different set of fea-
tures. Please refer the datasheet or manual of your SOM 144
module for details or consult your supplier for supported features. SOM
144 modules are only interchangeable as long as they provide the same
features. At this point, without changing customers’
solution board, customers can upgrade the system module with
higher performance CPU immediately. Some non-standard features like
LCD display interface are not usable without external parts. To create a
backplane or customer’s solution board for SOM 144 module, it’s highly
recommended having experience with PCI device
development. Furthermore, experience with signal integrity and
timing for the layout of your solution board is recommended.
Please contact you supplier or Advantech for advice.
In addition to this document, the user should refer to the following indus-
try standard specifications:
PCI Bus specification Rev 2.2
USB specification 1.1
ATX specification
AC97 Specification Revision 1.3, 2.0, and 2.1
HIROSE Catalog FX8 SERIES

Chapter 2 Pinout of SOM 144/PCI Interfaces 3
CHAPTER
2
Connector Assignments
and Descriptions
This chapter provides the pinout tables
for the SOM 144 PCI interface, including
the 144-pin SODIMM and recommended
80-pin frontend connector.

4SOM 144 Design Specification Rev.1.0
2.1 144-pin SODIMM (PCI/IDE/ Serial port
/USB/AC97/KB/Mouse)
Table 2-1: Pinout of 144-pin SODIMM
Pin Signal Pin Signal
1 GND 2 GND
3 VCC 4 VCC
5 IRQY 6 IRQX
7 IRQW 8 IRQZ
9 GND 10 PCIRST#
11 PCICLK1 12 GND
13 PCICLK2 14 PCICLK3
15 GND 16 GND
17 REQ#0 18 GNT#0
19 REQ#1 20 GNT#1
21 REQ#2 22 GNT#2
23 AD31 24 AD30
25 AD29 26 AD28
27 AD27 28 AD26
29 AD25 30 AD24
31 CBE#3 32 AD22
33 AD23 34 AD20
35 AD21 36 AD18
37 AD19 38 AD16
39 AD17 40 FRAME#
41 CBE#2 42 TRDY#
43 IRDY# 44 STOP#
45 DEVSEL# 46 PAR
47 LOCK# 48 AD15
49 GPERR# 50 AD14
51 SERR# 52 AD13
53 CBE#1 54 AD12
55 AD11 56 CBE#0
57 AD10 58 AD9
59 GND 60 GND
61 GND 62 GND
63 AD8 64 AD7
65 AD6 66 AD5
67 AD4 68 AD2
69 AD0 70 AD3
71 RESERVED 72 A D1

Chapter 2 Pinout of SOM 144/PCI Interfaces 5
73 SERIRQ 74 RESERVED
75 HDRST# 76 PIDE_D8
77 PIDE_D7 78 PIDE_D9
79 PIDE_D6 80 PIDE_D10
81 PIDE_D5 82 PIDE_D11
83 PIDE_D4 84 PIDE_D12
85 PIDE_D3 86 PIDE_D13
87 PIDE_D2 88 PIDE_D14
89 PIDE_D1 90 PIDE_D15
91 PIDE_D0 92 PIDE_IOW#
93 PIDE_DRQ 94 PIDE_RDY
95 PIDE_IOR# 96 PIDE_A1
97 PIDE_AK# 98 RESERVED
99 PIDE_IRQ 100 PIDE_A2
101 PIDE_A0 102 PIDE_CS3#
103 PIDE_CS1# 104 BUZZER#
105 MSDAT 106 MSCLK
107 KBDAT 108 KBCLK
109 VCC 110 VCC
111 OVCR# 112 USB_EN#
113 USB01 114 ACSDTO
115 USB00 116 ACBITCLK
117 USB11 118 ACSDTI
119 USB10 120 ACSYNC
121 EXTRST# 122 ACRST#
123 DCD2# 124 DCD1#
125 DSR2# 126 DSR1#
127 RXD2 128 RXD1
129 RTS2# 130 RTS1#
131 TXD2 132 TXD1
133 CTS2# 134 CTS1#
135 DTR2# 136 DTR1#
137 RI2# 138 RI1#
139 VCC 140 VCC
141 VCC 142 VCC
143 GND 144 GND

6SOM 144 Design Specification Rev.1.0
2.2 Recommended 80-pin Front-end
Connector (VGA/Ethernet/IrDA/Print-
er/FDD/ATX)
Table 2-2: Pinout of Recommended Front-end Connector
Pin Signal Pin Signal
1 GND 2 RESERVED
3 GND 4 DDCK
5 DDAT 6 V S Y
7 HSY 8 B
9G 10R
11 GND 12 STB#
13 AFD# 14 ERR#
15 INIT# 16 SLIN#
17 PD0 18 PD1
19 PD2 20 PD3
21 PD4 22 PD5
23 PD6 24 PD7
25 ACK# 26 BUSY#
27 PE 28 SLCT
29 GND 30 IRFRXH
31 IRCRX 32 IRRX
33 IRTX 34 GND
35 TXDN 36 TXDP
37 GND 38 RXDN
39 RXDP 40 GND
41 GND 42 5VSB
43 5VSB 44 5VSB
45 PME# 46 PWBT
47 PS_ON 48 CKRUN#
49 GND 50 GND
51 GND 52 RESERVED
53 RESERVED 54 RESERVED
55 RESERVED 56 RESERVED
57 RESERVED 58 RESERVED
59 RESERVED 60 RESERVED
61 RESERVED 62 RESERVED
63 RESERVED 64 RESERVED
65 RESERVED 66 RESERVED
67 RESERVED 68 RESERVED
69 GND 70 RESERVED
71 RESERVED 72 RESERVED
73 RESERVED 74 GND
75 SPEEDLED 76 ACTLED
77 GND 78 LILED
79 SDLED 80 GND

Chapter 3 Signal Description 7
Signal Description
This chapter details each signal defined in
the SOM 144 Module.
CHAPTER
3

8 SOM 144 Design Specification Rev.1.0
3.1 144 pin SODIMM (PCI/IDE/ Serial port
/USB/AC97/KB/Mouse)
GND Ground.
VCC +5V +/- 5% power supply.
RESERVED Reserved pin.
3.1.1 PCI
All signals are 3.3 V level PCI signals. All pullups are integrated on
the SOM 144 Module.
PCICLK1..3 PCI clock outputs for 3 external PCI devices.
REQ#0..2 Bus Request signals of 3 external PCI Masters.
When asserted, it means the PCI Master is request-
ing the PCI bus ownership from the arbiter. Please
refer the specification for your SOM 144 Module
for used/ unused PCI Masters and shared PCI
Masters with onboard devices.
GNT#0..2 Grant signals to PCI Masters. When asserted by
the arbiter, it means the PCI master has been legally
granted to own the PCI bus.
AD0..31 PCI Address and Data Bus Lines. These lines are
connected to the PCI bus. AD[31:0] contain the
information of address or data for PCI transactions.
CBE#0..3 PCI Bus Command and Byte Enables. Bus com-
mands and byte enables are multiplexed in these
lines for address and data phases, respectively.
PAR Parity bit of PCI bus. It is the even parity bit across
PAD[31:0] and CBE#[3:0].
SERR# System Error or PCI Clock RUN. The Northbridge
asserts SERR# if parity errors are detected in
DRAM.
GPERR# Parity Error. For PCI operation per exception grant-
ed by PCI 2.1 specification.

Chapter 3 Signal Description 9
LOCK# Lock Resource Signal. This pin indicates the PCI
master or the bridge intends to do exclusive trans-
fers.
DEVSEL# Device Select. When the target device has decod-
ed the address as its own cycle, it will assert
DEVSEL#.
TRDY# Target Ready. This pin indicates the target is ready
to complete the current data phase of transaction.
IRDY# Initiator Ready. This signal indicates the initiator is
ready to complete the current data phase of trans-
action.
STOP# Stop. This signal indicates the target is requesting
the master to stop the current transaction.
FRAME# Cycle Frame of PCI Buses. This indicates the be-
ginning and duration of a PCI access. It will be as
an output driven by Northbridge on behalf of CPU,
or as an input during PCI master access.
PCIRST# PCI Bus Reset. This is an output signal to reset the
entire PCI Bus. This signal will be asserted during
system reset and is a logic invert of RSTDRV.
IRQW, IRQX, IRQY, IRQZ
PCI interrupts from CPU-PCI bridge.
For further descriptions of PCI signals please refer to Chapter 4.
3.1.2 IDE
All required pullups are integrated on the SOM 144 Module. ESD and
EMV protection devices need to be integrated on the backplane.
PIDE_D0..15 Primary/ Secondary IDE ATA Data Bus. These are
the Data pins connected to Primary Channel.
PIDE_A0..2 IDE ATA Address Bus. These are the Address pins
connected to Secondary Channel.
PIDE_CS1# Primary IDE Chip Select 1 for Channel 0. This com-
mand output pin enables the IDE device to watch
the Read/Write Command.

10 SOM 144 Design Specification Rev.1.0
PIDE_CS3# Primary IDE Chip Select 3 for Channel 1. This com-
mand output pin enables the IDE device to watch
the Read/Write Command.
PIDE_DRQ IDE DMA Request for IDE Master. This is the in-
put pin from the IDE DMA request to do the IDE
Master Transfer. It will active high in DMA or Ul-
tra-33 mode and always be inactive low in PIO mode.
PIDED_AK# IDE DACK# for IDE Master. This is the output pin
to grant the IDE DMA request to begin the IDE
Master Transfer in DMA or Ultra-33 mode.
PIDE_RDY IDE Ready. This is the input pin from the IDE Chan-
nel to indicate the IDE device is ready to terminate
the IDE command in PIO mode. The IDE device can
de-assert this input (logic 0) to expand the IDE com-
mand if the device is not ready. In Ultra-33 mode,
this pin has different functions. In read cycle, IDE
device will drive this signal as Data Strobe
(DSTROBE) to use by IDE Busmaster to strobe the
input data. In write cycles, this pin is used by IDE
device to notify IDE Busmaster as DMA Ready
(DDMARDY#).
PIDE_IOR#
IDE IOR# Command. This is the IOR# command
output pin to notify the IDE device to assert the
Read Data in PIO and DMA mode. In Ultra-33
mode, this pin has different function. In read
cycle, this pin is used by IDE Busmaster to notify
IDE device as DMA Ready (DDMARDY#). In
write cycle, IDE Busmaster will drive this signal
as Data Strobe (DSTROBE) to use by IDE device
to strobe the output data.
PIDE_IOW# IDE IOW# Command. This is the IOW# command
output pin to notify the IDE device that the avail-
able Write Data is already asserted by IDE Bus-
master in PIO and DMA mode. In Ultra-33 mode,
this pin is driven by IDE Busmaster to force IDE

Chapter 3 Signal Description 11
device to terminate current transaction. After re-
ceiving this input, IDE device will de-assert DRQ
to STOP current transaction.
PIDE_IRQ Interrupt signal.
HDRST# Low active hardware reset (RSTDRV inverted).
3.1.3 Serial Ports
All signals are TTL level signals. External drivers are necessary to
convert the TTL signals to the desired physical interfaces, such as
RS232, RS422,or RS485.
DCD1#, DCD2# This active low input for serial port. Handshake
signal which notifies the UART that carrier signal
is detected by the modem.
DSR1#, DSR2# This active low input is for serial port. Handshake
signal which notifies the UART that the modem is
ready to establish the communication link.
RXD1, RXD2 Receiver serial data input.
RTS1#, RTS2# This active low output for serial port. Handshake
signal notifies the modem that the UART is ready
to transmit data.
TXD1, TXD2 Transmitter serial data output from Serial port.
CTS1#, CTS2# This active low input for serial ports . Handshake
signal which notifies the UART that the modem is
ready to receive data.
DTR1#, DTR2# Active low data terminal ready outputs for the seri-
al port. Handshake output signal notifies modem
that the UART is ready to establish data communi-
cation link.
RI1#, RI2# This active low input is for the serial port. Hand-
shake signal which notifies the UART that the tele-
phone ring signal is detected by the modem.
3.1.4 USB
All pullups are integrated on the SOM 144 Module. For ESD and

12 SOM 144 Design Specification Rev.1.0
EMV protection please integrate the parts on you backplane.
USB00, USB01 Universal Serial Bus Port 0. These are the serial
data pair for USB Port 0.
USB00 – negative signal, USB01 – positive signal
USB10, USB11 Universal Serial Bus Port 1. These are the serial
data pair for USB Port 1.
USB10 – negative signal, USB11 – positive signal
USB_EN# USB Power Enable. This pin enables the power to a
self-powered USB hub.
OVCR# Over current detect input. This pin is used to mon-
itor the USB power over current. Pull with open-
collector to GND if over-current is detected.
For further description of USB Bus please refer Chapter 7.
3.1.5 AC97
All signals are provided for directively connecting to a AC97 Codec
or a AC97 compliant audio component on the solution boards for the
audio funcion. Note that the codec must have SRC (sample rate con-
version) support.
ACSDTO AC-Link Serial Data Output, CODEC Input Stream.
ACBITCLK AC-Link Bit Clock. 12.288 MHz Serial Data Clock.
Daisy Chain Output Clock.
ACSDTI AC-Link Serial Data Input. CODEC Output Stream.
ACSYNC AC-Link Frame Sample Sync 48 kHz Fixed Rate.
ACRST# AC-Link Reset. CODEC Master H/W Reset.
3.1.6 PS/2 Keyboard/Mouse
All signals are not fused and without ESD and EMV protection cir-
cuitry. Protection devices will need to be incorporated onto the SOM
144 backplane.
MSDAT This is the bi-directional Mouse data signal.

Chapter 3 Signal Description 13
MSCLK This is the Mouse clock signal.
KBDAT This is the bi-directional Keyboard data signal.
KBCLK This is the Keyboard clock signal.
3.1.7 Miscellaneous
SERIRQ Serial interrupt request. This pin is used to support
the serial interrupt protocol. Please refer the manu-
al of your SOM 144 Module for support of this
signal.
BUZZER# This is the PC buzzer speaker output signal, con-
nected to a speaker between output and VCC. Stan-
dard Speaker needs an External transistor. Max. sink
current of this signal is 5mA.
EXTRST# External Reset.
3.2 Recommended front-end 80pin board
to board connector (VGA/Ethernet/
IrDA/Printer/FDD/ATX)
GND Ground.
12V +12V +/- 5 % power supply
RESERVED Reserved pin.
3.2.1 VGA
All pullups are integrated on the SOM 144 Module. For ESD and
EMV protection please integrate the parts on you backplane.
HSY Horizontal Sync: This output supplies the horizon-
tal synchronization pulse to the monitor. It is nor-
mally not needed for flat panels.
VSY Vertical Sync: This output supplies the vertical syn-
chronization pulse to the monitor. It is normally not
needed for flat panels.
R, G, B Red, green and blue analog video output signals

14 SOM 144 Design Specification Rev.1.0
for CRT displays.
DDCK, DDAT These two pins are functionally suitable for a DDC
interface between the graphics controller chip and
the CRT monitor.
3.2.2 Ethernet
All required pullups are integrated on the SOM 144 Module. ESD and
EMV protection devices need to the please integrated on the back-
plane.
The SOM 144 Ethernet Interface is designed for use with a 1:1/ 1:1
external transformer.
Please refer to the electrical specification for further details.
TXDN, TXDP (Analog Twisted Pair)
Ethernet Transmit Differential Pair. These pins trans-
mit the serial bit stream for transmission on the
Unshielded Twisted Pair (UTP) cable. The current-
driven differential driver can be two-level (10BASE-
T) or three-level (100BASE-TX) signals depending
on the mode of operation. These signals interface
directly with an isolation transformer.
RXDN, RXDP ( Analog Twisted Pair)
Ethernet Receive Differential Pair. These pins re-
ceive the serial bit stream from the isolation trans-
former. The bit stream can be two-level (10BASE-
T) or three-level (100BASE-TX) signals depending
on the mode of operation.
ACTLED The Activity LED pin indicates either transmit or
receive activity. When activity is present, the ac-
tivity LED is on; when no activity is present, the
activity LED is off.
LILED The Link Integrity LED pin indicates link integrity.
If the link is valid in either 10 or 100 Mbps, the LED
is on; if link is invalid, the LED is off.
SPEEDLED The Speed LED pin indicates the speed. The speed
LED will be on at 100 Mbps and off at 10 Mbps.