A "Dual-in-Line
Package
(DIP) switch (SWI) (one eight
switch pack)
is
mounted on the board
and
can
be
read
under
program control. The 0 IP !;witch provides the system software·
with
information about the installed options,
how
much storage
the system board
has,
what type
of
the display adapter
is
installed,
what operation modes
ar~
desired when power
is
switched on
(color or black-and-white, 80-
or
40-character lines), and the
nL'mb£r
of
diskette drive attached.
The system board consists
of
five functional
area:
the proces-
sor
subsystem and its support elements, the Read-Only Memory
(ROM) subsystem, the ReadlWrite (RIW) Memory subsystem,
integrated I/O adapters,
and
the I/O channel. All
are
desired in
this section.
The heart
of
the 10MHZ Turbo system board
is.
the
INTEL
8088-1 or qualified 8088-2 microprocessor. This processor
is
a"
8-bit external
bus
version
of
INTEL'S
16
bit
8086 processor, and
it's softwarecompatible
with
the 8086. Thus, the 8088supports 16
bit
operations. including
multiply
and
divide,
and
supports 20
bits addressing
(1
megabyte
of
storage).
It
also
operates in amaximum mode,
so
a coprocessor
can
be
added
as
a feature. The processor operates in two mode, which
can
be
switched, called Normal mode
and
Turbo mode.
When
the
processor operating at 4.77
,111HZ
called Normal mode, the tre-
=1uency,
which
is
derived from a 14.318 MHZ crystal,
is
devided
by 3 for the processor clock,
and
by 4 to obtain the 3.58
MHZ
color burts signal required
for
color television.
When
processor
operating at 10
MHZ
called Turbo mode, the frequency
is
derived
from 30 MHZ.
2
-OMA-
Three
of
the four DMA channels
are
available on the I/O bus
and
support high
speed
data transfers betwt*3n I/O devices
and
memory
without
processor intervention. The fourth
DMA
chan-
nel
is
programmed
to
refresh the system dynamic memory. Th
is
is
done by programing a channel
of
the timer-counter device
to
periodically request a dummy
DMA
transfer. This action creates a
. memory-read cycle, which
is
available
to
refresh dynamic storage,
both on the system board
and
in the system expansion slots.
All
DMA
data transfers. except the refresh channel, take five proces-
sor clocks
of
210
ns,
or 1.05,
IJS
if
the processor ready line
is
not
deactivated.
Refresh
DMA cycles take
four
clocks or 840
ns.
-TIMER
-
The three programmable timer/counters
are
used
by
the
system
as
follows: Channel 0
is
used
as
a
general
pl,trpose timer,
providing a constant time
base
for implementing a time-of-day
clock;
ChClnnel
1
is
used
to
time
and
request refresh cycles from
the
DMA
channel; and Channel 2
is
used
to support the tone
generation for the audio
speaker.
Each
channel
has
a minimum
timing resolution
of
1.05
p.s.
-INTERRUPT -
Of the eight prioritized
levels
of
interrupt. six
are
bussed
to
the system expansion slots
for
use
by features
cards.
Two
levels
are
used
on the system board.
Level
0, the highest
priority,
is
. attached
to
Channel
0
of
the timer/counter
and
provides a per-
iodic interrupt for the time-of-day clock.
Level
1
is
attached
to
the keyboard adapter circuits and
receives
an
interrupt
for
~ach
scan
code
sent
by the keyboard. The Non-Maskable
Interrupt
(NMi)
of
the 8088
is
used
to
report memory parity errors.
3
