Emerson COM Express Carrier Guide

COM Express Carrier Type 2
Design Guide
October 2009
Confidential and Proprietary

Page 2 of 103 COM Express Carrier Type 2
Design Guide
Copyright
© Copyright 2009 Emerson Network Power
All rights reserved.
Emerson Network Power is registered in the U.S. Patent and Trademark offices.
All other product or service names mentioned in this document are the property of their respective
owners.
All the material herein is Emerson Confidential Proprietary and is subject to Emerson
standards for controlling proprietary material. Use of this material is restricted to
Emerson employees with a need to know, and others with a need to know that are
subject to a confidentiality agreement.
Information must be kept out of view of persons not having a need to know. When
printed information is not in use, it must be stored in a locked cabinet, desk or
approved Controlled Access Area. Digital information should have access control and
files should be locked for access only by authorized individuals.

COM Express Carrier Type 2 Page 3 of 103
Design Guide
Table of Contents
1About this Document ..........................................13
1.1 Introduction..................................................................................13
1.2 Intended Audience ........................................................................13
1.3 Acronyms and Abbreviations .........................................................13
2Carrier Board Connector ......................................16
2.1 Connectors Description .................................................................16
2.2 Connectors Land Pattern and Alignment........................................16
3PCI Express Lanes 0—5 ..........................................18
3.1 Introduction..................................................................................18
3.2 COM Express PCIe Signals Definition ..............................................18
3.3 PCIE Feature Support .....................................................................20
3.3.1 Polarity Inversion.........................................................................................................20
3.3.2 Lane Reversal ..............................................................................................................20
3.4 PCIE Schematic Example ................................................................20
3.4.1 PCIE Reference Clock ..................................................................................................20
3.4.2 PCIE Signals AC Couple................................................................................................22
3.4.3 X1 Slot Example ..........................................................................................................23
3.4.4 x4 Slot.........................................................................................................................24
3.4.5 Express Card Example..................................................................................................24
3.4.6 PCI Express Mini Card ..................................................................................................26
3.5 PCI Express Signals—Routing Consideration....................................27
4PCIe Graphics (PCIe 16—31) and SDVO ..................29

Page 4 of 103 COM Express Carrier Type 2
Design Guide
4.1 PCIe Graphics (PEG) Configuration .................................................32
4.1.1 Using as External Graphic Card.................................................................................... 32
4.1.2 Using as SDVO............................................................................................................ 32
4.1.3 Using as General PCI Express Lanes ............................................................................. 32
4.2 Schematic Examples ......................................................................33
4.2.1 x16 PCIE Graphic Card................................................................................................. 33
4.2.2 SDVO to DVI Inverter .................................................................................................. 34
4.3 Routing Consideration...................................................................35
5LAN .....................................................................37
5.1 LAN Signals Definition ...................................................................37
5.2 Emerson LAN LED Definition ..........................................................38
5.3 Example Schematic .......................................................................38
5.4 Layout Consideration.....................................................................38
6USB Ports.............................................................39
6.1 USB Carrier Signals Definition ........................................................39
6.2 Reference Schematic .....................................................................40
6.3 Layout Consideration.....................................................................40
7SATA....................................................................41
7.1 SATA Signals Definition..................................................................42
7.2 Reference Schematic .....................................................................43
7.3 Layout Consideration.....................................................................44
8LVDS....................................................................45
8.1 LVDS Signals Description ...............................................................45

COM Express Carrier Type 2 Page 5 of 103
Design Guide
8.1.1 Connector and Cable Considerations...........................................................................46
8.1.2 Display Timing Configuration ......................................................................................47
8.1.3 Backlight Control ........................................................................................................47
8.1.4 Color Mapping and Terms ...........................................................................................48
8.2 Reference Schematic .....................................................................50
8.3 Layout Considerations ...................................................................50
9VGA .....................................................................51
9.1 VGA Signals Definition ...................................................................51
9.2 Reference Schematic .....................................................................51
9.3 Layout Consideration.....................................................................51
10 IDE and Compact Flash.........................................53
10.1 IDE Signals Definition ....................................................................53
10.2 Reference Schematic .....................................................................54
10.2.1 40-pin IDE Header...................................................................................................54
10.2.2 44-pin IDE Header...................................................................................................55
10.2.3 5-pin Compact Flash Header...................................................................................56
10.3 Layout Consideration.....................................................................57
11 PCI.......................................................................58
11.1 PCI Signals Definition.....................................................................58
11.2 PCI Resource Assignment...............................................................62
11.3 Reference Schematic .....................................................................62
11.3.1 Device-Down example............................................................................................62
11.3.2 PCI Bus Slot Example...............................................................................................64
11.4 Layout Consideration.....................................................................64

Page 6 of 103 COM Express Carrier Type 2
Design Guide
12 LPC ......................................................................66
12.1 LPC Signals Definition ....................................................................66
12.2 Reference Schematic .....................................................................66
12.2.1 FWH Schematic ..................................................................................................... 66
12.2.2 Super IO Schematic................................................................................................ 68
12.3 Layout Consideration.....................................................................69
12.3.1 General Signals ...................................................................................................... 69
12.3.2 Bus Clock Routing .................................................................................................. 69
13 AC’97 and HD Audio.............................................70
13.1 Signals Definition ..........................................................................70
13.2 Reference Schematic .....................................................................71
13.3 Layout Consideration.....................................................................72
14 TV OUT ................................................................74
14.1 TV-Out Signals Definition...............................................................74
14.2 Reference Schematic .....................................................................75
14.3 Layout Consideration.....................................................................75
15 SM bus and I2C .....................................................76
15.1 Signals Definition ..........................................................................76
15.2 I2C Address Allocation Consideration..............................................76
15.3 Layout Consideration.....................................................................77
16 Miscellaneous Signals ..........................................78
16.1 Module Type Detection..................................................................78

COM Express Carrier Type 2 Page 7 of 103
Design Guide
16.2 Power Management Signals ..........................................................79
16.3 Watch Dog ....................................................................................81
16.4 Speaker.........................................................................................81
16.5 RTC Battery ...................................................................................82
16.6 GPIO..............................................................................................83
17 Thermal Signals ...................................................85
18 Power and Reset..................................................86
18.1 VCC12V .........................................................................................86
18.2 VCC5V_STB....................................................................................86
18.3 VCC_RTC .......................................................................................86
18.4 Copper Trace Size and Current Capacity .........................................86
18.5 Reset Signals Definitions................................................................87
19 BIOS Consideration..............................................88
19.1 Legacy versus Legacy Free .............................................................88
19.2 Carrier Super I/O Support...............................................................88
20 Mechanical Consideration ...................................89
20.1 Form Factor...................................................................................89
20.2 Heat Spreader ...............................................................................90
21 Layout Guidelines ................................................91
21.1 PCB Stack-ups................................................................................91

Page 8 of 103 COM Express Carrier Type 2
Design Guide
21.1.1 Four-Layer Stack-up ............................................................................................... 91
21.1.2 Six-Layer Stack-up.................................................................................................. 91
21.1.3 Eight-Layer Stack-up .............................................................................................. 92
21.2 Trace-Impedance Considerations...................................................92
21.3 Routing Rules for High-Speed Differential Interfaces ......................94
21.3.1 PCI Express 1.1 Trace Routing Guidelines ............................................................... 96
21.3.2 USB Trace Routing Guidelines ................................................................................ 97
21.3.3 PEG 1.1 Trace Routing Guidelines........................................................................... 97
21.3.4 SDVO Trace Routing Guidelines ............................................................................. 98
21.3.5 LAN Trace Routing Guidelines ................................................................................ 99
21.3.6 Serial ATA Trace Routing Guidelines..................................................................... 100
21.3.7 LVDS Trace Routing Guidelines ............................................................................ 101
21.4 Routing Rules for Single-Ended Interfaces ....................................101
21.4.1 PCI Trace Routing Guidelines................................................................................ 102
21.4.2 IDE Trace Routing Guidelines ............................................................................... 103
21.4.3 LPC Trace Routing Guidelines............................................................................... 103

COM Express Carrier Type 2 Page 9 of 103
Design Guide
List of Tables
Table 1 Available Carrier Board COM Express Connector Source...............................................16
Table 2 PCIe Signal Definition ..................................................................................................18
Table 3 Support Signals for ExpressCard ..................................................................................25
Table 4 PEG Signal Description ................................................................................................29
Table 5 SDVO Layout Requirement..........................................................................................36
Table 6 LAN Interface Signal Description..................................................................................37
Table 7 USB Signals Definition .................................................................................................39
Table 8 SATA Signal Definition.................................................................................................42
Table 9 SATA Connector Pinout ...............................................................................................42
Table 10 SATA Power Connector Pinout.....................................................................................42
Table 11 LVDS Signals Description.............................................................................................46
Table 12 LVDS Display Terms and Definitions ............................................................................49
Table 13 IDE Signals Description................................................................................................53
Table 14 PCI Signals Definition ..................................................................................................58
Table 15 PCI Bus Interrupt Routing ............................................................................................62
Table 16 LPC Interface Signal.....................................................................................................66
Table 17 Audio Codec Description of Signals .............................................................................70
Table 18 TV-Out Definition of Signals ........................................................................................74
Table 19 COM Express SMBus and I2C Signal Groups ..................................................................76
Table 20 Miscellaneous Signals..................................................................................................78
Table 21 Module Type Detection...............................................................................................79
Table 22 System States S0—S5 Definitions .................................................................................80
Table 23 Power Management Signal Description .......................................................................80
Table 24 GPIO Signal Definition .................................................................................................83
Table 25 Thermal Management Signal Description....................................................................85
Table 26 Approximate Copper Trace Current Capability Per IPC-2221 Charts.............................87
Table 27 Trace Parameters ........................................................................................................94
Table 28 PCI Express 1.1 Trace Routing Guidelines.....................................................................96

Page 10 of 103 COM Express Carrier Type 2
Design Guide
Table 29 USB Trace Routing Guidelines ..................................................................................... 97
Table 30 SDVO Trace Routing Guidelines .................................................................................. 98
Table 31 LAN Trace Routing Guidelines..................................................................................... 99
Table 32 Serial ATA Trace Routing Guidelines.......................................................................... 100
Table 33 LVDS Trace Routing Guidelines ................................................................................. 101
Table 34 PCI Trace Routing Guidelines .................................................................................... 102
Table 35 IDE Trace Routing Guidelines .................................................................................... 103
Table 36 LPC Trace Routing Guidelines.................................................................................... 103