Emerson COM Express Carrier Guide

COM Express Carrier Type 2
Design Guide
October 2009
Confidential and Proprietary

Page 2 of 103 COM Express Carrier Type 2
Design Guide
Copyright
© Copyright 2009 Emerson Network Power
All rights reserved.
Emerson Network Power is registered in the U.S. Patent and Trademark offices.
All other product or service names mentioned in this document are the property of their respective
owners.
All the material herein is Emerson Confidential Proprietary and is subject to Emerson
standards for controlling proprietary material. Use of this material is restricted to
Emerson employees with a need to know, and others with a need to know that are
subject to a confidentiality agreement.
Information must be kept out of view of persons not having a need to know. When
printed information is not in use, it must be stored in a locked cabinet, desk or
approved Controlled Access Area. Digital information should have access control and
files should be locked for access only by authorized individuals.

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Table of Contents
1About this Document ..........................................13
1.1 Introduction..................................................................................13
1.2 Intended Audience ........................................................................13
1.3 Acronyms and Abbreviations .........................................................13
2Carrier Board Connector ......................................16
2.1 Connectors Description .................................................................16
2.2 Connectors Land Pattern and Alignment........................................16
3PCI Express Lanes 0—5 ..........................................18
3.1 Introduction..................................................................................18
3.2 COM Express PCIe Signals Definition ..............................................18
3.3 PCIE Feature Support .....................................................................20
3.3.1 Polarity Inversion.........................................................................................................20
3.3.2 Lane Reversal ..............................................................................................................20
3.4 PCIE Schematic Example ................................................................20
3.4.1 PCIE Reference Clock ..................................................................................................20
3.4.2 PCIE Signals AC Couple................................................................................................22
3.4.3 X1 Slot Example ..........................................................................................................23
3.4.4 x4 Slot.........................................................................................................................24
3.4.5 Express Card Example..................................................................................................24
3.4.6 PCI Express Mini Card ..................................................................................................26
3.5 PCI Express Signals—Routing Consideration....................................27
4PCIe Graphics (PCIe 16—31) and SDVO ..................29

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4.1 PCIe Graphics (PEG) Configuration .................................................32
4.1.1 Using as External Graphic Card.................................................................................... 32
4.1.2 Using as SDVO............................................................................................................ 32
4.1.3 Using as General PCI Express Lanes ............................................................................. 32
4.2 Schematic Examples ......................................................................33
4.2.1 x16 PCIE Graphic Card................................................................................................. 33
4.2.2 SDVO to DVI Inverter .................................................................................................. 34
4.3 Routing Consideration...................................................................35
5LAN .....................................................................37
5.1 LAN Signals Definition ...................................................................37
5.2 Emerson LAN LED Definition ..........................................................38
5.3 Example Schematic .......................................................................38
5.4 Layout Consideration.....................................................................38
6USB Ports.............................................................39
6.1 USB Carrier Signals Definition ........................................................39
6.2 Reference Schematic .....................................................................40
6.3 Layout Consideration.....................................................................40
7SATA....................................................................41
7.1 SATA Signals Definition..................................................................42
7.2 Reference Schematic .....................................................................43
7.3 Layout Consideration.....................................................................44
8LVDS....................................................................45
8.1 LVDS Signals Description ...............................................................45

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8.1.1 Connector and Cable Considerations...........................................................................46
8.1.2 Display Timing Configuration ......................................................................................47
8.1.3 Backlight Control ........................................................................................................47
8.1.4 Color Mapping and Terms ...........................................................................................48
8.2 Reference Schematic .....................................................................50
8.3 Layout Considerations ...................................................................50
9VGA .....................................................................51
9.1 VGA Signals Definition ...................................................................51
9.2 Reference Schematic .....................................................................51
9.3 Layout Consideration.....................................................................51
10 IDE and Compact Flash.........................................53
10.1 IDE Signals Definition ....................................................................53
10.2 Reference Schematic .....................................................................54
10.2.1 40-pin IDE Header...................................................................................................54
10.2.2 44-pin IDE Header...................................................................................................55
10.2.3 5-pin Compact Flash Header...................................................................................56
10.3 Layout Consideration.....................................................................57
11 PCI.......................................................................58
11.1 PCI Signals Definition.....................................................................58
11.2 PCI Resource Assignment...............................................................62
11.3 Reference Schematic .....................................................................62
11.3.1 Device-Down example............................................................................................62
11.3.2 PCI Bus Slot Example...............................................................................................64
11.4 Layout Consideration.....................................................................64

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12 LPC ......................................................................66
12.1 LPC Signals Definition ....................................................................66
12.2 Reference Schematic .....................................................................66
12.2.1 FWH Schematic ..................................................................................................... 66
12.2.2 Super IO Schematic................................................................................................ 68
12.3 Layout Consideration.....................................................................69
12.3.1 General Signals ...................................................................................................... 69
12.3.2 Bus Clock Routing .................................................................................................. 69
13 AC’97 and HD Audio.............................................70
13.1 Signals Definition ..........................................................................70
13.2 Reference Schematic .....................................................................71
13.3 Layout Consideration.....................................................................72
14 TV OUT ................................................................74
14.1 TV-Out Signals Definition...............................................................74
14.2 Reference Schematic .....................................................................75
14.3 Layout Consideration.....................................................................75
15 SM bus and I2C .....................................................76
15.1 Signals Definition ..........................................................................76
15.2 I2C Address Allocation Consideration..............................................76
15.3 Layout Consideration.....................................................................77
16 Miscellaneous Signals ..........................................78
16.1 Module Type Detection..................................................................78

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16.2 Power Management Signals ..........................................................79
16.3 Watch Dog ....................................................................................81
16.4 Speaker.........................................................................................81
16.5 RTC Battery ...................................................................................82
16.6 GPIO..............................................................................................83
17 Thermal Signals ...................................................85
18 Power and Reset..................................................86
18.1 VCC12V .........................................................................................86
18.2 VCC5V_STB....................................................................................86
18.3 VCC_RTC .......................................................................................86
18.4 Copper Trace Size and Current Capacity .........................................86
18.5 Reset Signals Definitions................................................................87
19 BIOS Consideration..............................................88
19.1 Legacy versus Legacy Free .............................................................88
19.2 Carrier Super I/O Support...............................................................88
20 Mechanical Consideration ...................................89
20.1 Form Factor...................................................................................89
20.2 Heat Spreader ...............................................................................90
21 Layout Guidelines ................................................91
21.1 PCB Stack-ups................................................................................91

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21.1.1 Four-Layer Stack-up ............................................................................................... 91
21.1.2 Six-Layer Stack-up.................................................................................................. 91
21.1.3 Eight-Layer Stack-up .............................................................................................. 92
21.2 Trace-Impedance Considerations...................................................92
21.3 Routing Rules for High-Speed Differential Interfaces ......................94
21.3.1 PCI Express 1.1 Trace Routing Guidelines ............................................................... 96
21.3.2 USB Trace Routing Guidelines ................................................................................ 97
21.3.3 PEG 1.1 Trace Routing Guidelines........................................................................... 97
21.3.4 SDVO Trace Routing Guidelines ............................................................................. 98
21.3.5 LAN Trace Routing Guidelines ................................................................................ 99
21.3.6 Serial ATA Trace Routing Guidelines..................................................................... 100
21.3.7 LVDS Trace Routing Guidelines ............................................................................ 101
21.4 Routing Rules for Single-Ended Interfaces ....................................101
21.4.1 PCI Trace Routing Guidelines................................................................................ 102
21.4.2 IDE Trace Routing Guidelines ............................................................................... 103
21.4.3 LPC Trace Routing Guidelines............................................................................... 103

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List of Tables
Table 1 Available Carrier Board COM Express Connector Source...............................................16
Table 2 PCIe Signal Definition ..................................................................................................18
Table 3 Support Signals for ExpressCard ..................................................................................25
Table 4 PEG Signal Description ................................................................................................29
Table 5 SDVO Layout Requirement..........................................................................................36
Table 6 LAN Interface Signal Description..................................................................................37
Table 7 USB Signals Definition .................................................................................................39
Table 8 SATA Signal Definition.................................................................................................42
Table 9 SATA Connector Pinout ...............................................................................................42
Table 10 SATA Power Connector Pinout.....................................................................................42
Table 11 LVDS Signals Description.............................................................................................46
Table 12 LVDS Display Terms and Definitions ............................................................................49
Table 13 IDE Signals Description................................................................................................53
Table 14 PCI Signals Definition ..................................................................................................58
Table 15 PCI Bus Interrupt Routing ............................................................................................62
Table 16 LPC Interface Signal.....................................................................................................66
Table 17 Audio Codec Description of Signals .............................................................................70
Table 18 TV-Out Definition of Signals ........................................................................................74
Table 19 COM Express SMBus and I2C Signal Groups ..................................................................76
Table 20 Miscellaneous Signals..................................................................................................78
Table 21 Module Type Detection...............................................................................................79
Table 22 System States S0—S5 Definitions .................................................................................80
Table 23 Power Management Signal Description .......................................................................80
Table 24 GPIO Signal Definition .................................................................................................83
Table 25 Thermal Management Signal Description....................................................................85
Table 26 Approximate Copper Trace Current Capability Per IPC-2221 Charts.............................87
Table 27 Trace Parameters ........................................................................................................94
Table 28 PCI Express 1.1 Trace Routing Guidelines.....................................................................96

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Table 29 USB Trace Routing Guidelines ..................................................................................... 97
Table 30 SDVO Trace Routing Guidelines .................................................................................. 98
Table 31 LAN Trace Routing Guidelines..................................................................................... 99
Table 32 Serial ATA Trace Routing Guidelines.......................................................................... 100
Table 33 LVDS Trace Routing Guidelines ................................................................................. 101
Table 34 PCI Trace Routing Guidelines .................................................................................... 102
Table 35 IDE Trace Routing Guidelines .................................................................................... 103
Table 36 LPC Trace Routing Guidelines.................................................................................... 103

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List of Figures
Figure 1 COM Express Type 2 Connector...................................................................................17
Figure 2 PCI Express Clock Reference Schematic .......................................................................21
Figure 3 PCIe Rx Coupling Capacitors........................................................................................22
Figure 4 PCIe x1 Reference Schematic.......................................................................................23
Figure 5 PCIe x4 Reference Schematic.......................................................................................24
Figure 6 PCI Express: ExpressCard Example ...............................................................................25
Figure 7 PCI Express Mini Card Example ....................................................................................27
Figure 9 x1, x4, x8, x16 Slot.......................................................................................................33
Figure 10 SDVO to DVI Transmitter Example (Part 1) ..................................................................34
Figure 11 SDVO to DVI Transmitter Example (Part 1) ..................................................................35
Figure 12 10/100/1000 Mbps LAN Example ................................................................................38
Figure 13 USB Ports Reference Schematic...................................................................................40
Figure 14 SATA Connector..........................................................................................................41
Figure 14 SATA Connector Diagram............................................................................................43
Figure 16 LVDS Reference Schematic..........................................................................................50
Figure 17 VGA Reference Schematic...........................................................................................51
Figure 18 40-pin IDE Example .....................................................................................................55
Figure 19 44-pin IDE Example .....................................................................................................56
Figure 20 50-pin CompactFlash Header Example ........................................................................57
Figure 21 PCI Clock Buffer Circuitry.............................................................................................63
Figure 22 PCI Device Down Example (Dual UART) .......................................................................63
Figure 23 PCI Slot 5 V, 32-bit / 33 MHz Schematic .......................................................................64
Figure 24 LPC Firmware Hub—Carrier Board BIOS Schematic .......................................................67
Figure 25 LPC Super I/O Example ................................................................................................68
Figure 26 AC’97 Schematic Example...........................................................................................71
Figure 27 Audio Amplifier ...........................................................................................................71
Figure 28 HDA Example Schematic .............................................................................................72
Figure 29 TV-Out Reference Schematic.......................................................................................75

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Figure 30 Module Type 2 Detection Circuitry.............................................................................. 79
Figure 31 Watchdog Timer Event Latch Schematic..................................................................... 81
Figure 32 Speaker Output Circuitry ............................................................................................ 82
Figure 33 RTC Battery Circuitry and Serial Schottky Diode .......................................................... 83
Figure 34 GPIO Loop-Back Schematic......................................................................................... 84
Figure 35 Mechanical Comparison of Available Com Express Form Factors ................................. 89
Figure 36 Heat Spreader Used on COMX-ATOM-420 COM Express Module................................. 90
Figure 37 Four Layer Stack-Up.................................................................................................... 91
Figure 38 Six Layer Stack-Up....................................................................................................... 91
Figure 39 Eight Layer Stack-Up................................................................................................... 92
Figure 40 Microstrip Cross Section ............................................................................................. 93
Figure 41 Stripline Cross Section ................................................................................................ 93
Figure 42 Layout Considerations ................................................................................................ 95

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1About this Document
1.1 Introduction
The COM Express module standard is defined by PICMG. It is an open standard and is supported by
many embedded computing vendors. This provides customers with a wide range and reliable selection
of COM Express modules to choose from. This helps customers focus on their core business and speed
up time-to-market.
This document provides information for designing a custom system carrier board for Type 2 COM
Express modules. It includes reference schematics and layout considerations for the external circuitry
required to implement the various COM Express peripheral functions. It also explains how to extend
the supported buses and how to add additional peripherals and expansion slots to a COM Express-
based system.
1.2 Intended Audience
The intended audience of this document are COM Express carrier board designers. It is strongly
recommended to use the latest COM Express Specification and the module vendor’s product manuals
with this document.
1.3 Acronyms and Abbreviations
Item Description
AC ‘97 Audio Coder-Decoder 1997
An Intel-defined format to digitally encode and decode audio signals.
ATX Advanced Technology Extended
An Intel-defined form factor for motherboards.
BIOS Basic Input Output System
This software runs from non-volatile memory on the module or on the carrier board,
initializes a system, and allocates resources before the operating system takes over.
COM Express A computer-on-module form factor standard for small modules as defined by PICMG.
This form factor is for mezzanine-style CPU modules that incorporate a rich set of high-
speed serial interfaces such as PCIe, SATA, USB, GBE, and flat-panel LVDS.
PICMG refers to the standard as both COM.0 and COM Express.
CRT Cathode Ray Tube

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GBE Gigabit Ethernet
HD Audio High Definition Audio
I2C Inter Integrated Circuit
A signaling scheme that uses two wires to allow communication between integrated
circuits. This reads and loads register values.
IDE Integrated Device Electronics
IDE is synonymous with PATA and is a hard-disk standard that uses a single-ended,
parallel-bus interconnect.
JEDEC Industry standards organization (originally known as the Joint Electron Device
Engineering Council)
JEDEC standards cover memory modules, memory sockets, IC packaging, memory chip
organizations, and more.
Legacy Free A system without a PS2 keyboard/mouse controller. The keyboard and mouse, if used,
are plugged into USB ports.
LPC Low Pin Count
An Intel-defined standard for attaching low-bandwidth peripherals such as serial ports,
keyboard controllers, and Super I/Os to a computer system. As the name implies, few
pins are involved, making LPC easy to implement.
LVDS Low Voltage Differential Signaling
Many modern high-speed interfaces, such as PCIe and SATA, are LVDS interfaces.
However, the term LVDS commonly refers to a serialized differential interface, which is
used for flat-panel interfacing. In this document and in the COM Express Specification,
LVDS refers primarily to a flat-panel interface
MAC Media Access Controller
The digital hardware control section of a LAN implementation.
MicroATX An Intel-defined form factor size for motherboards: 9.6 in x 9.6 in
Microstrip A constant-width PCB trace on an outer PCB layer that is a fixed height above a
reference plane.
PATA Parallel AT Attachment
A hard disk standard (synonymous with IDE) that uses a single-ended parallel bus
interconnect.
PHY Physical layer interface of a LAN implementation.
The physical layer drives physical media such as the twisted pair cable.
PICMG PCI Industrial Computer Manufacturing Group
A non-profit industry trade group that issues and maintains technical standards to
manufacturers of embedded and industrial computer boards and systems.
SATA Serial AT Attachment
A high-speed serial-interconnect standard for hard disks. SATA is electrically quite

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different from PATA or IDE, but SATA software protocols are backwards compatible with
PATA.
SMBus System Management (SM) Bus
A two-wire, bidirectional bus (clock and serial data) that is used for system
management such as reading parameters from a memory card and reading
temperatures and voltages of system components.
The SMBus uses the same signaling scheme as an I2C bus.
Stripline A constant width internal layer PCB trace that is sandwiched between two reference
planes. If the stripline trace is equidistant between the two reference planes, it is said to
be symmetric or balanced. If the stripline trace is closer to on of the planes, it is said to
be asymmetric or unbalanced.
TMDS Transition Minimized Differential Signaling
A low voltage differential signaling scheme for flat-panel displays that is an alternative
to flat-panel LVDS. TMDS uses 8b/10b encoding to achieve DC balance and is used for
DVD-D displays
USB Universal Serial Bus
A hot-pluggable serial I/O interconnect standard.
VESA Video Electronics Standards Association
An industry trade group that issues standards for CRT and flat-panel displays.

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2Carrier Board Connector
2.1 Connectors Description
The carrier board connector for module pinout Type 2 shall be a 440-pin plug that is composed of two
pieces of a 220-pin, 0.5 mm pitch plug. The pair of connectors may be held together by a plastic carrier
during assembly to allow handling by automated assembly equipment.
The connectors shall be qualified for LVDS operation up to 6.25 GHz, to support PCI Express Generation
2 signaling speeds. The carrier board plugs are available in a variety of heights. The carrier board shall
use either the 5 mm or 8 mm heights.
Table 1 Available Carrier Board COM Express Connector Source
Type Height Part Number Notes
Single connector 5 mm Tyco 3-1827253-6 220 pos., 0.5 mm, Plug
Connector pair 5 mm Tyco 3-1827233-6 220 pos., 0.5 mm, Plug with hold carrier
Single connector 8 mm Tyco 3-6318491-6 220 pos., 0.5 mm, Plug
Connector pair 8 mm Tyco 3-5353652-6 220 pos., 0.5 mm, Plug with hold carrier
For the carrier board connector figure, see Figure 6-4 in the COM Express specification.
The following section details the COM Express signals group.
2.2 Connectors Land Pattern and Alignment
It is extremely important that the designers of carrier boards ensure that the COM Express connectors
have the proper land patterns and that the connectors are aligned correctly. The land pattern is
diagrammed in the COM Express specification. Connector alignment is ensured if the peg location
holes in the PCB connector pattern are in the correct positions (as shown in the land pattern of the
COM Express specification) and if the holes are drilled to the proper size and tolerance by the PCB
fabricator.

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Figure 1 COM Express Type 2 Connector

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3PCI Express Lanes 0—5
3.1 Introduction
The PCI Express provides a scalable, high-speed, serial I/O point-to-point bus connection. A PCI Express
lane consists of dual simplex channels, each implemented as a low-voltage differentially driven
transmit pair and receive pair. They are used for simultaneous transmission in each direction. The
bandwidth of a PCI Express link can be scaled by adding signal pairs to form multiple lanes between
two devices. The PCI Express specification defines x1, x4, x8, x16, and x32 link widths. Each single lane
has a raw data transfer rate of 2.5 Gbps at 1.25 GHz.
PCIe is easy to work with, but design rules must be followed. The most important design rule is that the
PCIe lanes must be routed as differential pairs. Routing a PCIe link is often easier than routing a
traditional 32 bit wide PCI bus, as there are fewer lines (two data pairs and a clock pair for a PCIe x1 link
as opposed to over 50 lines for parallel PCI). Routing a PCIe x16 graphics link is much easier than
routing an AGP 8X link, as the constraints required for the PCIe implementation are much easier than
those for AGP.
The source specifications for PCI Express include the PCI Express Base Specification, the PCI Express
Card Electromechanical Specification and the PCI Express Mini Card Electromechanical Specification.
3.2 COM Express PCIe Signals Definition
The general purpose PCI Express interface of the COM Express Type 2 module on the COM Express A-B
connector consists of up to six lanes, each with a receive and transmit differential signal pair
designated from PCIE_RX0 (+ and -) to PCIE_RX5 (+ and -) and correspondingly from PCIE_TX0 (+ and -)
to PCIE_TX5 (+ and -). The six lanes may be grouped into various link widths as defined in the COM
Express specification.
According to the COM Express Specification, the PCIe lanes on the A-B connector can be configured as
up to six PCI Express x1 links or may be combined into various combinations of x4, x2 and x1 links that
add up to a total of six lanes. These configuration possibilities are based on the COM Express module's
chipset capabilities.
The lane configuration possibilities of the PCI Express interface of a COM Express module are
dependent on the module's chipset. Some module and chipset implementations may allow software or
setup screen configuration of link width (x1, x4). Others may require a hardware strap or build option
on the module to configure the x4 option. The COM Express Specification does not allocate any
module pins for strapping PCIe lane width options.
Table 2 PCIe Signal Definition
Signal Pin Description I/O Comment
PCIE_RX0+
PCIE_RX0-
B68
B69
PCIe channel 0. Receive Input
differential pair.
I PCIE

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PCIE_TX0+
PCIE_TX0-
A68
A69
PCIe channel 0. Transmit
Output differential pair.
O PCIE
PCIE_RX1+
PCIE_RX1-
B64
B65
PCIe channel 1. Receive Input
differential pair.
I PCIE
PCIE_TX1+
PCIE_TX1-
A64
A65
PCIe channel 1. Transmit
Output differential pair.
O PCIE
PCIE_RX2+
PCIE_RX2-
B61
B62
PCIe channel 2. Receive Input
differential pair.
I PCIE
PCIE_TX2+
PCIE_TX2-
A61
A62
PCIe channel 2. Transmit
Output differential pair.
O PCIE
PCIE_RX3+
PCIE_RX3-
B58
B59
PCIe channel 3. Receive Input
differential pair.
I PCIE
PCIE_TX3+
PCIE_TX3-
A58
A59
PCIe channel 3. Transmit
Output differential pair.
O PCIE
PCIE_RX4+
PCIE_RX4-
B55
B56
PCIe channel 4. Receive Input
differential pair.
I PCIE
PCIE_TX4+
PCIE_TX4-
A55
A56
PCIe channel 4. Transmit
Output differential pair.
O PCIE
PCIE_RX5+
PCIE_RX5-
B52
B53
PCIe channel 5. Receive Input
differential pair.
I PCIE
PCIE_TX5+
PCIE_TX5-
A52
A53
PCIe channel 4. Transmit
Output differential pair.
O PCIE
PCI_CLK_REF+
PCIE_CLK_REF-
A88
A89
PCIe reference clock for all COM
Express PCIe lanes, and for PEG
lanes.
O PCIE COM Express only
allocates a single ref
clock
EXCD0_CPPE# A49 PCI ExpressCard0: PCI Express
capable card request, active
low, one per card
I CMOS
EXCD0_PERST# A48 PCI ExpressCard0: reset, active
low, one per card
O CMOS
EXCD1_CPPE# B48 PCI ExpressCard1: PCI Express
capable card request, active
low, one per card
I CMOS
EXCD1_PERST# B47 PCI ExpressCard1: reset, active
low, one per card
O CMOS
CB_RESET# B50 Reset output from module to
carrier board. Active low. Issued
by module chipset and may
result from a low SYS_RESET#
input, a low PWR_OK input, a
O CMOS
Suspend

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VCC_12V power input that falls
below the minimum
specification, a watchdog
timeout, or may be initiated by
the module software.
PCI_RESET# C23 PCI reset output, active low. O CMOS
Suspend
WAKE0# B66 PCI Express wake up signal I CMOS
The COM Express supports up to two ExpressCard through EXCDx_PERST# and EXCDx_CPPE#
signals.
For information on the supported number and configuration of PCI Express lanes of a specific
COM Express module, see the corresponding user’s manual or contact an Emerson Application
Engineer.
The PCI_RESET# or CB_RESET# either can be used as PCI Express device reset input.
The signals input and output is from COM Express module view.
3.3 PCIE Feature Support
3.3.1 Polarity Inversion
According to the PCI Express Card Electromechanical Specification, all PCIe devices must support
polarity inversion on each PCIe lane, independent of the other lanes. This means that you can route the
module’s PCIE_TX0+ signal to the corresponding ‘—’ pin on the slot or target device, and the PCIE_TX0-
signal to the corresponding ‘+’ pin. If this makes the layout cleaner, with fewer layer transitions and
better differential pairs, then take advantage of this PCIe feature.
3.3.2 Lane Reversal
PCIe lane reversal is not supported on the COM Express general purpose PCIe lanes according to the
COM Express Specification.
3.4 PCIE Schematic Example
3.4.1 PCIE Reference Clock
The COM Express Specification supports only a PCIe reference clock pair to be brought out of the
module. This clock is a 100 MHz differential pair and is sometimes known as a hint clock. The clock
allows the PLL in the target PCIe device to lock faster onto the embedded clock in the PCIe bit stream.