Epson S1C6S3N2 User manual

MF859-06
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C6S3N2 Technical Hardware/S1C6S3N2 Technical Software
S1C6S3N2

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001 All rights reserved.

PREFACE
This manual is individualy described about the hardware and the software
of the S1C6S3N2.
I. S1C6S3N2 Technical Hardware
This part explains the function of the S1C6S3N2, the circuit configu-
rations, and details the controlling method.
II. S1C6S3N2 Technical Software
This part explains the programming method of the S1C6S3N2.
Software
Hardware

The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C60 Family processors
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
S1 C60N01 F0A01 Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C60R08 D1 1Packing specification
Version (1: Version 1 ∗2)
Tool type (D1: Development Tool ∗1)
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
S1C62 Family processors
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
KIT6003
KIT6004
KIT6007
New No.
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
00
00

HardwareHardware
S1C6S3N2
I. Technical Hardware

HardwareHardware
S1C6S3N2 TECHNICAL HARDWARE EPSON I-i
CONTENTS
CONTENTS
CHAPTER 1 OVERVIEW....................................................................... I-1
1.1 Configuration ................................................................... I-1
1.2 Features .......................................................................... I-2
1.3 Block Diagram ................................................................. I-3
1.4 Pin Layout Diagram......................................................... I-4
1.5 Pin Description ................................................................ I-5
CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-6
2.1 Power Supply .................................................................. I-6
2.2 Initial Reset..................................................................... I-10
Reset pin (RESET) ................................................... I-11
Simultaneous high input to input ports (K00–K03) .. I-11
Watchdog timer (Auxiliary reset).............................. I-11
Oscillation detection circuit (Auxiliary reset)............ I-12
Internal register at initial setting ............................. I-12
2.3 Test Terminal (TEST)..................................................... I-12
CHAPTER 3 CPU, ROM, RAM ............................................................ I-13
3.1 CPU................................................................................ I-13
3.2 ROM ............................................................................... I-14
3.3 RAM ............................................................................... I-15
CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-16
4.1 Memory Map .................................................................. I-16
4.2 Resetting Watchdog Timer............................................. I-24
Configuration of watchdog timer.............................. I-24
Mask option ............................................................ I-24
Control of watchdog timer ....................................... I-25
Programming note................................................... I-25

I-ii EPSON S1C6S3N2 TECHNICAL HARDWARE
CONTENTS
4.3 Oscillation Circuit............................................................ I-26
OSC1 oscillation circuit........................................... I-26
OSC3 oscillation circuit........................................... I-26
Configuration of oscillation circuit........................... I-28
Control of oscillation circuit .................................... I-29
Programming notes ................................................. I-30
4.4 Input Ports (K00–K03, K10) ........................................... I-31
Configuration of input ports .................................... I-31
Differential registers and interrupt function ............ I-32
Mask option ............................................................ I-34
Control of input ports.............................................. I-35
Programming notes ................................................. I-37
4.5 Output Ports (R00–R03, R10–R13) ............................... I-40
Configuration of output ports .................................. I-40
Mask option ............................................................ I-40
Control of output ports............................................ I-43
Programming note................................................... I-45
4.6 I/O Ports (P00–P03, P10–P13) ...................................... I-46
Configuration of I/O ports....................................... I-46
I/O control register and I/O mode........................... I-47
Mask option ............................................................ I-47
Control of I/O ports ................................................ I-48
Programming notes ................................................. I-50
4.7 LCD Driver (COM0–3, SEG0–37) .................................. I-51
Configuration of LCD driver..................................... I-51
Switching between dynamic and ALL OFF ............... I-56
Mask option (segment allocation)............................. I-57
Control of LCD driver .............................................. I-59
Programming notes ................................................. I-60
4.8 Clock Timer .................................................................... I-61
Configuration of clock timer .................................... I-61
Interrupt function ................................................... I-62
Control of clock timer.............................................. I-63
Programming notes ................................................. I-65

HardwareHardware
S1C6S3N2 TECHNICAL HARDWARE EPSON I-iii
CONTENTS
4.9 Stopwatch Counter......................................................... I-66
Configuration of stopwatch counter......................... I-66
Count-up pattern .................................................... I-67
Interrupt function ................................................... I-68
Control of stopwatch counter .................................. I-69
Programming notes ................................................. I-72
4.10 Event Counter ................................................................ I-73
Configuration of event counter ................................ I-73
Operation of event counter ...................................... I-73
Mask option ............................................................ I-74
Control of event counter.......................................... I-75
Programming note................................................... I-76
4.11 Analog Comparator ........................................................ I-77
Configuration of analog comparator ........................ I-77
Operation of analog comparator .............................. I-77
Control of analog comparator .................................. I-78
Programming notes ................................................. I-79
4.12 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................. I-80
Configuration of SVD circuit.................................... I-80
Heavy load protection function ................................ I-81
Detection timing of SVD circuit ............................... I-82
Control of SVD circuit ............................................. I-84
Programing notes .................................................... I-86
4.13 Interrupt and HALT......................................................... I-88
Interrupt factors...................................................... I-90
Specific masks and factor flags for interrupt............ I-91
Interrupt vectors ..................................................... I-92
Control of interrupt and HALT................................. I-93
Programming notes ................................................. I-96

I-iv EPSON S1C6S3N2 TECHNICAL HARDWARE
CONTENTS
CHAPTER 5 SUMMARY OF NOTES..................................................... I-97
5.1 Notes for Low Current Consumption .............................. I-97
5.2 Summary of Notes by Function ...................................... I-98
CHAPTER 6 DIAGRAM OF BASIC
EXTERNAL CONNECTIONS ........................................... I-104
CHAPTER 7 ELECTRICAL CHARACTERISTICS ................................... I-107
7.1 Absolute Maximum Rating ............................................ I-107
7.2 Recommended Operating Conditions ........................... I-108
7.3 DC Characteristics ........................................................ I-109
7.4 Analog Circuit Characteristics
and Consumed Current ................................................. I-111
7.5 Oscillation Characteristics ............................................. I-119
CHAPTER 8 PACKAGE ..................................................................... I-124
8.1 Plastic Package............................................................. I-124
8.2 Ceramic Package for Test Samples.............................. I-126
CHAPTER 9 PAD LAYOUT ................................................................. I-127
9.1 Diagram of Pad Layout.................................................. I-127
9.2 Pad Coordinates............................................................ I-128

S1C6S3N2 TECHNICAL HARDWARE EPSON I-1
CHAPTER 1: OVERVIEW
CHAPTER 1 OVERVIEW
The S1C6S3N2 Series is a single-chip microcomputer made
up of the 4-bit core CPU S1C6200A, ROM (2,048 words, 12
bits to a word), RAM (144 words, 4 bits to a word) LCD
driver circuit, analog comparator, event counter, watchdog
timer, and two types of time base counter. Because of its
low-voltage operation and low power consumption, this
series is ideal for a wide range of applications, and is espe-
cially suitable for battery-driven systems.
Furthermore, the S1C6S3N2 is a shrunk model of the
S1C62N32. It can be used as various controller applications
such as a clock, game and pager.
Configuration
The S1C6S3N2 Series is configured as follows, depending on
supply voltage and oscillation circuits.
Model S1C6S3N2 S1C6S3L2 S1C6S3B2 S1C6S3A2
Supply Voltage 1.8*–3.6 V 0.9–1.8 V 0.9–3.6 V 1.8*–3.6 V
External Supports Supports Not Supports
LCD 3.0 V 3.0 V supported 4.5/3.0 V
Power Supply LCD panels LCD panels LCD panels
Oscillation OSC1 only OSC1 and OSC3
Circuits (Single Clock) (Twin Clock)
1.1
*Applications that display with an LCD panel require at
least 2.2 V of supply voltage because a voltage less than
2.2 V lowers the LCD drive voltage.

I-2 EPSON S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 1: OVERVIEW
1.2 Features
*1 Selected by mask option
*2 The supply voltage range of the S1C6S3N2 and S1C6S3A2 is 2.2 to 3.6 V when
an LCD panel is used.
In this manual, BLD and SVD (supply voltage detection) have the same meaning.
OSC1 oscillation circuit
OSC3 oscillation circuit
Instruction sets
Instruction execution time
(differs depending oninstruction)
(CLK: CPU operation frequency)
ROM capacity
RAM capacity
Input ports
Output ports
Input/output ports
LCD driver
Time base counter
Watchdog timer
Event counter
Analog comparator
Supply voltage detection circuit (SVD)
External interrupt
Internal interrupt
Supply voltage *2
Consumed
current
(Typ. value)
Form when shipped
CLK = 32.768 kHz
(when halted)
CLK = 32.768 kHz
(when executed)
CLK = 1 MHz
(when executed)
Crystal oscillation circuit 32.768 kHz (Typ.)
No setting
100 types
153 µsec, 214 µsec, 366 µsec (CLK = 32.768 kHz)
2,048 words, 12 bits per word
144 words, 4 bits per word
5 bits (pull-down resistor can be added through mask option)
8 bits (BZ, BZ, FOUT outputs are available through mask option)
8 bits (pull-down resistor is added during input data read-out)
Either 38 segments ×4 or 3 or 2 common *1
V-3V 1/4 or 1/3 or 1/2 duty (regulated voltage circut and booster voltage circuit built-in)
Two types (timer and stopwatch)
Built-in (can be disabled through mask option)
One 8-bit inputs
Inverted input x 1, noninverted input x 1
Input port interrupt; dual system
Time base counter interrupt; dual system
80-pin QFP (plastic) or chip
CR or ceramic
oscillation circuit *1
1 MHz
(Typ.)
5 µsec, 7 µsec, 12 µsec
(CLK = 1 MHz)
S1C6S3N2 S1C6S3L2 S1C6S3B2 S1C6S3A2
2.4 V
3.0 V (1.8–3.6 V)
0.65 µA
2.0 µA
–
1.2 V
1.5 V (0.9–1.8 V)
0.65 µA
2.0 µA
–
1.2 V
1.5 V (0.9–3.6 V)
0.65 µA
2.0 µA
–
2.4 V
3.0 V (1.8–3.6 V)
1.5 µA
4.0 µA
150 µA

S1C6S3N2 TECHNICAL HARDWARE EPSON I-3
CHAPTER 1: OVERVIEW
Block Diagram1.3
Fig. 1.3.1
Block diagram
Power
Controller
LCD
Driver
Interrupt
Generator
Core CPU S1C6200A
OSC System
Reset
Control
COM0
|
COM3
SEG0
|
SEG37
V
DD
V L1
|
V L3
CA
|
CB
V
S1
V SS
K00–K03, K10
TEST
P00–P03
R00–R03
P10–P13
R10–R13
AMPP
AMPM
RESET OSC1 OSC2 OSC3 OSC4
RAM
144 x 4
ROM
2,048 x 12
Event
Counter
SVD
I Port
I/O Port
O Port
Comparator
Timer
Stop
Watch

I-4 EPSON S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 1: OVERVIEW
Pin Layout Diagram1.4
QFP5-80pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG17
TEST
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
Pin No. Pin Name
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG36
SEG37
AMPP
AMPM
K10
K03
K02
K01
K00
P03
P02
P01
P00
P13
P12
P11
P10
R03
R02
R01
Pin No. Pin Name
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
R00
R12
R11
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V L3
V L2
V L1
N.C.
CB
CA
COM3
Pin No. Pin Name
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
Pin No. Pin Name
N.C. : No connection
QFP14-80pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AMPP
AMPM
K10
K03
K02
K01
K00
P03
P02
P01
P00
P13
P12
P11
P10
R03
R02
R01
R00
R12
Pin No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
R11
R10
R13
V
SS
RESET
OSC4
OSC3
V
S1
OSC2
OSC1
V
DD
V L3
V L2
V L1
N.C.
CB
CA
COM3
COM2
COM1
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
TEST
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
Pin No.Pin Name Pin Name Pin Name Pin Name
N.C. : No connection
Fig. 1.4.1(a)
Pin layout diagram
Fig. 1.4.1(b)
Pin layout diagram
80
65
124
64 41
25
40
Index
Index
21
40
80
61
120
60 41

S1C6S3N2 TECHNICAL HARDWARE EPSON I-5
CHAPTER 1: OVERVIEW
1.5 Pin Description
Table 1.5.1 Pin description
*1 6S3N2/6S3L2/6S3B2:Not connected
6S3A2: CR or ceramic oscillation input terminal
(Switchable through mask option.)
*2 6S3N2/6S3L2/6S3B2:Not connected
6S3A2: CR or ceramic oscillation output terminal
(Switchable through mask option.)
VDD
VSS
VS1
VL1
VL2
VL3
CA, CB
OSC1
OSC2
OSC3
OSC4
K00–10
P00–13
R00–03
R10
R13
R11
R12
AMPP
AMPM
SEG0–37
COM0–3
RESET
TEST
53
46
50
56
55
54
58, 59
52
51
49
48
25–29
30–37
38–41
44
45
43
42
23
24
1, 3–22,
64–80
60–63
47
2
QFP5-80
Pin Name
(I)
(I)
–
–
–
–
–
I
O
I
O
I
I/O
O
O
O
O
O
I
I
O
O
I
I
Input/
Output
Power source positive terminal
Power source negative terminal
Constant voltage output terminal for oscillation
Function
Crystal oscillator input terminal
Crystal oscillator output terminal
*1
*2
Input terminal
Input/output terminal
Output terminal
Output terminal (Can output BZ through mask option.)
Output terminal (Can output BZ through mask option.)
Output terminal
Output terminal (Can output FOUT through mask option.)
Analog comparator noninverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal
(DC output available through mask option.)
LCD common output terminal
Initial setting input terminal
Test input terminal
Constant voltage output terminal for LCD (approx. -1.05 V)
Booster output terminal for LCD (VL1 × 2)
Booster output terminal for LCD (VL1 × 3)
Booster condenser connector terminal
31
24
28
34
33
32
36, 37
30
29
27
26
3–7
8–15
16–19
22
23
21
20
1
2
42–59,
61–80
38–41
25
60
QFP14-80
Pin Number

I-6 EPSON S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2
2.1
POWER SUPPLY AND INITIAL RESET
Power Supply
With a single external power supply (*1) supplied to VDD
through VSS, the S1C6S3N2 Series generates the necessary
internal voltage with the regulated voltage circuit (<VS1> for
oscillators, <VL1> for LCDs) and the voltage booster circuit
(<VL2, VL3> for LCDs). Or the S1C6S3N2 Series generates the
necessary internal voltage with the regulated voltage circuit
(<VS1> for oscillators, <VL2> for LCDs) and the voltage
booster circuit (<VL1, VL3> for LCDs).
Figures 2.1.1(a) and 2.1.1(b) show the configuration of
power supply.
*1 Supply voltage: 6S3N2 .. 1.8 (2.2)–3.6 V
6S3L2 .. 0.9–1.8 V
6S3B2 .. 0.9–3.6 V
6S3A2 .. 1.8 (2.2)–3.6 V
The values enclosed with ( ) are mini-
mum voltages for applications that use
LCD display.
- External loads cannot be driven by the regulated voltage and
voltage booster circuit's output voltage.
- See "7 ELECTRICAL CHARACTERISTICS" for voltage values.
Note

S1C6S3N2 TECHNICAL HARDWARE EPSON I-7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
External
power
supply
Internal
circuit
Oscillation
circuit
LCD driver
circuit
LCD system
voltage
booster circuit
Oscillation system
regulated voltage
circuit
LCD system
regulated voltage
circuit
V DD
V S1
V S1
V L1
V L1
V L2
V L3
CA
CB
V
SS
OSC1–4
COM0–3
SEG0–37
V L1
V L2
V L3
C 5
C 2
C 3
C 4
C 1
Fig. 2.1.1(a)
Example of configuration of
power supply
(S1C6S3L2/6S3B2)
External
power
supply
Internal
circuit
Oscillation
circuit
LCD driver
circuit
LCD system
voltage
booster/reducer
circuit
Oscillation system
regulated voltage
circuit
LCD system
regulated voltage
circuit
V DD
V S1
V S1
V L2
V L2
V L1
V L3
CA
CB
V
SS
OSC1–4
COM0–3
SEG0–37
V L2
V L1
V L3
C 5
C 2
C 3
C 4
C 1
Fig. 2.1.1(b)
Example of configuration of
power supply
(S1C6S3N2/6S3A2)

I-8 EPSON S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
The LCD system regulated voltage circuit use can be prohibited by
setting the mask option. In this case, external elements can be
minimized because the external capacitors for the LCD system
regulated voltage circuit are not necessary. However when the LCD
system regulated voltage circuit is not used, the display quality of
the LCD panel, when the supply voltage fluctuates (drops), is
inferior to when the LCD system regulated voltage circuit is used.
The S1C6S3B2 always uses the the LCD system regulated voltage
circuit, therefore the external capacitors are required.
Figure 2.1.2 shows the external elements when the the LCD sys-
tem regulated voltage circuit is not used.
• S1C6S3A2
4.5 V LCD panel
1/4, 1/3, 1/2 duty, 1/3 bias
Note: VL2 is shorted to VSS inside the IC.
• S1C6S3N2/S1C6S3A2
3 V LCD panel 3 V LCD panel
1/4, 1/3, 1/2 duty, 1/3 bias 1/4, 1/3, 1/2 duty, 1/2 bias
Note: VL3 is shorted to VSS inside the IC.
VDD
VS1
VL1
VL2
VL3
CA
CB
VSS
3 V
C5
C2
C3
C1
V DD
V S1
V L1
V L2
V L3
CA
CB
V
SS
3 V
C 5
C 2
C 1
• S1C6S3L2
3 V LCD panel
1/4, 1/3, 1/2 duty, 1/2 bias
VDD
VS1
VL1
VL2
VL3
CA
CB
VSS
3 V
C5
C2
C4
C1
VDD
VS1
VL1
VL2
VL3
CA
CB
VSS
1.5 V
C5
C4
C1
Note: VL1 is shorted to VSS inside the IC.
Fig. 2.1.2
External elements when
LCD system regulated
voltage circuit is not used