Epson S1C17M12 User manual

Rev. 1.2
CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M12/M13
Technical Manual

©
SEIKO EPSON CORPORATION 2021 , All rights reserved.
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(Rev. e1.0, 2021.9)

PREFACE
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.2)
Preface
This is a technical manual for designers and programmers who develop a product using the S1C17M12/M13.
This document describes the functions of the IC, embedded peripheral circuit operations, and their control
methods.
For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions
and operations of the debugging tools, refer to the respective tool manuals. (Our “Products: Document Down-
loads” website provides the downloadable manuals.)
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit Area” in
the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish from signal
and pin names.
XXX register: Represents a register including its all bits.
XXX.YYY bit: Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits: Represents the two control bits ZZZ1 and ZZZ0 in the XXX register.
Register table contents and symbols
Initial: Value set at initialization
Reset: Initialization condition. The initialization condition depends on the reset group (H0, H1, or S0).
For more information on the reset groups, refer to “Initialization Conditions (Reset Groups)” in the
“Power Supply, Reset, and Clocks” chapter.
R/W: R = Read only bit
W = Write only bit
WP = Write only bit with a write protection using the MSCPROT.PROT[15:0] bits
R/W = Read/write bit
R/WP = Read/write bit with a write protection using the MSCPROT.PROT[15:0] bits
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and except
when decimal or binary notation is required in terms of explanation). The values are described as shown
below according to the control bit width.
1 bit: 0 or 1
2 to 4 bits: 0x0 to 0xf
5 to 8 bits: 0x00 to 0xff
9 to 12 bits: 0x000 to 0xfff
13 to 16 bits: 0x0000 to 0xffff
Decimal: 0 to 9999...
Binary: 0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The peripheral
circuit chapters use ‘n’ as the value that represents the channel number in the register and pin names regard-
less of the number of channel actually implemented. Normally, the descriptions are applied to all channels.
If there is a channel that has different functions from others, the channel number is specified clearly.
Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in the
“Overview” chapter.

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– Contents –
Preface......................................................................................................................................i
Notational conventions and symbols in this manual ................................................................i
1 Overview........................................................................................................................1-1
1.1 Features .......................................................................................................................... 1-1
1.2 Block Diagram................................................................................................................. 1-3
1.3 Pins ................................................................................................................................. 1-4
1.3.1 Pin Configuration Diagram (TQFP12-48PIN) .................................................... 1-4
1.3.2 Pad Configuration Diagram (Chip).................................................................... 1-6
1.3.3 Pin Descriptions................................................................................................ 1-8
2 Power Supply, Reset, and Clocks ...............................................................................2-1
2.1 Power Generator (PWG).................................................................................................. 2-1
2.1.1 Overview ........................................................................................................... 2-1
2.1.2 Pins................................................................................................................... 2-1
2.1.3 VD1 Regulator Operation Mode......................................................................... 2-2
2.2 System Reset Controller (SRC)....................................................................................... 2-2
2.2.1 Overview ........................................................................................................... 2-2
2.2.2 Input Pin............................................................................................................ 2-3
2.2.3 Reset Sources .................................................................................................. 2-3
2.2.4 Initialization Conditions (Reset Groups)............................................................ 2-4
2.3 Clock Generator (CLG).................................................................................................... 2-4
2.3.1 Overview ........................................................................................................... 2-4
2.3.2 Input/Output Pins ............................................................................................. 2-5
2.3.3 Clock Sources .................................................................................................. 2-5
2.3.4 Operations ........................................................................................................ 2-6
2.4 Operating Mode .............................................................................................................. 2-9
2.4.1 Initial Boot Sequence........................................................................................ 2-9
2.4.2 Transition between Operating Modes.............................................................. 2-10
2.5 Interrupts........................................................................................................................ 2-11
2.6 Control Registers ........................................................................................................... 2-11
PWG VD1 Regulator Control Register ....................................................................................... 2-11
CLG System Clock Control Register........................................................................................ 2-11
CLG Oscillation Control Register ............................................................................................. 2-13
CLG OSC3 Control Register .................................................................................................... 2-13
CLG Interrupt Flag Register ..................................................................................................... 2-14
CLG Interrupt Enable Register ................................................................................................. 2-15
CLG FOUT Control Register..................................................................................................... 2-15
3 CPU and Debugger ......................................................................................................3-1
3.1 Overview ......................................................................................................................... 3-1
3.2 CPU Core........................................................................................................................ 3-2
3.2.1 CPU Registers .................................................................................................. 3-2
3.2.2 Instruction Set .................................................................................................. 3-2
3.2.3 Reading PSR .................................................................................................... 3-2
3.2.4 I/O Area Reserved for the S1C17 Core ............................................................ 3-2
3.3 Debugger ........................................................................................................................ 3-2
3.3.1 Debugging Functions........................................................................................ 3-2
3.3.2 Resource Requirements and Debugging Tools ................................................ 3-3
3.3.3 List of Debugger Input/Output Pins.................................................................. 3-3
3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-4

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3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-5
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting....................................................................... 4-2
4.3.3 Flash Programming........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers................................................................................ 4-3
4.5.1 System-Protect Function.................................................................................. 4-6
4.6 Control Registers ............................................................................................................ 4-7
MISC System Protect Register ................................................................................................. 4-7
MISC IRAM Size Register.......................................................................................................... 4-7
FLASHC Flash Read Cycle Register ......................................................................................... 4-7
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR)................................................................... 5-2
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-3
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI.................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-4
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register................................................................................ 5-5
ITC Interrupt Level Setup Register x......................................................................................... 5-5
6 I/O Ports (PPORT).........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-2
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell................................................... 6-2
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-2
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.2.5 High-/Low-level High-Current Drive Outputs ................................................... 6-3
6.3 Clock Settings................................................................................................................. 6-3
6.3.1 PPORT Operating Clock................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-3
6.3.3 Clock Supply in DEBUG Mode......................................................................... 6-3
6.4 Operations ...................................................................................................................... 6-4
6.4.1 Initialization ....................................................................................................... 6-4
6.4.2 Port Input/Output Control................................................................................. 6-5
6.5 Interrupts......................................................................................................................... 6-6
6.6 Control Registers ............................................................................................................ 6-7

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PxPort Data Register................................................................................................................ 6-7
PxPort Enable Register ............................................................................................................ 6-7
PxPort Pull-up/down Control Register..................................................................................... 6-7
PxPort Interrupt Flag Register.................................................................................................. 6-8
PxPort Interrupt Control Register............................................................................................. 6-8
PxPort Chattering Filter Enable Register.................................................................................. 6-8
PxPort Mode Select Register ................................................................................................... 6-9
PxPort Function Select Register .............................................................................................. 6-9
P Port Clock Control Register ................................................................................................... 6-9
P Port Interrupt Flag Group Register........................................................................................ 6-11
6.7 Control Register and Port Function Configuration of this IC ......................................... 6-12
6.7.1 P0 Port Group.................................................................................................. 6-12
6.7.2 P1 Port Group.................................................................................................. 6-13
6.7.3 P2 Port Group.................................................................................................. 6-14
6.7.4 P4 Port Group.................................................................................................. 6-15
6.7.5 P5 Port Group.................................................................................................. 6-16
6.7.6 Pd Port Group.................................................................................................. 6-17
6.7.7 Common Registers between Port Groups....................................................... 6-18
7 Universal Port Multiplexer (UPMUX)...........................................................................7-1
7.1 Overview ......................................................................................................................... 7-1
7.2 Peripheral Circuit I/O Function Assignment.................................................................... 7-1
7.3 Control Registers ............................................................................................................ 7-2
Pxy–xz Universal Port Multiplexer Setting Register................................................................... 7-2
8 Watchdog Timer (WDT2)..............................................................................................8-1
8.1 Overview ......................................................................................................................... 8-1
8.2 Clock Settings................................................................................................................. 8-1
8.2.1 WDT2 Operating Clock..................................................................................... 8-1
8.2.2 Clock Supply in DEBUG Mode......................................................................... 8-1
8.3 Operations ...................................................................................................................... 8-2
8.3.1 WDT2 Control ................................................................................................... 8-2
8.3.2 Operations in HALT and SLEEP Modes............................................................ 8-3
8.4 Control Registers ............................................................................................................ 8-3
WDT2 Clock Control Register ................................................................................................... 8-3
WDT2 Control Register ............................................................................................................. 8-4
WDT2 Counter Compare Match Register ................................................................................. 8-4
9 Supply Voltage Detector (SVD3)..................................................................................9-1
9.1 Overview ......................................................................................................................... 9-1
9.2 Input Pins and External Connection ............................................................................... 9-2
9.2.1 Input Pins.......................................................................................................... 9-2
9.2.2 External Connection ......................................................................................... 9-2
9.3 Clock Settings................................................................................................................. 9-2
9.3.1 SVD3 Operating Clock...................................................................................... 9-2
9.3.2 Clock Supply in SLEEP Mode .......................................................................... 9-2
9.3.3 Clock Supply in DEBUG Mode......................................................................... 9-3
9.4 Operations ...................................................................................................................... 9-3
9.4.1 SVD3 Control .................................................................................................... 9-3
9.4.2 SVD3 Operations .............................................................................................. 9-4
9.5 SVD3 Interrupt and Reset ............................................................................................... 9-4
9.5.1 SVD3 Interrupt .................................................................................................. 9-4
9.5.2 SVD3 Reset....................................................................................................... 9-5
9.6 Control Registers ............................................................................................................ 9-5

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SVD3 Clock Control Register .................................................................................................... 9-5
SVD3 Control Register .............................................................................................................. 9-6
SVD3 Status and Interrupt Flag Register .................................................................................. 9-7
SVD3 Interrupt Enable Register ................................................................................................ 9-8
10 16-bit Timers (T16).....................................................................................................10-1
10.1 Overview ...................................................................................................................... 10-1
10.2 Input Pin....................................................................................................................... 10-1
10.3 Clock Settings.............................................................................................................. 10-2
10.3.1 T16 Operating Clock...................................................................................... 10-2
10.3.2 Clock Supply in SLEEP Mode ....................................................................... 10-2
10.3.3 Clock Supply in DEBUG Mode...................................................................... 10-2
10.3.4 Event Counter Clock...................................................................................... 10-2
10.4 Operations ................................................................................................................... 10-2
10.4.1 Initialization .................................................................................................... 10-2
10.4.2 Counter Underflow ........................................................................................ 10-3
10.4.3 Operations in Repeat Mode........................................................................... 10-3
10.4.4 Operations in One-shot Mode ....................................................................... 10-3
10.4.5 Counter Value Read....................................................................................... 10-4
10.5 Interrupt........................................................................................................................ 10-4
10.6 Control Registers ......................................................................................................... 10-4
T16 Ch.nClock Control Register ............................................................................................. 10-4
T16 Ch.nMode Register .......................................................................................................... 10-5
T16 Ch.nControl Register........................................................................................................ 10-5
T16 Ch.nReload Data Register................................................................................................ 10-6
T16 Ch.nCounter Data Register .............................................................................................. 10-6
T16 Ch.nInterrupt Flag Register .............................................................................................. 10-6
T16 Ch.nInterrupt Enable Register.......................................................................................... 10-7
11 UART (UART3)............................................................................................................11-1
11.1 Overview ...................................................................................................................... 11-1
11.2 Input/Output Pins and External Connections .............................................................. 11-2
11.2.1 List of Input/Output Pins................................................................................ 11-2
11.2.2 External Connections .................................................................................... 11-2
11.2.3 Input Pin Pull-Up Function............................................................................. 11-2
11.2.4 Output Pin Open-Drain Output Function ...................................................... 11-2
11.2.5 Input/Output Signal Inverting Function.......................................................... 11-2
11.3 Clock Settings.............................................................................................................. 11-2
11.3.1 UART3 Operating Clock ................................................................................ 11-2
11.3.2 Clock Supply in SLEEP Mode ....................................................................... 11-3
11.3.3 Clock Supply in DEBUG Mode...................................................................... 11-3
11.3.4 Baud Rate Generator..................................................................................... 11-3
11.4 Data Format ................................................................................................................. 11-3
11.5 Operations ................................................................................................................... 11-4
11.5.1 Initialization .................................................................................................... 11-4
11.5.2 Data Transmission ......................................................................................... 11-5
11.5.3 Data Reception .............................................................................................. 11-6
11.5.4 IrDA Interface................................................................................................. 11-7
11.5.5 Carrier Modulation ......................................................................................... 11-7
11.6 Receive Errors.............................................................................................................. 11-8
11.6.1 Framing Error ................................................................................................. 11-8
11.6.2 Parity Error..................................................................................................... 11-8
11.6.3 Overrun Error ................................................................................................. 11-9
11.7 Interrupts...................................................................................................................... 11-9

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11.8 Control Registers ......................................................................................................... 11-9
UART3 Ch.nClock Control Register ........................................................................................ 11-9
UART3 Ch.nMode Register.................................................................................................... 11-10
UART3 Ch.nBaud–Rate Register ........................................................................................... 11-11
UART3 Ch.nControl Register ................................................................................................. 11-12
UART3 Ch.nTransmit Data Register ....................................................................................... 11-12
UART3 Ch.nReceive Data Register........................................................................................ 11-12
UART3 Ch.nStatus and Interrupt Flag Register ..................................................................... 11-13
UART3 Ch.nInterrupt Enable Register.................................................................................... 11-14
UART3 Ch.nCarrier Waveform Register ................................................................................. 11-14
12 Synchronous Serial Interface (SPIA)........................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Pin Functions in Master Mode and Slave Mode............................................ 12-3
12.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 12-3
12.3 Clock Settings.............................................................................................................. 12-3
12.3.1 SPIA Operating Clock.................................................................................... 12-3
12.3.2 Clock Supply in DEBUG Mode...................................................................... 12-4
12.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 12-4
12.4 Data Format ................................................................................................................. 12-5
12.5 Operations ................................................................................................................... 12-5
12.5.1 Initialization .................................................................................................... 12-5
12.5.2 Data Transmission in Master Mode ............................................................... 12-5
12.5.3 Data Reception in Master Mode.................................................................... 12-7
12.5.4 Terminating Data Transfer in Master Mode.................................................... 12-8
12.5.5 Data Transfer in Slave Mode.......................................................................... 12-8
12.5.6 Terminating Data Transfer in Slave Mode ..................................................... 12-10
12.6 Interrupts..................................................................................................................... 12-10
12.7 Control Registers ........................................................................................................ 12-11
SPIA Ch.nMode Register ....................................................................................................... 12-11
SPIA Ch.nControl Register..................................................................................................... 12-12
SPIA Ch.nTransmit Data Register .......................................................................................... 12-13
SPIA Ch.nReceive Data Register ........................................................................................... 12-13
SPIA Ch.nInterrupt Flag Register ........................................................................................... 12-13
SPIA Ch.nInterrupt Enable Register ....................................................................................... 12-14
13 I2C (I2C).......................................................................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.3 Clock Settings.............................................................................................................. 13-3
13.3.1 I2C Operating Clock ...................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode...................................................................... 13-3
13.3.3 Baud Rate Generator..................................................................................... 13-3
13.4 Operations ................................................................................................................... 13-4
13.4.1 Initialization .................................................................................................... 13-4
13.4.2 Data Transmission in Master Mode ............................................................... 13-5
13.4.3 Data Reception in Master Mode.................................................................... 13-7
13.4.4 10-bit Addressing in Master Mode ................................................................ 13-9
13.4.5 Data Transmission in Slave Mode................................................................. 13-10
13.4.6 Data Reception in Slave Mode ..................................................................... 13-12

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13.4.7 Slave Operations in 10-bit Address Mode.................................................... 13-14
13.4.8 Automatic Bus Clearing Operation ............................................................... 13-14
13.4.9 Error Detection.............................................................................................. 13-15
13.5 Interrupts..................................................................................................................... 13-16
13.6 Control Registers ........................................................................................................ 13-17
I2C Ch.nClock Control Register............................................................................................. 13-17
I2C Ch.nMode Register.......................................................................................................... 13-18
I2C Ch.nBaud-Rate Register.................................................................................................. 13-18
I2C Ch.nOwn Address Register ............................................................................................. 13-18
I2C Ch.nControl Register ....................................................................................................... 13-19
I2C Ch.nTransmit Data Register............................................................................................. 13-20
I2C Ch.nReceive Data Register.............................................................................................. 13-20
I2C Ch.nStatus and Interrupt Flag Register ........................................................................... 13-20
I2C Ch.nInterrupt Enable Register ......................................................................................... 13-21
14 16-bit PWM Timers (T16B) ........................................................................................14-1
14.1 Overview ...................................................................................................................... 14-1
14.2 Input/Output Pins......................................................................................................... 14-2
14.3 Clock Settings.............................................................................................................. 14-3
14.3.1 T16B Operating Clock ................................................................................... 14-3
14.3.2 Clock Supply in SLEEP Mode ....................................................................... 14-3
14.3.3 Clock Supply in DEBUG Mode...................................................................... 14-3
14.3.4 Event Counter Clock...................................................................................... 14-3
14.4 Operations ................................................................................................................... 14-4
14.4.1 Initialization .................................................................................................... 14-4
14.4.2 Counter Block Operations ............................................................................. 14-5
14.4.3 Comparator/Capture Block Operations......................................................... 14-8
14.4.4 TOUT Output Control ................................................................................... 14-16
14.5 Interrupt....................................................................................................................... 14-22
14.6 Control Registers ........................................................................................................ 14-22
T16B Ch.nClock Control Register.......................................................................................... 14-22
T16B Ch.nCounter Control Register ...................................................................................... 14-23
T16B Ch.nMax Counter Data Register................................................................................... 14-24
T16B Ch.nTimer Counter Data Register................................................................................. 14-24
T16B Ch.nCounter Status Register........................................................................................ 14-25
T16B Ch.nInterrupt Flag Register........................................................................................... 14-26
T16B Ch.nInterrupt Enable Register ...................................................................................... 14-27
T16B Ch.nComparator/Capture mControl Register.............................................................. 14-28
T16B Ch.nCompare/Capture mData Register....................................................................... 14-30
15 IR Remote Controller (REMC2) ................................................................................15-1
15.1 Overview ...................................................................................................................... 15-1
15.2 Input/Output Pins and External Connections .............................................................. 15-1
15.2.1 Output Pin...................................................................................................... 15-1
15.2.2 External Connections .................................................................................... 15-2
15.3 Clock Settings.............................................................................................................. 15-2
15.3.1 REMC2 Operating Clock ............................................................................... 15-2
15.3.2 Clock Supply in SLEEP Mode ....................................................................... 15-2
15.3.3 Clock Supply in DEBUG Mode...................................................................... 15-2
15.4 Operations ................................................................................................................... 15-2
15.4.1 Initialization .................................................................................................... 15-2
15.4.2 Data Transmission Procedures...................................................................... 15-3
15.4.3 REMO Output Waveform ............................................................................... 15-3
15.4.4 Continuous Data Transmission and Compare Buffers................................... 15-5
15.5 Interrupts...................................................................................................................... 15-6

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15.6 Application Example: Driving EL Lamp........................................................................ 15-7
15.7 Control Registers ......................................................................................................... 15-7
REMC2 Clock Control Register................................................................................................ 15-7
REMC2 Data Bit Counter Control Register .............................................................................. 15-8
REMC2 Data Bit Counter Register........................................................................................... 15-9
REMC2 Data Bit Active Pulse Length Register....................................................................... 15-10
REMC2 Data Bit Length Register............................................................................................ 15-10
REMC2 Status and Interrupt Flag Register............................................................................. 15-10
REMC2 Interrupt Enable Register ........................................................................................... 15-11
REMC2 Carrier Waveform Register......................................................................................... 15-11
REMC2 Carrier Modulation Control Register .......................................................................... 15-12
16 Seven-Segment LED Controller (LEDC) ..................................................................16-1
16.1 Overview ...................................................................................................................... 16-1
16.2 Output Pins and External Connections........................................................................ 16-2
16.2.1 List of Output Pins ......................................................................................... 16-2
16.2.2 External Connections .................................................................................... 16-2
16.3 Clock Settings.............................................................................................................. 16-2
16.3.1 LEDC Operating Clock .................................................................................. 16-2
16.3.2 Clock Supply in SLEEP Mode ....................................................................... 16-2
16.3.3 Clock Supply in DEBUG Mode...................................................................... 16-3
16.3.4 LED Lighting Cycle ........................................................................................ 16-3
16.4 Operations ................................................................................................................... 16-3
16.4.1 Initialization .................................................................................................... 16-3
16.4.2 Display On/Off ............................................................................................... 16-4
16.4.3 Common Mode.............................................................................................. 16-4
16.4.4 Number of Display Digits............................................................................... 16-4
16.4.5 Brightness Adjustment .................................................................................. 16-4
16.4.6 Display Data Registers .................................................................................. 16-5
16.4.7 Drive Waveform ............................................................................................. 16-5
16.5 Interrupt........................................................................................................................ 16-6
16.6 Control Registers ......................................................................................................... 16-6
LEDC Clock Control Register................................................................................................... 16-6
LEDC Control Register ............................................................................................................. 16-7
LEDC Lighting Period Setting Register .................................................................................... 16-8
LEDC Interrupt Flag Register ................................................................................................... 16-8
LEDC Interrupt Enable Register ............................................................................................... 16-8
LEDC COMxy Data Registers................................................................................................... 16-8
17 12-bit A/D Converter (ADC12A)................................................................................17-1
17.1 Overview ...................................................................................................................... 17-1
17.2 Input Pins and External Connections........................................................................... 17-2
17.2.1 List of Input Pins............................................................................................ 17-2
17.2.2 External Connections .................................................................................... 17-2
17.3 Clock Settings.............................................................................................................. 17-2
17.3.1 ADC12A Operating Clock.............................................................................. 17-2
17.3.2 Sampling Time............................................................................................... 17-2
17.4 Operations ................................................................................................................... 17-3
17.4.1 Initialization .................................................................................................... 17-3
17.4.2 Conversion Start Trigger Source.................................................................... 17-3
17.4.3 Conversion Mode and Analog Input Pin Settings.......................................... 17-4
17.4.4 A/D Conversion Operations and Control Procedures.................................... 17-4
17.5 Interrupts...................................................................................................................... 17-6
17.6 Control Registers ......................................................................................................... 17-6
ADC12A Ch.nControl Register ................................................................................................ 17-6

CONTENTS
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation ix
(Rev. 1.2)
ADC12A Ch.nTrigger/Analog Input Select Register ................................................................ 17-7
ADC12A Ch.nConfiguration Register ...................................................................................... 17-8
ADC12A Ch.nInterrupt Flag Register ...................................................................................... 17-9
ADC12A Ch.nInterrupt Enable Register ................................................................................. 17-10
ADC12A Ch.nResult Register m............................................................................................. 17-10
18 Multiplier/Divider (COPRO2).....................................................................................18-1
18.1 Overview ...................................................................................................................... 18-1
18.2 Operation Mode and Output Mode.............................................................................. 18-1
18.3 Multiplication................................................................................................................ 18-2
18.4 Division......................................................................................................................... 18-3
18.5 MAC ............................................................................................................................. 18-5
18.6 Reading Operation Results .......................................................................................... 18-7
19 Electrical Characteristics .........................................................................................19-1
19.1 Absolute Maximum Ratings ......................................................................................... 19-1
19.2 Recommended Operating Conditions ......................................................................... 19-1
19.3 Current Consumption................................................................................................... 19-2
19.4 System Reset Controller (SRC) Characteristics........................................................... 19-3
19.5 Clock Generator (CLG) Characteristics........................................................................ 19-4
19.6 Flash Memory Characteristics ..................................................................................... 19-5
19.7 Input/Output Port (PPORT) Characteristics ................................................................. 19-5
19.8 Supply Voltage Detector (SVD3) Characteristics ......................................................... 19-7
19.9 UART (UART3) Characteristics .................................................................................... 19-9
19.10 Synchronous Serial Interface (SPIA) Characteristics ................................................. 19-9
19.11 I2C (I2C) Characteristics............................................................................................ 19-10
19.12 12-bit A/D Converter (ADC12A) Characteristics ....................................................... 19-11
20 Basic External Connection Diagram .......................................................................20-1
21 Package......................................................................................................................21-1
Appendix A List of Peripheral Circuit Control Registers ......................................... AP-A-1
0x4000–0x4008 Misc Registers (MISC)................................................................. AP-A-1
0x4020 Power Generator (PWG).............................................................. AP-A-1
0x4040–0x4050 Clock Generator (CLG) ................................................................ AP-A-1
0x4080–0x4090 Interrupt Controller (ITC).............................................................. AP-A-2
0x40a0–0x40a4 Watchdog Timer (WDT2) ............................................................. AP-A-3
0x4100–0x4106 Supply Voltage Detector (SVD3).................................................. AP-A-3
0x4160–0x416c 16-bit Timer (T16) Ch.0................................................................ AP-A-4
0x41b0 Flash Controller (FLASHC) .......................................................... AP-A-4
0x4200–0x42e2 I/O Ports (PPORT) ....................................................................... AP-A-4
0x4300–0x4314 Universal Port Multiplexer (UPMUX)............................................ AP-A-8
0x4380–0x4390 UART (UART3) Ch.0 .................................................................... AP-A-9
0x43a0–0x43ac 16-bit Timer (T16) Ch.1............................................................... AP-A-10
0x43b0–0x43ba Synchronous Serial Interface (SPIA) Ch.0.................................. AP-A-11
0x43c0–0x43d2 I2C (I2C) Ch.0.............................................................................. AP-A-11
0x5000–0x501a 16-bit PWM Timer (T16B) Ch.0 .................................................. AP-A-12
0x5260–0x526c 16-bit Timer (T16) Ch.2............................................................... AP-A-14
0x5270–0x527a Synchronous Serial Interface (SPIA) Ch.1 .................................. AP-A-14
0x5320–0x5332 IR Remote Controller (REMC2)................................................... AP-A-15
0x5400–0x5414 Seven-Segment LED Controller (LEDC) ..................................... AP-A-16
0x5480–0x548c 16-bit Timer (T16) Ch.3............................................................... AP-A-16
0x54a2–0x54ba 12-bit A/D Converter (ADC12A).................................................. AP-A-17
0xffff90 Debugger (DBG) ......................................................................... AP-A-18

CONTENTS
xSeiko Epson Corporation S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Appendix B Power Saving .......................................................................................... AP-B-1
B.1 Operating Status Configuration Examples for Power Saving...................................... AP-B-1
B.2 Other Power Saving Methods ..................................................................................... AP-B-2
Appendix C Mounting Precautions............................................................................ AP-C-1
Appendix D Measures Against Noise ........................................................................ AP-D-1
Appendix E Initialization Routine ............................................................................... AP-E-1
Revision History

1 OVERVIEW
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.2)
1 Overview
The S1C17M12/M13 is a 16-bit embedded Flash MCU that features low power consumption. It includes various
serial interfaces and a seven-segment LED controller on the compact die. It is suitable for control panels with a
seven-segment display for housing equipment and FA equipment.
1.1 Features
Table 1.1.1 Features
Model S1C17M12 S1C17M13
CPU
CPU core Seiko Epson original 16-bit RISC CPU core S1C17
Other On-chip debugger
Embedded Flash memory
Capacity 16K bytes (for both instructions and data)
Erase/program count 1,000 times (min.)
Other Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Embedded RAM
Capacity 2K bytes
Clock generator (CLG)
System clock source 3 sources (IOSC/OSC3/EXOSC)
System clock frequency (operating frequency) 16.8 MHz (max.)
IOSC oscillator circuit (boot clock source) 700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU)
OSC3 oscillator circuit 16.8 MHz (max.) crystal/ceramic oscillator
4, 8, 12, and 16 MHz-switchable embedded oscillator
EXOSC clock input 16.8 MHz (max.) square or sine wave input
Other Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports Input/output port: 38 bits (max.)
Output port: 1 bit (max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports 34 bits (max.)
Number of ports that support universal port
multiplexer (UPMUX)
21 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Number of low-level high-current drive
outputs
8 bits (max.)
7 mA output (max.)
Number of high-level high-current drive
outputs
5 bits (max.)
56 mA output (max., Total sum of 5 bits)
Timers
Watchdog timer (WDT2) Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
16-bit timer (T16) 4 channels
Generates the SPIA master clock and the ADC12A trigger signal.
16-bit PWM timer (T16B) 1 channel
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
Supply voltage detector (SVD3)
Detection voltage VDD or external voltage (two external voltage input ports are provided.)
Detection level VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Other Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Serial interfaces
UART (UART3) 4 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function

1 OVERVIEW
1-2 Seiko Epson Corporation S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Model S1C17M12 S1C17M13
Serial interfaces
Synchronous serial interface (SPIA) 2 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
I2C (I2C) *11 channel
Baud-rate generator included
IR remote controller (REMC2)
Number of transmitter channels 1 channel
Other EL lamp drive waveform can be generated for an application example.
Seven-segment LED controller (LEDC)
LED control output Seven-segment LED outputs up to five digits (8SEG ×1–5COM(max.))
COM time-division dynamic drive control
Software configurable anode/cathode common mode and off-state pin status
Four-level brightness adjustment function
12-bit A/D converter (ADC12A)
Conversion method – Successive approximation type
Resolution 12 bits
Number of conversion channels 1 channel
Number of analog signal inputs 8 ports/channel
Multiplier/divider (COPRO2)
Arithmetic functions 16-bit ×16-bit multiplier
16-bit ×16-bit + 32-bit multiply and accumulation unit
32-bit ÷32-bit divider
Reset
#RESET pin Reset when the reset pin is set to low.
Power-on reset Reset at power on.
Brownout reset Reset when the power supply voltage drops.
Key entry reset Reset when the P00 to P01/P02/P03 keys are pressed simultaneously (can be en-
abled/disabled using a register).
Watchdog timer reset Reset when the watchdog timer overflows (can be enabled/disabled using a register).
Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level (can be enabled/
disabled using a register).
Interrupt
Non-maskable interrupt 4 systems (Reset, address misaligned interrupt, debug, NMI)
Programmable interrupt External interrupt: 1 system (8 levels)
Internal interrupt: 14 systems (8 levels)
Power supply voltage
VDD operating voltage 1.8 to 5.5 V
VDD operating voltage for Flash programming 2.4 to 5.5 V (VPP = 7.5 V external power supply is required.)
Operating temperature
Operating temperature range -40 to 85 °C
Current consumption (Typ. value)
SLEEP mode *20.3 µA (VDD = 3.6 V)
0.35 µA (VDD = 5.5 V)
IOSC = OFF, OSC3 = OFF
HALT mode 340 µA
OSC3 = 16 MHz (internal oscillator)
RUN mode 1,650 µA
OSC3 = 16 MHz (internal oscillator), CPU = OSC3 (2 wait cycles)
Shipping form
1 *3TQFP12-48PIN (P-TQFP048-0707-0.50, 7 ×7 mm, t = 1.2 mm, 0.5 mm pitch)
2 Die form (Pad pitch: 80 µm (min.))
*1 The input filter in I2C (SDA and SCL inputs) does not comply with the standard for removing noise spikes less than 50 ns.
*2 The RAM retains data even in SLEEP mode.
*3 Shown in parentheses is a JEITA package name.

1 OVERVIEW
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.2)
1.2 Block Diagram
IOSC
oscillator
EXOSC
input circuit
Clock generator
(CLG)
Power-on reset
(POR)
Power generator
(PWG)
System reset controller
(SRC)
VDD
VDD2
VD1
VSS
VSS2
FOUT
OSC3
OSC4
EXOSC
#RESET
OSC3
oscillator
Brownout reset
(BOR)
CPU core & debugger
(S1C17)
Internal RAM
2K bytes
System clock Interrupt request
Interrupt signal
DCLK
DSIO
DST2
32-bit RAM bus
Multiplier/divider
(COPRO2)
Coprocessor bus
Instruction bus
16-bit internal bus
SDA0
SCL0
EXSVD0–1
P00–07
P10–17
P20–24
P40–47
P50–54
PD0–D1
PD3–D4
PD2
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
I2C
(I2C)
1 Ch.
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
4 Ch.
TOUT00–01
CAP00–01
EXCL00–01
16-bit PWM timer
(T16B)
1 Ch.
SDI0–1
SDO0–1
SPICLK0–1
#SPISS0–1
Synchronous
serial interface
(SPIA)
2 Ch.
USIN0
USOUT0
UART
(UART3)
1 Ch.
Flash memory
16K bytes VPP
COM0–4
SEG0–7
Seven-segment
LED controller
(LEDC)
ADIN00–07
#ADTRG0
VREFA0
12-bit A/D
converter
(ADC12A)
1 Ch.
REMO
CLPLS
IR remote
controller
(REMC2)
1 Ch.
∗
*Not available in the S1C17M12.
Figure 1.2.1 S1C17M12/M13 Block Diagram

1 OVERVIEW
1-4 Seiko Epson Corporation S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
1.3 Pins
1.3.1 Pin Configuration Diagram (TQFP12-48PIN)
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
P52
VDD2
P53 P54 P00 P01 P02 P03 P04 P05 P06 P07
P52/COM2
VDD2
P53/COM3 P54/COM4
P00/UPMUX P01/UPMUX P02/UPMUX P03/UPMUX P04/UPMUX P05/UPMUX P06/UPMUX P07/UPMUX
VSS2 VPP P24 P23 P22 P21 P20 PD2 PD1 PD0 VDD #RESET
VSS2
VPP
P24/UPMUX P23/UPMUX P22/UPMUX P21/UPMUX P20/UPMUX
DCLK/PD2 DSIO/PD1 DST2/PD0 VDD #RESET
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
S1C17M12
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX
Pin name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P51
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P51/CLPLS/COM1
Figure 1.3.1.1 S1C17M12 Pin Configuration Diagram (TQFP12-48PIN)

1 OVERVIEW
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.2)
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
P52
VDD2
P53 P54 P00 P01 P02 P03 P04 P05 P06 P07
P52/COM2
VDD2
P53/COM3 P54/COM4
P00/UPMUX/ADIN07 P01/UPMUX/ADIN06 P02/UPMUX/ADIN05 P03/UPMUX/ADIN04 P04/UPMUX/ADIN03 P05/UPMUX/ADIN02 P06/UPMUX/ADIN01 P07/UPMUX/ADIN00
VSS2 VPP P24 P23 P22 P21 P20 PD2 PD1 PD0 VDD #RESET
VSS2
VPP
P24/UPMUX P23/UPMUX P22/UPMUX P21/UPMUX P20/UPMUX
DCLK/PD2 DSIO/PD1 DST2/PD0 VDD #RESET
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
S1C17M13
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/#ADTRG0/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX/VREFA0
Pin name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P51
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P51/CLPLS/COM1
Figure 1.3.1.2 S1C17M13 Pin Configuration Diagram (TQFP12-48PIN)

1 OVERVIEW
1-6 Seiko Epson Corporation S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
1.3.2 Pad Configuration Diagram (Chip)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
33
32
31
30
29
28
27
26
25
24
23
22
45 44 43 42 41 40 39 38 37 36 35 34
Y
X
(0, 0)
2.00 mm
2.28 mm
P52 P52 P52 P52
VDD2
P53 P53 P53 P53 P54 P54 P54 P54 P00 P01 P02 P03 P04 P05 P06 P07
P52/COM2 P52/COM2 P52/COM2 P52/COM2
VDD2
P53/COM3 P53/COM3 P53/COM3 P53/COM3 P54/COM4 P54/COM4 P54/COM4 P54/COM4
P00/UPMUX P01/UPMUX P02/UPMUX P03/UPMUX P04/UPMUX P05/UPMUX P06/UPMUX P07/UPMUX
VSS2
VPP P24 P23 P22 P21 P20 PD2 PD1 PD0 VDD #RESET
VSS2
VPP
P24/UPMUX P23/UPMUX P22/UPMUX P21/UPMUX P20/UPMUX
DCLK/PD2 DSIO/PD1 DST2/PD0 VDD #RESET
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX
Die No. CJxxxxxxx
∗
1
∗1∗1∗1
∗
1
Pad
name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P50
P50
P50
P51
P51
P51
P51
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P50/REMO/COM0
P50/REMO/COM0
P50/REMO/COM0
P51/CLPLS/COM1
P51/CLPLS/COM1
P51/CLPLS/COM1
P51/CLPLS/COM1
Figure 1.3.2.1 S1C17M12 Pad Configuration Diagram (Chip)
*1 These pads have the same specification. Select one pad to be used.
Pad opening: X = 68 µm, Y = 68 µm
Chip thickness: 400 µm

1 OVERVIEW
S1C17M12/M13 TECHNICAL MANUAL Seiko Epson Corporation 1-7
(Rev. 1.2)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
33
32
31
30
29
28
27
26
25
24
23
22
45 44 43 42 41 40 39 38 37 36 35 34
Y
X
(0, 0)
2.00 mm
2.28 mm
P52 P52 P52 P52
VDD2
P53 P53 P53 P53 P54 P54 P54 P54 P00 P01 P02 P03 P04 P05 P06 P07
P52/COM2 P52/COM2 P52/COM2 P52/COM2
VDD2
P53/COM3 P53/COM3 P53/COM3 P53/COM3 P54/COM4 P54/COM4 P54/COM4 P54/COM4
P00/UPMUX/ADIN07 P01/UPMUX/ADIN06 P02/UPMUX/ADIN05 P03/UPMUX/ADIN04 P04/UPMUX/ADIN03 P05/UPMUX/ADIN02 P06/UPMUX/ADIN01 P07/UPMUX/ADIN00
VSS2
VPP P24 P23 P22 P21 P20 PD2 PD1 PD0 VDD #RESET
VSS2
VPP
P24/UPMUX P23/UPMUX P22/UPMUX P21/UPMUX P20/UPMUX
DCLK/PD2 DSIO/PD1 DST2/PD0 VDD #RESET
VSS
VD1
PD4
PD3
P17
P16
P15
P14
P13
P12
P11
P10
VSS
VD1
PD4/OSC4
PD3/OSC3
P17/#ADTRG0/UPMUX
P16/FOUT/UPMUX
P15/EXCL01/UPMUX
P14/EXCL00/UPMUX
P13/EXOSC/UPMUX
P12/UPMUX/EXSVD1
P11/UPMUX/EXSVD0
P10/UPMUX/VREFA0
Pad
name
P40
P41
P42
P43
VSS2
P44
P45
P46
P47
VSS2
P50
P50
P50
P50
P51
P51
P51
P51
Port function
or signal
assignment
P40/SEG0
P41/SEG1
P42/SEG2
P43/SEG3
VSS2
P44/SEG4
P45/SEG5
P46/SEG6
P47/SEG7
VSS2
P50/REMO/COM0
P50/REMO/COM0
P50/REMO/COM0
P50/REMO/COM0
P51/CLPLS/COM1
P51/CLPLS/COM1
P51/CLPLS/COM1
P51/CLPLS/COM1
Die No. CJxxxxxxx
∗
1
∗1∗1∗1
∗
1
Figure 1.3.2.2 S1C17M13 Pad Configuration Diagram (Chip)
*1 These pads have the same specification. Select one pad to be used.
Pad opening: X = 68 µm, Y = 68 µm
Chip thickness: 400 µm
Table 1.3.2.1 S1C17M12/M13 Pad Coordinates
No. X µm Y µm No. X µm Y µm No. X µm Y µm No. X µm Y µm
1 -950.0 -911.5 22 1,051.5 -628.0 34 666.6 911.5 46 -1,051.5 810.0
2 -870.0 -911.5 23 1,051.5 -483.0 35 576.6 911.5 47 -1,051.5 730.0
3 -790.0 -911.5 24 1,051.5 -403.0 36 430.0 911.5 48 -1,051.5 650.0
4 -710.0 -911.5 25 1,051.5 -258.0 37 350.0 911.5 49 -1,051.5 570.0
5 -630.0 -911.5 26 1,051.5 -178.0 38 270.0 911.5 50 -1,051.5 490.0
6 -550.0 -911.5 27 1,051.5 -98.0 39 110.0 911.5 51 -1,051.5 410.0
7 -470.0 -911.5 28 1,051.5 -18.0 40 30.0 911.5 52 -1,051.5 330.0
8 -390.0 -911.5 29 1,051.5 62.0 41 -50.0 911.5 53 -1,051.5 250.0
9 -310.0 -911.5 30 1,051.5 207.0 42 -130.0 911.5 54 -1,051.5 170.0
10 -230.0 -911.5 31 1,051.5 287.0 43 -210.0 911.5 55 -1,051.5 90.0
11 -150.0 -911.5 32 1,051.5 433.6 44 -370.0 911.5 56 -1,051.5 5.0
12 -70.0 -911.5 33 1,051.5 523.6 45 -695.0 911.5 57 -1,051.5 -75.0
13 10.0 -911.5 58 -1,051.5 -155.0
14 175.0 -911.5 59 -1,051.5 -235.0
15 255.0 -911.5 60 -1,051.5 -315.0
16 335.0 -911.5 61 -1,051.5 -395.0
17 415.0 -911.5 62 -1,051.5 -475.0
18 495.0 -911.5 63 -1,051.5 -555.0
19 575.0 -911.5
20 655.0 -911.5
21 735.0 -911.5

1 OVERVIEW
1-8 Seiko Epson Corporation S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
1.3.3 Pin Descriptions
Symbol meanings
Assigned signal: The signal listed at the top of each pin is assigned in the initial state. The pin function must be
switched via software to assign another signal (see the “I/O Ports” chapter).
I/O: I = Input
O = Output
I/O = Input/output
P = Power supply
A = Analog signal
Hi-Z = High impedance state
Initial state: I (Pull-up) = Input with pulled up
I (Pull-down) = Input with pulled down
Hi-Z = High impedance state
O (H) = High level output
O (L) = Low level output
Tolerant fail-safe structure:
✓= Over voltage tolerant fail-safe type I/O cell included (see the “I/O Ports” chapter)
Table 1.3.3.1 Pin description
Pin/pad
name
Assigned
signal I/O Initial state
Tolerant
fail-safe
structure
Function
S1C17M12 S1C17M13
VDD VDD P – – Power supply (+), I/O power supply (except for P50–54) ✓ ✓
VDD2 VDD2 P – – I/O power supply (P50–54) ✓ ✓
VSS VSS P – – GND (except for P40–47, P50–54) ✓ ✓
VSS2 VSS2 P – – GND (P40–47, P50–54) ✓ ✓
VPP VPP P – – Power supply for Flash programming ✓ ✓
VD1 VD1 A – – VD1 regulator output ✓ ✓
#RESET #RESET I I (Pull-up) –Reset input ✓ ✓
P00 P00 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN07 A 12-bit A/D converter Ch.0 analog signal input 7 –✓
P01 P01 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN06 A 12-bit A/D converter Ch.0 analog signal input 6 –✓
P02 P02 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN05 A 12-bit A/D converter Ch.0 analog signal input 5 –✓
P03 P03 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN04 A 12-bit A/D converter Ch.0 analog signal input 4 –✓
P04 P04 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN03 A 12-bit A/D converter Ch.0 analog signal input 3 –✓
P05 P05 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN02 A 12-bit A/D converter Ch.0 analog signal input 2 –✓
P06 P06 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN01 A 12-bit A/D converter Ch.0 analog signal input 1 –✓
P07 P07 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
ADIN00 A 12-bit A/D converter Ch.0 analog signal input 0 –✓
P10 P10 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
VREFA0 A 12-bit A/D converter Ch.0 reference voltage input –✓
P11 P11 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
EXSVD0 A External power supply voltage detection input Ch.0 ✓ ✓
P12 P12 I/O Hi-Z –I/O port ✓ ✓
UPMUX I/O User-selected I/O (universal port multiplexer) ✓ ✓
EXSVD1 A External power supply voltage detection input Ch.1 ✓ ✓