Fujitsu EVB JADE--D User manual

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Manfred Ortmann
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Receiver: Info:
M. Carstens-Behrens mycable GmbH
Manual
EVB JADE-D Interface Board
Version PA4.2
October 5, 2009
http://www.fujitsu.com/emea/services/microelectronics

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Notice
The contents of this document are subject to change without notice. Customers are advised to
consult with FUJITSU sales representatives before ordering.
Any information in this document, including functional descriptions and schematic diagrams,
shall not be construed as license of the use or the exercising of any intellectual property rights,
such as patent rights or copyright or any other right of FUJITSU or any third party or does
FUJITSU warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information
contained herein.
The products described in this document are designed, developed and manufactured for
general use, including unrestricted ordinary industrial use, general office use, personal use, and
household use but are not designed, developed and manufactured for use accompanying fatal
risks or dangers that, unless extremely high safety levels are ensured, could have a serious
effect to the public and could lead directly to death, personal injury, severe physical damage or
other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control,
mass transport control, medical life support system, missile launch control in weapon systems),
or (2) for use requiring extremely high reliability (i.e., submarine or satellite technology). Please
note that FUJITSU will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by the Japanese government will be required for export of those products from
Japan.
All rights reserved and Copyright ©FUJITSU LIMITED 2009

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Developer’s Manual for EVB JADE-D Interface Board
Summary
This manual provides detailed technical information for system architects, hardware and
software developers, who work with the EVB JADE-D Interface board version PA 4 for
evaluation and development purpose.
Enclosures
None.
Product Information
A JADE Evaluation board was developed to demonstrate the versatile features from the JADE
and its interfaces.
The JADE together with DDR SDRAM and Flash memory is implemented as module which is
called XXSvideo and can be plugged on the JADE Evaluation board.
Now also a module with the JADE-D is available. It is called XXSvideo-D.
For using the XXSvideo-D module with the JADE Evaluation board the EVB JADE-D
Interface board was developed.

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Revision History
Revision Date Sign Description
PA2.1 2009-03-02 mo Document setup
PA2.2 2009-03-09 mo Pinning of APIX signals
PA3.1 2009-04-23 mo Documentation after finishing PCB
PA3.2 2009-05-15 mo Pin table of X804 added
PA3.3 2009-07-06 mo Pictures added
PA4.1 2009-08-14 mo PCB revision PA4
video connector X804
APIX connector X802
PA4.2 2009-10-05 mo Picture change
Contact Information
mycable GmbH
Michael Carstens-Behrens
( hardware and commercial )
Email [e-mail]
Tel. [phone]
mycable GmbH
Carsten Schneider ( Software )
Email [e-mail]
mycable GmbH
Manfred Ortmann ( Hardware )
Email [e-mail]

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Table of Contents
1 OVERVIEW....................................................................................................................6
1.1 Manual Scope........................................................................................................6
1.2 Putting into Operation.............................................................................................6
2 EVB JADE-D INTERFACE BOARD...........................................................................7
2.1 System Architecture...............................................................................................7
2.2 Function Units........................................................................................................9
2.2.1 XXSvideo-D Module.....................................................................................10
2.2.2 XXSvideo-D Interface...................................................................................11
2.2.3 XXSvideo Interface.......................................................................................21
2.2.4 Configuration................................................................................................30
2.2.5 ADC Interface...............................................................................................30
2.2.5 I2C and Host SPI Interface..........................................................................32
2.2.6 32 bit Flash Memory.....................................................................................33
2.2.7 USB..............................................................................................................33
2.2.8 Audio CODEC..............................................................................................34
2.2.9 APIX.............................................................................................................35
2.2.10 Video Output..............................................................................................37
2.2.11 RGB Input..................................................................................................40
2.3 Hardware Variants................................................................................................41
2.4 Placement of Components...................................................................................42
2.5 Mechanical Dimensions........................................................................................44

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1 Overview
1.1 Manual Scope
This manual provides detailed technical information about the EVB JADE-D Interface board for
system architects, hardware and software developers covering:
•System architecture description and users manual
•Hardware architecture
•Mechanical information
•References to further information like design data, data sheets, software documentation
It is the engineer’s reference for evaluation, system development and prototyping based on the
board. This document covers all available hardware versions regarding their configuration
options and revision state.
1.2 Putting into Operation
Plug the EVB JADE-D Interface board on a board only if the power supply is off !

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2 EVB JADE-D Interface Board
2.1 System Architecture
Picture 2-2 shows the top side of the EVB JADE-D Interface board and picture 2-3 shows the
bottom side.
Pic. 2-2: EVB JADE-D Interface board top side

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Pic. 2-3: EVB JADE-D Interface board bottom side

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2.2 Function Units
Overview in the available interfaces:
–RGB Input
–32 bit Flash memory
–USB
–Audio
–Connectors
–ADC
–Host SPI
–I2C

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2.2.1XXSvideo-DModule
Pic. 2-4: XXSvideo-D Module top side
Pic. 2-5: XXSvideo-D Module bottom side

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2.2.2XXSvideo-DInterface
Pic. 2-6: XXSvideo-D interface
The 120-pin 0.5 mm connectors X101 ( CPU signals side ) and X201 ( IO signals side ) QTH-
060-05-F-D-A from Samtec are the interfaces to the XXSvideo-D module with the JADE-D and
memory.
Detailed information on the XXSvideo-D module see the manual to this board.
Do not plug the XXSvideo-D module or EVB-JADE-D when the power supply is on !
Following tables shows the assignment from pins, signals and function of these connectors.
Mostly the function is no further elucidated and only the name of the connected pin of the
JADE-D is stated. For further details see the datasheet from the JADE-D and the schematic of
the XXSvideo-D module.
The signal order is the result of optimisation for a good layout of the XXSvideo-D module.

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Pin Signal Function
1 VCC33 Power Supply 3.3 V for XXSvideo-D
2 VCC33 Power Supply 3.3 V for XXSvideo-D
3 MEM_XCS4 Chip Select 4 for Flash Memory
4 VCC33 Power Supply 3.3 V for XXSvideo-D
5 CPU_D15 Data
6 VCC33 Power Supply 3.3 V for XXSvideo-D
7 CPU_A1 Address
8 GND Ground
9 CPU_A3 Address
10 CPU_D0 Data
11 CPU_A4 Address
12 CPU_D3 Data
13 CPU_A7 Address
14 CPU_D4 Data
15 CPU_A8 Address
16 CPU_D7 Data
17 CPU_A11 Address
18 CPU_D8 Data
19 CPU_A12 Address
20 CPU_D11 Data
21 CPU_A15 Address
22 CPU_D12 Data
23 CPU_A16 Address
24 CPU_D14 Data
25 CPU_A19 Address
26 CPU_D1 Data
27 CPU_A20 Address
28 CPU_D2 Data
29 CPU_A23 Address
30 CPU_D5 Data
31 MEM_XWR1 Write Strobe
32 CPU_D6 Data
33 MEM_XRD Read Strobe
34 CPU_D9 Data

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Pin Signal Function
35 MEM_XCS2 Chip Select 2
36 CPU_D10 Data
37 MEM_XCS0 Chip Select 0
38 CPU_D13 Data
39 CPU_A22 Address
40 CPU_A2 Address
41 CPU_A21 Address
42 CPU_A6 Address
43 MEM_XWR0 Write Strobe
44 CPU_A5 Address
45 CPU_A24 Address
46 CPU_A10 Address
47 MEM_RDY Ready input for slow device
48 CPU_A9 Address
49 APIXGND Ground for APIX signals
50 CPU_A14 Address
51 APIX_SDIN2 Serial Data Input 1 ( positive )
52 CPU_A13 Address
53 APIX_SDIN3 Serial Data Input 0 ( negative )
54 CPU_A18 Address
55 APIXGND Ground for APIX signals
56 CPU_A17 Address
57 APIX_SDOUT3 Serial Data Output 1 ( negative )
58 HOST_SPI_DI HOST SPI Data Input ( MOSI )
59 APIX_SDOUT2 Serial Data Output 1 ( positive )
60 HOST_SPI_DO HOST SPI Data Output ( MISO )
61 APIX_SDIN1 Serial Data Input 0 ( negative )
62 HOST_SPI_SS HOST SPI Slave Select
63 APIX_SDIN0 Serial Data Input 0 ( positive )
64 HOST_SPI_SCK HOST SPI Clock
65 APIXGND Ground for APIX signals
66 DCLKIN1 Video output interface 1 dot clock input
67 APIX_SDOUT1 Serial Data Output 0 ( negative )
68 SPI_DI0 SPI0 Master Data Input ( MISO )
69 APIX_SDOUT0 Serial Data Output 0 ( positive )
70 SPI_DO0 SPI0 Master Data Output ( MOSI )

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Pin Signal Function
71 APIXGND Ground for APIX signals
72 SPI_SS0 SPI0 Master Slave Select
73 VIN0_7 Video Capture Data Input 0 bit 7
74 SPI_SCK0 SPI0 Master serial clock
75 VIN0_4 Video Capture Data Input 0 bit 4
76 TSG_R_4 TCON Timing Signal
77 VIN0_3 Video Capture Data Input 0 bit 3
78 TSG_R_5 TCON Timing Signal
79 VIN0_5 Video Capture Data Input 0 bit 5
80 TSG_R_6 TCON Timing Signal
81 VIN0_6 Video Capture Data Input 0 bit 6
82 DCLKP RSDS Clock Output CLKp, in TTL Mode
83 VIN0_1 Video Capture Data Input 0 bit 1
84 DCLKN RSDS Clock Output CLKn, in TTL Mode
85 VIN0_2 Video Capture Data Input 0 bit 2
86 DE0 TCON Bypass: DE/CSYNC of DISPL0, TCON:TSG_2
87 VIN0_8 Video Capture 0 Clock
88 HSYNC0 Video Capture 0 Horizontal Syncronisation
89 VIN0_0 Video Capture Data Input 0 bit 0
90 GVO0 Video output interface 0 graphics / video switch
91 TSG_R_7 TCON Timing Signal
92
VSYNC0 TCON Bypass: Video output interface 0 vertical sync
output vertical sync input in external sync mode
93 ATST_R APIX analog Test Clock
94 DOUTB1_R_5 Digital RGB output1 with serial resistor
95 PWMO2 PWM Output
96 DOUTB1_R_2 Digital RGB output1 with serial resistor
97 DOUTB1_R_3 Digital RGB output1 with serial resistor
98 DOUTG1_R_3 Digital RGB output1 with serial resistor
99 DOUTB1_R_4 Digital RGB output1 with serial resistor
100 DOUTB1_R_6 Digital RGB output1 with serial resistor
101 DOUTB1_R_7 Digital RGB output1 with serial resistor
102 DOUTG1_R_7 Digital RGB output1 with serial resistor
103 DOUTG1_R_2 Digital RGB output1 with serial resistor
104 DOUTG1_R_4 Digital RGB output1 with serial resistor
105 DOUTG1_R_5 Digital RGB output1 with serial resistor

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Pin Signal Function
106 DOUTR1_R_5 Digital RGB output1 with serial resistor
107 DOUTG1_R_6 Digital RGB output1 with serial resistor
108 DOUTR1_R_2 Digital RGB output1 with serial resistor
109 DOUTR1_R_3 Digital RGB output1 with serial resistor
110 DCLKO1_R Video output interface 1 dot clock output w. s. r.
111 DOUTR1_R_4 Digital RGB output1 with serial resistor
112 GV1 Video output interface 1 graphics / video switch
113 DOUTR1_R_7 Digital RGB output1 with serial resistor
114 VINHSYNC0 Video Capture 0 Horizontal Syncronisation
115 DOUTR1_R_6 Digital RGB output1 with serial resistor
116 VINVSYNC1 Video Capture 1 Vertical Syncronisation
117
VSYNC1 Video output interface 1 vertical sync output
vertical sync input in external sync mode
118 VINFID0 Video input 0 field identification signal
119
HSYNC1 Video output interface 1 horizontal sync output
Horizontal sync input in external sync mode
120 DE1 DE / CSYNC
121 GND Ground at center pin
122 GND Ground at center pin
123 GND Ground at center pin
124 GND Ground at center pin
125 GND Ground at center pin
126 GND Ground at center pin
127 GND Ground at center pin
128 GND Ground at center pin
Tab. 2-1: Pin assignment of connector X101, CPU signals side

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Following table shows the assignment from pins, signals and function of connector X201 I/O
signals side:
Pin Signal Function
1 VCC33 Power Supply 3.3 V for XXSvideo-D
2 VCC33 Power Supply 3.3 V for XXSvideo-D
3 VCC33 Power Supply 3.3 V for XXSvideo-D
4 VCC33 Power Supply 3.3 V for XXSvideo-D
5 GND Ground
6 GND Ground
7 INT_A0 Interrupt 0
8 I2C_SDA0 I2C 0 Data
9 INT_A1 Interrupt 1
10 I2C_SCL0 I2C 0 Clock
11 I2C_SDA1 I2C 1 Data
12 I2C_SCL1 I2C 1 Clock
13 INT_A3 Interrupt 3
14 SPI_DO1 SPI1 Master Data Output ( MOSI )
15 INT_A2 Interrupt 2
16 SPI_DI1 SPI1 Master Data Input ( MISO )
17 TSG_R_10 TCON Timing Signal 10
18 TSG_R_8 TCON Timing Signal 8
19 TSG_R_11 TCON Timing Signal 11
20 TSG_R_9 TCON Timing Signal 9
21 SPI_SCK1 SPI1 Master serial clock
22 UART_SOUT1 UART 1 serial output
23 SPI_SS1 SPI1 Master Slave Select
24 UART_SIN1 UART 1serial input
25 UART_SIN2 UART 2 serial input
26 UART_CTS0# UART 0 Clear to send
27 UART_SOUT2 UART 2 serial output
28 UART_SIN0 UART 0 serial input
29 ADCGND Ground for ADC signals
30 UART_RTS0# UART0 Request to send
31 AD_VRL1 Reference voltage "L" input
32 UART_SOUT0 UART 0 serial output
33 AD_VR1 Reference output

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Pin Signal Function
34 ADCGND Ground for ADC signals
35 AD_VRL0 Reference voltage "L" input
36 AD_VRH1 Reference voltage "H" input 1
37 AD_VR0 Reference output
38 AD_VIN1 A/D analog input, channel 1
39 AD_VIN0 A/D analog input, channel 0
40 AD_VRH0 Reference voltage "H" input 0
41 GND Ground
42
OPT_PIN_0 A/D analog input, channel 2 or
TESTMODE 2
43
DISP_P_R_10 RSDS Output 10p, in TTL Mode
Default=DOUTB0_4
44
OPT_PIN_1 A/D analog input, channel 3 or
VINITHI
45
DISP_N_R_10 RSDS Output 10n, in TTL Mode
Default=DOUTB0_5
46 VCC12 1.2 V from CPU core voltage regulator
47
DISP_P_R_7 RSDS Output 7p, in TTL Mode
Default=DOUTG0_6
48 VCC12 1.2 V from CPU core voltage regulator
49
DISP_N_R_7 RSDS Output 7n, in TTL Mode
Default=DOUTG0_7
50
DISP_P_R_0 RSDS Output 0p, in TTL Mode
Default=DOUTR0_0
51
DISP_P_R_8 RSDS Output 8p, in TTL Mode
Default=DOUTB0_0
52
DISP_N_R_0 RSDS Output 0n, in TTL Mode
Default=DOUTR0_1
53
DISP_N_R_8 RSDS Output 8n, in TTL Mode
Default=DOUTB0_1
54
DISP_P_R_1 RSDS Output 1p, in TTL Mode
Default=DOUTR0_2
55
DISP_P_R_9 RSDS Output 9p, in TTL Mode
Default=DOUTB0_2
56
DISP_N_R_1 RSDS Output 1n, in TTL Mode
Default=DOUTR0_3
57
DISP_N_R_9 RSDS Output 9n, in TTL Mode
Default=DOUTB0_3
58
DISP_P_R_2 RSDS Output 2p, in TTL Mode
Default=DOUTR0_4

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Pin Signal Function
59 CAN_TX0 CAN Transmission 0
60
DISP_N_R_2 RSDS Output 2n, in TTL Mode
Default=DOUTR0_5
61 CAN_RX0 CAN Reception 0
62
DISP_P_R_3 RSDS Output 3p, in TTL Mode
Default=DOUTR0_6
63
DISP_P_R_11 RSDS Output 11p, in TTL Mode
Default=DOUTB0_6
64
DISP_N_R_3 RSDS Output 3n, in TTL Mode
Default=DOUTR0_7
65
DISP_N_R_11 RSDS Output 11n, in TTL Mode
Default=DOUTB0_7
66 CAN_RX1 CAN Reception 1
67 TSG_R_12 TCON Timing Signal 12
68 CAN_TX1 CAN Transmission 1
69 VIN1_9 Video Capture Data Input 1 bit 6
70
DISP_P_R_5 RSDS Output 5p, in TTL Mode
Default=DOUTG0_2
71 I2S_WS
72
DISP_N_R_5 RSDS Output 5n, in TTL Mode
Default=DOUTG0_3
73 VIN1_3 Video Capture Data Input 1 bit 3
74
DISP_P_R_6 RSDS Output 6p, in TTL Mode
Default=DOUTG0_4
75 VIN1_0 Video Capture Data Input 1 bit 0
76
DISP_N_R_6 RSDS Output 6n, in TTL Mode
Default=DOUTG0_5
77 VIN1_10 Video Capture 1 Vertical Syncronisation
78
DISP_P_R_4 RSDS Output 4p, in TTL Mode
Default=DOUTG0_0
79 I2S_SDI Serial Data Input
80
DISP_N_R_4 RSDS Output 4n, in TTL Mode
Default=DOUTG0_1
81 VIN1_4 Video Capture Data Input 1 bit 4
82 PWMO0 PWM Output
83 VIN1_1 Video Capture Data Input 1 bit 1
84 I2S_ECLK I2S Clock Input (
85 VIN1_7 Video Capture Data Input 1 bit 7
86 PWMO1 PWM Output

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Pin Signal Function
87 VIN1_5 Video Capture Data Input 1 bit 5
88 I2S_SCK I2S Clock Output
89 VIN1_6 Video Capture Data Input 1 bit 6
90 I2S_SDO Serial Data Output
91 MLB_SIG Media LB Control Pin
92 CCLK1 Video Capture 1 Clock
93 MLB_CLK Media LB Clock Pin
94 VIN1_2 Video Capture Data Input 1 bit 2
95 MLB_DAT Media LB Data Pin
96 MPX_MODE_1_0 Multiplex Mode Pin
97 RTCK Return test clock
98 MPX_MODE_1_1 Multiplex Mode Pin
99 TCK JTAG Test Clock
100 VINFID1 Video input 1 field identification signal
101 TMS JTAG TMS
102
JTAGSEL JTAG Selector ( 0 = Fujitsu TAP Controller, 1
= ARM Tap Controller )
103 TDO JTAG TDO
104 XSRST ICE System reset
105
TRACEDATA_0 Trace data used by the trace tool such as
RealView supplied by ARM Limited.
106 XTRST Test reset
107
TRACEDATA_2 Trace data used by the trace tool such as
RealView supplied by ARM Limited.
108 TDI JTAG TDI
109 TRACECTL TRACE control
110 VCC_CORE_PG Power good CPU core voltage
111
TRACEDATA_1 Trace data used by the trace tool such as
RealView supplied by ARM Limited.
112 MR# Master reset input
113 GND Ground
114 RESET# Reset output
115 GND Ground
116 WDI Watch dog input
117
TRACEDATA_3 Trace data used by the trace tool such as
RealView supplied by ARM Limited.

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Pin Signal Function
118
VCC18 1.8 V, regulated on XXSvideo-D for DDR2
SDRAM
119 TRACECLK Trace clock
120
VCC18 1.8 V, regulated on XXSvideo-D for DDR2
SDRAM
121 GND Ground at center pin
122 GND Ground at center pin
123 GND Ground at center pin
124 GND Ground at center pin
125 GND Ground at center pin
126 GND Ground at center pin
127 GND Ground at center pin
128 GND Ground at center pin
Tab. 2-2: Pin assignment of connector X201, I/O signals side